diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/mips64/mips64/cache_r5k.S | 82 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/context.S | 34 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/fp.S | 724 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/tlbhandler.S | 52 |
4 files changed, 446 insertions, 446 deletions
diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S index a0a2b51a81f..e84a1890b94 100644 --- a/sys/arch/mips64/mips64/cache_r5k.S +++ b/sys/arch/mips64/mips64/cache_r5k.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r5k.S,v 1.6 2004/09/10 08:58:27 pefo Exp $ */ +/* $OpenBSD: cache_r5k.S,v 1.7 2004/09/10 09:32:13 pefo Exp $ */ /* * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se) @@ -162,7 +162,7 @@ * primary cache associativity. * * Allocation: - * ta4, ta5 ta6 used to hold I and D set size and Alias mask. + * ta0, ta1 ta2 used to hold I and D set size and Alias mask. * *---------------------------------------------------------------------------- */ @@ -174,7 +174,7 @@ LEAF(Mips5k_ConfigCache, 0) srl t1, v0, 9 # Get I cache size. and t1, 3 li t2, 4096 - sllv ta4, t2, t1 # ta4 = Initial I set size. + sllv ta0, t2, t1 # ta0 = Initial I set size. and t2, v0, 0x20 srl t2, t2, 1 # Get I cache line size. @@ -184,15 +184,15 @@ LEAF(Mips5k_ConfigCache, 0) srl t1, v0, 6 # Get D cache size. and t1, 3 li t2, 4096 # Fixed page size. - sllv ta5, t2, t1 + sllv ta1, t2, t1 and t2, v0, 0x10 addu t2, t2, 16 # Get D cache line size. sw t2, CpuPrimaryDataCacheLSize li t2, CTYPE_2WAY # Assume two way cache - li ta6, 0 # Secondary size 0. - li ta7, 0 # Tertiary size 0. + li ta2, 0 # Secondary size 0. + li ta3, 0 # Tertiary size 0. and v1, 0xff00 # Recognize CPU's with li t1, (MIPS_R4600 << 8) # N way L1 caches only. @@ -217,7 +217,7 @@ LEAF(Mips5k_ConfigCache, 0) Conf5K: # R5000 type, check for L2 cache and t1, v0, CF_5_SC bnez t1, ConfResult # not enabled - li ta6, 0 # set size to 0. + li ta2, 0 # set size to 0. li t3, CF_5_SS and t1, t3, v0 @@ -227,12 +227,12 @@ Conf5K: # R5000 type, check for L2 cache or t2, CTYPE_HAS_XL2 # External L2 present. li t3, CF_5_SE # Set SE in conf or v0, t3 # Update config register - li ta6, 512*1024 # 512k per 'click'. - sll ta6, t1 + li ta2, 512*1024 # 512k per 'click'. + sll ta2, t1 mtc0 v0, COP_0_CONFIG # Enable L2 cache LA t0, KSEG0_BASE - PTR_ADDU t1, t0, ta6 + PTR_ADDU t1, t0, ta2 1: cache InvalidateSecondaryPage, 0(t0) PTR_ADDU t0, 128*32 @@ -247,7 +247,7 @@ Conf5K: # R5000 type, check for L2 cache Conf52K: # R5200 type, check for L2 cache and t1, v0, CF_52_SC bnez t1, ConfResult # not present - li ta6, 0 # set size to 0. + li ta2, 0 # set size to 0. li t3, CF_52_SS and t1, t3, v0 @@ -257,16 +257,16 @@ Conf52K: # R5200 type, check for L2 cache or t2, CTYPE_HAS_XL2 # External L2 present. li t3, CF_5_SE # Set SE in conf or v0, t3 # Update config register - li ta6, 512*1024 # 512k per 'click'. + li ta2, 512*1024 # 512k per 'click'. lw t3, CpuExternalCacheOn # Check if disabled bnez t3, ConfResult # No use it. - sll ta6, t1 + sll ta2, t1 and t2, ~CTYPE_HAS_XL2 li t1, ~CF_52_SE # Clear SE in conf and v0, t1 # Update config register b ConfResult - li ta6, 0 # L2 cache disabled + li ta2, 0 # L2 cache disabled #---- RM7K ----------------------------- @@ -274,11 +274,11 @@ Conf7K: # RM7000, check for L2 and L3 cache li t2, CTYPE_4WAY # 4-way cache and t1, v0, CF_7_TC bnez t1, Conf7KL2 # No L3 cache if set - li ta7, 0 # Set size = 0 + li ta3, 0 # Set size = 0 - lw ta7, CpuTertiaryCacheSize + lw ta3, CpuTertiaryCacheSize and t2, ~CTYPE_HAS_XL3 - beqz ta7, Conf7KL2 # No L3 cache present + beqz ta3, Conf7KL2 # No L3 cache present nop or t2, CTYPE_HAS_XL3 @@ -289,17 +289,17 @@ Conf7K: # RM7000, check for L2 and L3 cache and v0, ~CF_7_TE # Clear TE in conf mtc0 v0, COP_0_CONFIG # establish any new config NOP10 - li ta7, 0 # L3 cache disabled + li ta3, 0 # L3 cache disabled Conf7KL2: and t1, v0, CF_7_SC # check for L2 cache bnez t1, ConfResult - li ta6, 0 # No L2? + li ta2, 0 # No L2? or t2, CTYPE_HAS_IL2 # L2 is on chip lw t3, CpuOnboardCacheOn # Check if disabled bnez t3, ConfResult # No, use it - li ta6, 256*1024 # size = 256k + li ta2, 256*1024 # size = 256k /* Sync on chip L2 */ @@ -317,11 +317,11 @@ Conf7KL2: mtc0 v0, COP_0_CONFIG # establish any new config NOP10 b ConfResult - li ta6, 0 # L2 cache disabled + li ta2, 0 # L2 cache disabled /* - * Get here with t2 = Cache type, ta4 = L1 I size, ta5 = L1 D size. - * ta6 = secondary size, ta7 = tertiary size. + * Get here with t2 = Cache type, ta0 = L1 I size, ta1 = L1 D size. + * ta2 = secondary size, ta3 = tertiary size. */ ConfResult: sw v0, CpuConfigRegister @@ -332,21 +332,21 @@ ConfResult: sw t2, CpuNWayCache srl t2, 1 # get div shift for set size. - sw ta6, CpuSecondaryCacheSize - sw ta7, CpuTertiaryCacheSize + sw ta2, CpuSecondaryCacheSize + sw ta3, CpuTertiaryCacheSize - addu t1, ta4, -1 # Use icache for alias mask + addu t1, ta0, -1 # Use icache for alias mask srl t1, t2 # Some cpus have different and t1, ~(NBPG - 1) # i and d cache sizes... sw t1, CpuCacheAliasMask - sw ta4, CpuPrimaryInstCacheSize # store cache size. - srl ta4, t2 # calculate set size. - sw ta4, CpuPrimaryInstSetSize + sw ta0, CpuPrimaryInstCacheSize # store cache size. + srl ta0, t2 # calculate set size. + sw ta0, CpuPrimaryInstSetSize - sw ta5, CpuPrimaryDataCacheSize # store cache size. - srl ta5, t2 # calculate set size. - sw ta5, CpuPrimaryDataSetSize + sw ta1, CpuPrimaryDataCacheSize # store cache size. + srl ta1, t2 # calculate set size. + sw ta1, CpuPrimaryDataSetSize and v0, 0xfffffff8 or v0, 0x00000003 # set cachable writeback kseg0 @@ -424,11 +424,11 @@ LEAF(Mips5k_SyncCache, 0) 3: LA t3, KSEG0_BASE - lw ta4, CpuSecondaryCacheSize + lw ta0, CpuSecondaryCacheSize 10: cache IndexWBInvalidate_S, 0(t3) - PTR_SUBU ta4, 32 # Fixed cache line size. - bgtz ta4, 10b + PTR_SUBU ta0, 32 # Fixed cache line size. + bgtz ta0, 10b PTR_ADDU t3, 32 /* Do off chip L2 if present */ @@ -440,11 +440,11 @@ LEAF(Mips5k_SyncCache, 0) mtc0 zero, COP_0_TAG_LO LA t3, KSEG0_BASE - lw ta4, CpuSecondaryCacheSize + lw ta0, CpuSecondaryCacheSize 21: cache InvalidateSecondaryPage, 0(t3) - PTR_SUBU ta4, 4096 # Fixed cache page size. - bgtz ta4, 21b + PTR_SUBU ta0, 4096 # Fixed cache page size. + bgtz ta0, 21b PTR_ADDU t3, 4096 /* Do off chip L3 if present */ @@ -456,11 +456,11 @@ LEAF(Mips5k_SyncCache, 0) mtc0 zero, COP_0_TAG_LO LA t3, KSEG0_BASE - lw ta4, CpuTertiaryCacheSize + lw ta0, CpuTertiaryCacheSize 31: cache InvalidatePage_T, 0(t3) - PTR_SUBU ta4, 4096 # Fixed cache page size. - bgtz ta4, 31b + PTR_SUBU ta0, 4096 # Fixed cache page size. + bgtz ta0, 31b PTR_ADDU t3, 4096 99: diff --git a/sys/arch/mips64/mips64/context.S b/sys/arch/mips64/mips64/context.S index 490ce7ad7a6..b0e42c7557b 100644 --- a/sys/arch/mips64/mips64/context.S +++ b/sys/arch/mips64/mips64/context.S @@ -1,4 +1,4 @@ -/* $OpenBSD: context.S,v 1.5 2004/09/10 08:58:27 pefo Exp $ */ +/* $OpenBSD: context.S,v 1.6 2004/09/10 09:32:13 pefo Exp $ */ /* * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -336,14 +336,14 @@ sw1: ctx1: mtc0 zero, COP_0_TLB_INDEX dmtc0 v0, COP_0_TLB_HI - lw ta4, 0(t1) - lw ta5, 4(t1) - dsll ta4, ta4, 34 - dsrl ta4, ta4, 34 - dsll ta5, ta5, 34 - dsrl ta5, ta5, 34 - dmtc0 ta4, COP_0_TLB_LO0 - dmtc0 ta5, COP_0_TLB_LO1 + lw ta0, 0(t1) + lw ta1, 4(t1) + dsll ta0, ta0, 34 + dsrl ta0, ta0, 34 + dsll ta1, ta1, 34 + dsrl ta1, ta1, 34 + dmtc0 ta0, COP_0_TLB_LO0 + dmtc0 ta1, COP_0_TLB_LO1 nop PTR_ADDU v0, 2*NBPG nop @@ -352,14 +352,14 @@ ctx1: #if (UPAGES != 2) dmtc0 v0, COP_0_TLB_HI # init high entry (tlbid) - lw ta4, 8(t1) - lw ta5, 12(t1) - dsll ta4, ta4, 34 - dsrl ta4, ta4, 34 + lw ta0, 8(t1) + lw ta1, 12(t1) + dsll ta0, ta0, 34 + dsrl ta0, ta0, 34 tlbp nop - dsll ta5, ta5, 34 - dsrl ta5, ta5, 34 + dsll ta1, ta1, 34 + dsrl ta1, ta1, 34 mfc0 t0, COP_0_TLB_INDEX nop bltz t0, ctx2 # not in tlb @@ -380,8 +380,8 @@ ctx1: ctx2: mtc0 t2, COP_0_TLB_INDEX dmtc0 v0, COP_0_TLB_HI - dmtc0 ta4, COP_0_TLB_LO0 - dmtc0 ta5, COP_0_TLB_LO1 + dmtc0 ta0, COP_0_TLB_LO0 + dmtc0 ta1, COP_0_TLB_LO1 nop nop nop diff --git a/sys/arch/mips64/mips64/fp.S b/sys/arch/mips64/mips64/fp.S index 0790bc857ad..ce088991c7a 100644 --- a/sys/arch/mips64/mips64/fp.S +++ b/sys/arch/mips64/mips64/fp.S @@ -1,4 +1,4 @@ -/* $OpenBSD: fp.S,v 1.4 2004/09/10 08:58:27 pefo Exp $ */ +/* $OpenBSD: fp.S,v 1.5 2004/09/10 09:32:13 pefo Exp $ */ /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)fp.s 8.1 (Berkeley) 6/10/93 - * $Id: fp.S,v 1.4 2004/09/10 08:58:27 pefo Exp $ + * $Id: fp.S,v 1.5 2004/09/10 09:32:13 pefo Exp $ */ /* @@ -638,7 +638,7 @@ func_fmt_tbl: */ sub_s: jal get_ft_fs_s - xor ta4, ta4, 1 # negate FT sign bit + xor ta0, ta0, 1 # negate FT sign bit b add_sub_s /* * Single precision add. @@ -647,38 +647,38 @@ add_s: jal get_ft_fs_s add_sub_s: bne t1, SEXP_INF, 1f # is FS an infinity? - bne ta5, SEXP_INF, result_fs_s # if FT is not inf, result=FS + bne ta1, SEXP_INF, result_fs_s # if FT is not inf, result=FS bne t2, zero, result_fs_s # if FS is NAN, result is FS - bne ta6, zero, result_ft_s # if FT is NAN, result is FT - bne t0, ta4, invalid_s # both infinities same sign? + bne ta2, zero, result_ft_s # if FT is NAN, result is FT + bne t0, ta0, invalid_s # both infinities same sign? b result_fs_s # result is in FS 1: - beq ta5, SEXP_INF, result_ft_s # if FT is inf, result=FT + beq ta1, SEXP_INF, result_ft_s # if FT is inf, result=FT bne t1, zero, 4f # is FS a denormalized num? beq t2, zero, 3f # is FS zero? - bne ta5, zero, 2f # is FT a denormalized num? - beq ta6, zero, result_fs_s # FT is zero, result=FS + bne ta1, zero, 2f # is FT a denormalized num? + beq ta2, zero, result_fs_s # FT is zero, result=FS jal renorm_fs_s jal renorm_ft_s b 5f 2: jal renorm_fs_s - subu ta5, ta5, SEXP_BIAS # unbias FT exponent - or ta6, ta6, SIMPL_ONE # set implied one bit + subu ta1, ta1, SEXP_BIAS # unbias FT exponent + or ta2, ta2, SIMPL_ONE # set implied one bit b 5f 3: - bne ta5, zero, result_ft_s # if FT != 0, result=FT - bne ta6, zero, result_ft_s + bne ta1, zero, result_ft_s # if FT != 0, result=FT + bne ta2, zero, result_ft_s and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, ta4 # compute result sign + or t0, t0, ta0 # compute result sign b result_fs_s 1: - and t0, t0, ta4 # compute result sign + and t0, t0, ta0 # compute result sign b result_fs_s 4: - bne ta5, zero, 2f # is FT a denormalized num? - beq ta6, zero, result_fs_s # FT is zero, result=FS + bne ta1, zero, 2f # is FT a denormalized num? + beq ta2, zero, result_fs_s # FT is zero, result=FS subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit jal renorm_ft_s @@ -686,15 +686,15 @@ add_sub_s: 2: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit - subu ta5, ta5, SEXP_BIAS # unbias FT exponent - or ta6, ta6, SIMPL_ONE # set implied one bit + subu ta1, ta1, SEXP_BIAS # unbias FT exponent + or ta2, ta2, SIMPL_ONE # set implied one bit /* * Perform the addition. */ 5: move t8, zero # no shifted bits (sticky reg) - beq t1, ta5, 4f # no shift needed - subu v0, t1, ta5 # v0 = difference of exponents + beq t1, ta1, 4f # no shift needed + subu v0, t1, ta1 # v0 = difference of exponents move v1, v0 # v1 = abs(difference) bge v0, zero, 1f negu v1 @@ -702,50 +702,50 @@ add_sub_s: ble v1, SFRAC_BITS+2, 2f # is difference too great? li t8, STICKYBIT # set the sticky bit bge v0, zero, 1f # check which exp is larger - move t1, ta5 # result exp is FTs + move t1, ta1 # result exp is FTs move t2, zero # FSs fraction shifted is zero b 4f 1: - move ta6, zero # FTs fraction shifted is zero + move ta2, zero # FTs fraction shifted is zero b 4f 2: li t9, 32 # compute 32 - abs(exp diff) subu t9, t9, v1 bgt v0, zero, 3f # if FS > FT, shift FTs frac - move t1, ta5 # FT > FS, result exp is FTs + move t1, ta1 # FT > FS, result exp is FTs sll t8, t2, t9 # save bits shifted out srl t2, t2, v1 # shift FSs fraction b 4f 3: - sll t8, ta6, t9 # save bits shifted out - srl ta6, ta6, v1 # shift FTs fraction + sll t8, ta2, t9 # save bits shifted out + srl ta2, ta2, v1 # shift FTs fraction 4: - bne t0, ta4, 1f # if signs differ, subtract - addu t2, t2, ta6 # add fractions + bne t0, ta0, 1f # if signs differ, subtract + addu t2, t2, ta2 # add fractions b norm_s 1: - blt t2, ta6, 3f # subtract larger from smaller - bne t2, ta6, 2f # if same, result=0 + blt t2, ta2, 3f # subtract larger from smaller + bne t2, ta2, 2f # if same, result=0 move t1, zero # result=0 move t2, zero and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, ta4 # compute result sign + or t0, t0, ta0 # compute result sign b result_fs_s 1: - and t0, t0, ta4 # compute result sign + and t0, t0, ta0 # compute result sign b result_fs_s 2: - sltu t9, zero, t8 # compute t2:zero - ta6:t8 + sltu t9, zero, t8 # compute t2:zero - ta2:t8 subu t8, zero, t8 - subu t2, t2, ta6 # subtract fractions + subu t2, t2, ta2 # subtract fractions subu t2, t2, t9 # subtract barrow b norm_s 3: - move t0, ta4 # sign of result = FTs - sltu t9, zero, t8 # compute ta6:zero - t2:t8 + move t0, ta0 # sign of result = FTs + sltu t9, zero, t8 # compute ta2:zero - t2:t8 subu t8, zero, t8 - subu t2, ta6, t2 # subtract fractions + subu t2, ta2, t2 # subtract fractions subu t2, t2, t9 # subtract barrow b norm_s @@ -754,7 +754,7 @@ add_sub_s: */ sub_d: jal get_ft_fs_d - xor ta4, ta4, 1 # negate sign bit + xor ta0, ta0, 1 # negate sign bit b add_sub_d /* * Double precision add. @@ -763,46 +763,46 @@ add_d: jal get_ft_fs_d add_sub_d: bne t1, DEXP_INF, 1f # is FS an infinity? - bne ta5, DEXP_INF, result_fs_d # if FT is not inf, result=FS + bne ta1, DEXP_INF, result_fs_d # if FT is not inf, result=FS bne t2, zero, result_fs_d # if FS is NAN, result is FS bne t3, zero, result_fs_d - bne ta6, zero, result_ft_d # if FT is NAN, result is FT - bne ta7, zero, result_ft_d - bne t0, ta4, invalid_d # both infinities same sign? + bne ta2, zero, result_ft_d # if FT is NAN, result is FT + bne ta3, zero, result_ft_d + bne t0, ta0, invalid_d # both infinities same sign? b result_fs_d # result is in FS 1: - beq ta5, DEXP_INF, result_ft_d # if FT is inf, result=FT + beq ta1, DEXP_INF, result_ft_d # if FT is inf, result=FT bne t1, zero, 4f # is FS a denormalized num? bne t2, zero, 1f # is FS zero? beq t3, zero, 3f 1: - bne ta5, zero, 2f # is FT a denormalized num? - bne ta6, zero, 1f - beq ta7, zero, result_fs_d # FT is zero, result=FS + bne ta1, zero, 2f # is FT a denormalized num? + bne ta2, zero, 1f + beq ta3, zero, result_fs_d # FT is zero, result=FS 1: jal renorm_fs_d jal renorm_ft_d b 5f 2: jal renorm_fs_d - subu ta5, ta5, DEXP_BIAS # unbias FT exponent - or ta6, ta6, DIMPL_ONE # set implied one bit + subu ta1, ta1, DEXP_BIAS # unbias FT exponent + or ta2, ta2, DIMPL_ONE # set implied one bit b 5f 3: - bne ta5, zero, result_ft_d # if FT != 0, result=FT - bne ta6, zero, result_ft_d - bne ta7, zero, result_ft_d + bne ta1, zero, result_ft_d # if FT != 0, result=FT + bne ta2, zero, result_ft_d + bne ta3, zero, result_ft_d and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, ta4 # compute result sign + or t0, t0, ta0 # compute result sign b result_fs_d 1: - and t0, t0, ta4 # compute result sign + and t0, t0, ta0 # compute result sign b result_fs_d 4: - bne ta5, zero, 2f # is FT a denormalized num? - bne ta6, zero, 1f - beq ta7, zero, result_fs_d # FT is zero, result=FS + bne ta1, zero, 2f # is FT a denormalized num? + bne ta2, zero, 1f + beq ta3, zero, result_fs_d # FT is zero, result=FS 1: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit @@ -811,15 +811,15 @@ add_sub_d: 2: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit - subu ta5, ta5, DEXP_BIAS # unbias FT exponent - or ta6, ta6, DIMPL_ONE # set implied one bit + subu ta1, ta1, DEXP_BIAS # unbias FT exponent + or ta2, ta2, DIMPL_ONE # set implied one bit /* * Perform the addition. */ 5: move t8, zero # no shifted bits (sticky reg) - beq t1, ta5, 4f # no shift needed - subu v0, t1, ta5 # v0 = difference of exponents + beq t1, ta1, 4f # no shift needed + subu v0, t1, ta1 # v0 = difference of exponents move v1, v0 # v1 = abs(difference) bge v0, zero, 1f negu v1 @@ -827,18 +827,18 @@ add_sub_d: ble v1, DFRAC_BITS+2, 2f # is difference too great? li t8, STICKYBIT # set the sticky bit bge v0, zero, 1f # check which exp is larger - move t1, ta5 # result exp is FTs + move t1, ta1 # result exp is FTs move t2, zero # FSs fraction shifted is zero move t3, zero b 4f 1: - move ta6, zero # FTs fraction shifted is zero - move ta7, zero + move ta2, zero # FTs fraction shifted is zero + move ta3, zero b 4f 2: li t9, 32 bge v0, zero, 3f # if FS > FT, shift FTs frac - move t1, ta5 # FT > FS, result exp is FTs + move t1, ta1 # FT > FS, result exp is FTs blt v1, t9, 1f # shift right by < 32? subu v1, v1, t9 subu t9, t9, v1 @@ -860,62 +860,62 @@ add_sub_d: blt v1, t9, 1f # shift right by < 32? subu v1, v1, t9 subu t9, t9, v1 - sll t8, ta6, t9 # save bits shifted out - srl ta7, ta6, v1 # shift FTs fraction - move ta6, zero + sll t8, ta2, t9 # save bits shifted out + srl ta3, ta2, v1 # shift FTs fraction + move ta2, zero b 4f 1: subu t9, t9, v1 - sll t8, ta7, t9 # save bits shifted out - srl ta7, ta7, v1 # shift FTs fraction - sll t9, ta6, t9 # save bits shifted out of t2 - or ta7, ta7, t9 # and put into t3 - srl ta6, ta6, v1 + sll t8, ta3, t9 # save bits shifted out + srl ta3, ta3, v1 # shift FTs fraction + sll t9, ta2, t9 # save bits shifted out of t2 + or ta3, ta3, t9 # and put into t3 + srl ta2, ta2, v1 4: - bne t0, ta4, 1f # if signs differ, subtract - addu t3, t3, ta7 # add fractions - sltu t9, t3, ta7 # compute carry - addu t2, t2, ta6 # add fractions + bne t0, ta0, 1f # if signs differ, subtract + addu t3, t3, ta3 # add fractions + sltu t9, t3, ta3 # compute carry + addu t2, t2, ta2 # add fractions addu t2, t2, t9 # add carry b norm_d 1: - blt t2, ta6, 3f # subtract larger from smaller - bne t2, ta6, 2f - bltu t3, ta7, 3f - bne t3, ta7, 2f # if same, result=0 + blt t2, ta2, 3f # subtract larger from smaller + bne t2, ta2, 2f + bltu t3, ta3, 3f + bne t3, ta3, 2f # if same, result=0 move t1, zero # result=0 move t2, zero move t3, zero and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, ta4 # compute result sign + or t0, t0, ta0 # compute result sign b result_fs_d 1: - and t0, t0, ta4 # compute result sign + and t0, t0, ta0 # compute result sign b result_fs_d 2: - beq t8, zero, 1f # compute t2:t3:zero - ta6:ta7:t8 + beq t8, zero, 1f # compute t2:t3:zero - ta2:ta3:t8 subu t8, zero, t8 sltu v0, t3, 1 # compute barrow out subu t3, t3, 1 # subtract barrow subu t2, t2, v0 1: - sltu v0, t3, ta7 - subu t3, t3, ta7 # subtract fractions - subu t2, t2, ta6 # subtract fractions + sltu v0, t3, ta3 + subu t3, t3, ta3 # subtract fractions + subu t2, t2, ta2 # subtract fractions subu t2, t2, v0 # subtract barrow b norm_d 3: - move t0, ta4 # sign of result = FTs - beq t8, zero, 1f # compute ta6:ta7:zero - t2:t3:t8 + move t0, ta0 # sign of result = FTs + beq t8, zero, 1f # compute ta2:ta3:zero - t2:t3:t8 subu t8, zero, t8 - sltu v0, ta7, 1 # compute barrow out - subu ta7, ta7, 1 # subtract barrow - subu ta6, ta6, v0 + sltu v0, ta3, 1 # compute barrow out + subu ta3, ta3, 1 # subtract barrow + subu ta2, ta2, v0 1: - sltu v0, ta7, t3 - subu t3, ta7, t3 # subtract fractions - subu t2, ta6, t2 # subtract fractions + sltu v0, ta3, t3 + subu t3, ta3, t3 # subtract fractions + subu t2, ta2, t2 # subtract fractions subu t2, t2, v0 # subtract barrow b norm_d @@ -924,22 +924,22 @@ add_sub_d: */ mul_s: jal get_ft_fs_s - xor t0, t0, ta4 # compute sign of result - move ta4, t0 + xor t0, t0, ta0 # compute sign of result + move ta0, t0 bne t1, SEXP_INF, 2f # is FS an infinity? bne t2, zero, result_fs_s # if FS is a NAN, result=FS - bne ta5, SEXP_INF, 1f # FS is inf, is FT an infinity? - bne ta6, zero, result_ft_s # if FT is a NAN, result=FT + bne ta1, SEXP_INF, 1f # FS is inf, is FT an infinity? + bne ta2, zero, result_ft_s # if FT is a NAN, result=FT b result_fs_s # result is infinity 1: - bne ta5, zero, result_fs_s # inf * zero? if no, result=FS - bne ta6, zero, result_fs_s + bne ta1, zero, result_fs_s # inf * zero? if no, result=FS + bne ta2, zero, result_fs_s b invalid_s # infinity * zero is invalid 2: - bne ta5, SEXP_INF, 1f # FS != inf, is FT an infinity? + bne ta1, SEXP_INF, 1f # FS != inf, is FT an infinity? bne t1, zero, result_ft_s # zero * inf? if no, result=FT bne t2, zero, result_ft_s - bne ta6, zero, result_ft_s # if FT is a NAN, result=FT + bne ta2, zero, result_ft_s # if FT is a NAN, result=FT b invalid_s # zero * infinity is invalid 1: bne t1, zero, 1f # is FS zero? @@ -950,17 +950,17 @@ mul_s: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit 2: - bne ta5, zero, 1f # is FT zero? - beq ta6, zero, result_ft_s # result is zero + bne ta1, zero, 1f # is FT zero? + beq ta2, zero, result_ft_s # result is zero jal renorm_ft_s b 2f 1: - subu ta5, ta5, SEXP_BIAS # unbias FT exponent - or ta6, ta6, SIMPL_ONE # set implied one bit + subu ta1, ta1, SEXP_BIAS # unbias FT exponent + or ta2, ta2, SIMPL_ONE # set implied one bit 2: - addu t1, t1, ta5 # compute result exponent + addu t1, t1, ta1 # compute result exponent addu t1, t1, 9 # account for binary point - multu t2, ta6 # multiply fractions + multu t2, ta2 # multiply fractions mflo t8 mfhi t2 b norm_s @@ -970,27 +970,27 @@ mul_s: */ mul_d: jal get_ft_fs_d - xor t0, t0, ta4 # compute sign of result - move ta4, t0 + xor t0, t0, ta0 # compute sign of result + move ta0, t0 bne t1, DEXP_INF, 2f # is FS an infinity? bne t2, zero, result_fs_d # if FS is a NAN, result=FS bne t3, zero, result_fs_d - bne ta5, DEXP_INF, 1f # FS is inf, is FT an infinity? - bne ta6, zero, result_ft_d # if FT is a NAN, result=FT - bne ta7, zero, result_ft_d + bne ta1, DEXP_INF, 1f # FS is inf, is FT an infinity? + bne ta2, zero, result_ft_d # if FT is a NAN, result=FT + bne ta3, zero, result_ft_d b result_fs_d # result is infinity 1: - bne ta5, zero, result_fs_d # inf * zero? if no, result=FS - bne ta6, zero, result_fs_d - bne ta7, zero, result_fs_d + bne ta1, zero, result_fs_d # inf * zero? if no, result=FS + bne ta2, zero, result_fs_d + bne ta3, zero, result_fs_d b invalid_d # infinity * zero is invalid 2: - bne ta5, DEXP_INF, 1f # FS != inf, is FT an infinity? + bne ta1, DEXP_INF, 1f # FS != inf, is FT an infinity? bne t1, zero, result_ft_d # zero * inf? if no, result=FT bne t2, zero, result_ft_d # if FS is a NAN, result=FS bne t3, zero, result_ft_d - bne ta6, zero, result_ft_d # if FT is a NAN, result=FT - bne ta7, zero, result_ft_d + bne ta2, zero, result_ft_d # if FT is a NAN, result=FT + bne ta3, zero, result_ft_d b invalid_d # zero * infinity is invalid 1: bne t1, zero, 2f # is FS zero? @@ -1003,37 +1003,37 @@ mul_d: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit 3: - bne ta5, zero, 2f # is FT zero? - bne ta6, zero, 1f - beq ta7, zero, result_ft_d # result is zero + bne ta1, zero, 2f # is FT zero? + bne ta2, zero, 1f + beq ta3, zero, result_ft_d # result is zero 1: jal renorm_ft_d b 3f 2: - subu ta5, ta5, DEXP_BIAS # unbias FT exponent - or ta6, ta6, DIMPL_ONE # set implied one bit + subu ta1, ta1, DEXP_BIAS # unbias FT exponent + or ta2, ta2, DIMPL_ONE # set implied one bit 3: - addu t1, t1, ta5 # compute result exponent + addu t1, t1, ta1 # compute result exponent addu t1, t1, 12 # ??? - multu t3, ta7 # multiply fractions (low * low) - move ta4, t2 # free up t2,t3 for result - move ta5, t3 + multu t3, ta3 # multiply fractions (low * low) + move ta0, t2 # free up t2,t3 for result + move ta1, t3 mflo a3 # save low order bits mfhi t8 not v0, t8 - multu ta4, ta7 # multiply FS(high) * FT(low) + multu ta0, ta3 # multiply FS(high) * FT(low) mflo v1 mfhi t3 # init low result sltu v0, v0, v1 # compute carry addu t8, v1 - multu ta5, ta6 # multiply FS(low) * FT(high) + multu ta1, ta2 # multiply FS(low) * FT(high) addu t3, t3, v0 # add carry not v0, t8 mflo v1 mfhi t2 sltu v0, v0, v1 addu t8, v1 - multu ta4, ta6 # multiply FS(high) * FT(high) + multu ta0, ta2 # multiply FS(high) * FT(high) addu t3, v0 not v1, t3 sltu v1, v1, t2 @@ -1054,24 +1054,24 @@ mul_d: */ div_s: jal get_ft_fs_s - xor t0, t0, ta4 # compute sign of result - move ta4, t0 + xor t0, t0, ta0 # compute sign of result + move ta0, t0 bne t1, SEXP_INF, 1f # is FS an infinity? bne t2, zero, result_fs_s # if FS is NAN, result is FS - bne ta5, SEXP_INF, result_fs_s # is FT an infinity? - bne ta6, zero, result_ft_s # if FT is NAN, result is FT + bne ta1, SEXP_INF, result_fs_s # is FT an infinity? + bne ta2, zero, result_ft_s # if FT is NAN, result is FT b invalid_s # infinity/infinity is invalid 1: - bne ta5, SEXP_INF, 1f # is FT an infinity? - bne ta6, zero, result_ft_s # if FT is NAN, result is FT + bne ta1, SEXP_INF, 1f # is FT an infinity? + bne ta2, zero, result_ft_s # if FT is NAN, result is FT move t1, zero # x / infinity is zero move t2, zero b result_fs_s 1: bne t1, zero, 2f # is FS zero? bne t2, zero, 1f - bne ta5, zero, result_fs_s # FS=zero, is FT zero? - beq ta6, zero, invalid_s # 0 / 0 + bne ta1, zero, result_fs_s # FS=zero, is FT zero? + beq ta2, zero, invalid_s # 0 / 0 b result_fs_s # result = zero 1: jal renorm_fs_s @@ -1080,8 +1080,8 @@ div_s: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit 3: - bne ta5, zero, 2f # is FT zero? - bne ta6, zero, 1f + bne ta1, zero, 2f # is FT zero? + bne ta2, zero, 1f or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap @@ -1093,18 +1093,18 @@ div_s: jal renorm_ft_s b 3f 2: - subu ta5, ta5, SEXP_BIAS # unbias FT exponent - or ta6, ta6, SIMPL_ONE # set implied one bit + subu ta1, ta1, SEXP_BIAS # unbias FT exponent + or ta2, ta2, SIMPL_ONE # set implied one bit 3: - subu t1, t1, ta5 # compute exponent + subu t1, t1, ta1 # compute exponent subu t1, t1, 3 # compensate for result position li v0, SFRAC_BITS+3 # number of bits to divide move t8, t2 # init dividend move t2, zero # init result 1: - bltu t8, ta6, 3f # is dividend >= divisor? + bltu t8, ta2, 3f # is dividend >= divisor? 2: - subu t8, t8, ta6 # subtract divisor from dividend + subu t8, t8, ta2 # subtract divisor from dividend or t2, t2, 1 # remember that we did bne t8, zero, 3f # if not done, continue sll t2, t2, v0 # shift result to final position @@ -1121,19 +1121,19 @@ div_s: */ div_d: jal get_ft_fs_d - xor t0, t0, ta4 # compute sign of result - move ta4, t0 + xor t0, t0, ta0 # compute sign of result + move ta0, t0 bne t1, DEXP_INF, 1f # is FS an infinity? bne t2, zero, result_fs_d # if FS is NAN, result is FS bne t3, zero, result_fs_d - bne ta5, DEXP_INF, result_fs_d # is FT an infinity? - bne ta6, zero, result_ft_d # if FT is NAN, result is FT - bne ta7, zero, result_ft_d + bne ta1, DEXP_INF, result_fs_d # is FT an infinity? + bne ta2, zero, result_ft_d # if FT is NAN, result is FT + bne ta3, zero, result_ft_d b invalid_d # infinity/infinity is invalid 1: - bne ta5, DEXP_INF, 1f # is FT an infinity? - bne ta6, zero, result_ft_d # if FT is NAN, result is FT - bne ta7, zero, result_ft_d + bne ta1, DEXP_INF, 1f # is FT an infinity? + bne ta2, zero, result_ft_d # if FT is NAN, result is FT + bne ta3, zero, result_ft_d move t1, zero # x / infinity is zero move t2, zero move t3, zero @@ -1142,9 +1142,9 @@ div_d: bne t1, zero, 2f # is FS zero? bne t2, zero, 1f bne t3, zero, 1f - bne ta5, zero, result_fs_d # FS=zero, is FT zero? - bne ta6, zero, result_fs_d - beq ta7, zero, invalid_d # 0 / 0 + bne ta1, zero, result_fs_d # FS=zero, is FT zero? + bne ta2, zero, result_fs_d + beq ta3, zero, invalid_d # 0 / 0 b result_fs_d # result = zero 1: jal renorm_fs_d @@ -1153,9 +1153,9 @@ div_d: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit 3: - bne ta5, zero, 2f # is FT zero? - bne ta6, zero, 1f - bne ta7, zero, 1f + bne ta1, zero, 2f # is FT zero? + bne ta2, zero, 1f + bne ta3, zero, 1f or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap @@ -1168,10 +1168,10 @@ div_d: jal renorm_ft_d b 3f 2: - subu ta5, ta5, DEXP_BIAS # unbias FT exponent - or ta6, ta6, DIMPL_ONE # set implied one bit + subu ta1, ta1, DEXP_BIAS # unbias FT exponent + or ta2, ta2, DIMPL_ONE # set implied one bit 3: - subu t1, t1, ta5 # compute exponent + subu t1, t1, ta1 # compute exponent subu t1, t1, 3 # compensate for result position li v0, DFRAC_BITS+3 # number of bits to divide move t8, t2 # init dividend @@ -1179,13 +1179,13 @@ div_d: move t2, zero # init result move t3, zero 1: - bltu t8, ta6, 3f # is dividend >= divisor? - bne t8, ta6, 2f - bltu t9, ta7, 3f + bltu t8, ta2, 3f # is dividend >= divisor? + bne t8, ta2, 2f + bltu t9, ta3, 3f 2: - sltu v1, t9, ta7 # subtract divisor from dividend - subu t9, t9, ta7 - subu t8, t8, ta6 + sltu v1, t9, ta3 # subtract divisor from dividend + subu t9, t9, ta3 + subu t8, t8, ta2 subu t8, t8, v1 or t3, t3, 1 # remember that we did bne t8, zero, 3f # if not done, continue @@ -1580,23 +1580,23 @@ cmp_s: bne t1, SEXP_INF, 1f # is FS an infinity? bne t2, zero, unordered # FS is a NAN 1: - bne ta5, SEXP_INF, 2f # is FT an infinity? - bne ta6, zero, unordered # FT is a NAN + bne ta1, SEXP_INF, 2f # is FT an infinity? + bne ta2, zero, unordered # FT is a NAN 2: sll t1, t1, 23 # reassemble exp & frac or t1, t1, t2 - sll ta5, ta5, 23 # reassemble exp & frac - or ta5, ta5, ta6 + sll ta1, ta1, 23 # reassemble exp & frac + or ta1, ta1, ta2 beq t0, zero, 1f # is FS positive? negu t1 1: - beq ta4, zero, 1f # is FT positive? - negu ta5 + beq ta0, zero, 1f # is FT positive? + negu ta1 1: li v0, COND_LESS - blt t1, ta5, test_cond # is FS < FT? + blt t1, ta1, test_cond # is FS < FT? li v0, COND_EQUAL - beq t1, ta5, test_cond # is FS == FT? + beq t1, ta1, test_cond # is FS == FT? move v0, zero # FS > FT b test_cond @@ -1609,14 +1609,14 @@ cmp_d: bne t2, zero, unordered bne t3, zero, unordered # FS is a NAN 1: - bne ta5, DEXP_INF, 2f # is FT an infinity? - bne ta6, zero, unordered - bne ta7, zero, unordered # FT is a NAN + bne ta1, DEXP_INF, 2f # is FT an infinity? + bne ta2, zero, unordered + bne ta3, zero, unordered # FT is a NAN 2: sll t1, t1, 20 # reassemble exp & frac or t1, t1, t2 - sll ta5, ta5, 20 # reassemble exp & frac - or ta5, ta5, ta6 + sll ta1, ta1, 20 # reassemble exp & frac + or ta1, ta1, ta2 beq t0, zero, 1f # is FS positive? not t3 # negate t1,t3 not t1 @@ -1624,21 +1624,21 @@ cmp_d: seq v0, t3, zero # compute carry addu t1, t1, v0 1: - beq ta4, zero, 1f # is FT positive? - not ta7 # negate ta5,ta7 - not ta5 - addu ta7, ta7, 1 - seq v0, ta7, zero # compute carry - addu ta5, ta5, v0 + beq ta0, zero, 1f # is FT positive? + not ta3 # negate ta1,ta3 + not ta1 + addu ta3, ta3, 1 + seq v0, ta3, zero # compute carry + addu ta1, ta1, v0 1: li v0, COND_LESS - blt t1, ta5, test_cond # is FS(MSW) < FT(MSW)? + blt t1, ta1, test_cond # is FS(MSW) < FT(MSW)? move v0, zero - bne t1, ta5, test_cond # is FS(MSW) > FT(MSW)? + bne t1, ta1, test_cond # is FS(MSW) > FT(MSW)? li v0, COND_LESS - bltu t3, ta7, test_cond # is FS(LSW) < FT(LSW)? + bltu t3, ta3, test_cond # is FS(LSW) < FT(LSW)? li v0, COND_EQUAL - beq t3, ta7, test_cond # is FS(LSW) == FT(LSW)? + beq t3, ta3, test_cond # is FS(LSW) == FT(LSW)? move v0, zero # FS > FT test_cond: and v0, v0, a0 # condition match instruction? @@ -1729,8 +1729,8 @@ norm_s: or t8, t8, v0 srl t2, t2, t9 norm_noshift_s: - move ta5, t1 # save unrounded exponent - move ta6, t2 # save unrounded fraction + move ta1, t1 # save unrounded exponent + move ta2, t2 # save unrounded fraction and v0, a1, FPC_ROUNDING_BITS # get rounding mode beq v0, FPC_ROUND_RN, 3f # round to nearest beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) @@ -1830,8 +1830,8 @@ underflow_s: * signal inexact result (if it is) and trap (if enabled). */ 1: - move t1, ta5 # get unrounded exponent - move t2, ta6 # get unrounded fraction + move t1, ta1 # get unrounded exponent + move t2, ta2 # get unrounded fraction li t9, SEXP_MIN # compute shift amount subu t9, t9, t1 # shift t2,t8 right by t9 blt t9, SFRAC_BITS+2, 3f # shift all the bits out? @@ -1974,9 +1974,9 @@ norm_d: or t3, t3, v0 srl t2, t2, t9 norm_noshift_d: - move ta5, t1 # save unrounded exponent - move ta6, t2 # save unrounded fraction (MS) - move ta7, t3 # save unrounded fraction (LS) + move ta1, t1 # save unrounded exponent + move ta2, t2 # save unrounded fraction (MS) + move ta3, t3 # save unrounded fraction (LS) and v0, a1, FPC_ROUNDING_BITS # get rounding mode beq v0, FPC_ROUND_RN, 3f # round to nearest beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) @@ -2082,9 +2082,9 @@ underflow_d: * signal inexact result (if it is) and trap (if enabled). */ 1: - move t1, ta5 # get unrounded exponent - move t2, ta6 # get unrounded fraction (MS) - move t3, ta7 # get unrounded fraction (LS) + move t1, ta1 # get unrounded exponent + move t2, ta2 # get unrounded fraction (MS) + move t3, ta3 # get unrounded fraction (LS) li t9, DEXP_MIN # compute shift amount subu t9, t9, t1 # shift t2,t8 right by t9 blt t9, DFRAC_BITS+2, 3f # shift all the bits out? @@ -2233,9 +2233,9 @@ ill: b done_err result_ft_s: - move t0, ta4 # result is FT - move t1, ta5 - move t2, ta6 + move t0, ta0 # result is FT + move t1, ta1 + move t2, ta2 result_fs_s: # result is FS jal set_fd_s # save result (in t0,t1,t2) b done @@ -2245,10 +2245,10 @@ result_fs_w: b done result_ft_d: - move t0, ta4 # result is FT - move t1, ta5 - move t2, ta6 - move t3, ta7 + move t0, ta0 # result is FT + move t1, ta1 + move t2, ta2 + move t3, ta3 result_fs_d: # result is FS jal set_fd_d # save result (in t0,t1,t2,t3) @@ -2364,9 +2364,9 @@ END(get_fs_int) * t0 contains the FS sign * t1 contains the FS (biased) exponent * t2 contains the FS fraction - * ta4 contains the FT sign - * ta5 contains the FT (biased) exponent - * ta6 contains the FT fraction + * ta0 contains the FT sign + * ta1 contains the FT (biased) exponent + * ta2 contains the FT fraction * *---------------------------------------------------------------------------- */ @@ -2397,59 +2397,59 @@ get_ft_s_tbl: .text get_ft_s_f0: - mfc1 ta4, $f0 + mfc1 ta0, $f0 b get_ft_s_done get_ft_s_f2: - mfc1 ta4, $f2 + mfc1 ta0, $f2 b get_ft_s_done get_ft_s_f4: - mfc1 ta4, $f4 + mfc1 ta0, $f4 b get_ft_s_done get_ft_s_f6: - mfc1 ta4, $f6 + mfc1 ta0, $f6 b get_ft_s_done get_ft_s_f8: - mfc1 ta4, $f8 + mfc1 ta0, $f8 b get_ft_s_done get_ft_s_f10: - mfc1 ta4, $f10 + mfc1 ta0, $f10 b get_ft_s_done get_ft_s_f12: - mfc1 ta4, $f12 + mfc1 ta0, $f12 b get_ft_s_done get_ft_s_f14: - mfc1 ta4, $f14 + mfc1 ta0, $f14 b get_ft_s_done get_ft_s_f16: - mfc1 ta4, $f16 + mfc1 ta0, $f16 b get_ft_s_done get_ft_s_f18: - mfc1 ta4, $f18 + mfc1 ta0, $f18 b get_ft_s_done get_ft_s_f20: - mfc1 ta4, $f20 + mfc1 ta0, $f20 b get_ft_s_done get_ft_s_f22: - mfc1 ta4, $f22 + mfc1 ta0, $f22 b get_ft_s_done get_ft_s_f24: - mfc1 ta4, $f24 + mfc1 ta0, $f24 b get_ft_s_done get_ft_s_f26: - mfc1 ta4, $f26 + mfc1 ta0, $f26 b get_ft_s_done get_ft_s_f28: - mfc1 ta4, $f28 + mfc1 ta0, $f28 b get_ft_s_done get_ft_s_f30: - mfc1 ta4, $f30 + mfc1 ta0, $f30 get_ft_s_done: - srl ta5, ta4, 23 # get exponent - and ta5, ta5, 0xFF - and ta6, ta4, 0x7FFFFF # get fraction - srl ta4, ta4, 31 # get sign - bne ta5, SEXP_INF, 1f # is it a signaling NAN? - and v0, ta6, SSIGNAL_NAN + srl ta1, ta0, 23 # get exponent + and ta1, ta1, 0xFF + and ta2, ta0, 0x7FFFFF # get fraction + srl ta0, ta0, 31 # get sign + bne ta1, SEXP_INF, 1f # is it a signaling NAN? + and v0, ta2, SSIGNAL_NAN bne v0, zero, invalid_s 1: /* fall through to get FS */ @@ -2565,10 +2565,10 @@ END(get_ft_fs_s) * t1 contains the FS (biased) exponent * t2 contains the FS fraction * t3 contains the FS remaining fraction - * ta4 contains the FT sign - * ta5 contains the FT (biased) exponent - * ta6 contains the FT fraction - * ta7 contains the FT remaining fraction + * ta0 contains the FT sign + * ta1 contains the FT (biased) exponent + * ta2 contains the FT fraction + * ta3 contains the FT remaining fraction * *---------------------------------------------------------------------------- */ @@ -2599,75 +2599,75 @@ get_ft_d_tbl: .text get_ft_d_f0: - mfc1 ta7, $f0 - mfc1 ta4, $f1 + mfc1 ta3, $f0 + mfc1 ta0, $f1 b get_ft_d_done get_ft_d_f2: - mfc1 ta7, $f2 - mfc1 ta4, $f3 + mfc1 ta3, $f2 + mfc1 ta0, $f3 b get_ft_d_done get_ft_d_f4: - mfc1 ta7, $f4 - mfc1 ta4, $f5 + mfc1 ta3, $f4 + mfc1 ta0, $f5 b get_ft_d_done get_ft_d_f6: - mfc1 ta7, $f6 - mfc1 ta4, $f7 + mfc1 ta3, $f6 + mfc1 ta0, $f7 b get_ft_d_done get_ft_d_f8: - mfc1 ta7, $f8 - mfc1 ta4, $f9 + mfc1 ta3, $f8 + mfc1 ta0, $f9 b get_ft_d_done get_ft_d_f10: - mfc1 ta7, $f10 - mfc1 ta4, $f11 + mfc1 ta3, $f10 + mfc1 ta0, $f11 b get_ft_d_done get_ft_d_f12: - mfc1 ta7, $f12 - mfc1 ta4, $f13 + mfc1 ta3, $f12 + mfc1 ta0, $f13 b get_ft_d_done get_ft_d_f14: - mfc1 ta7, $f14 - mfc1 ta4, $f15 + mfc1 ta3, $f14 + mfc1 ta0, $f15 b get_ft_d_done get_ft_d_f16: - mfc1 ta7, $f16 - mfc1 ta4, $f17 + mfc1 ta3, $f16 + mfc1 ta0, $f17 b get_ft_d_done get_ft_d_f18: - mfc1 ta7, $f18 - mfc1 ta4, $f19 + mfc1 ta3, $f18 + mfc1 ta0, $f19 b get_ft_d_done get_ft_d_f20: - mfc1 ta7, $f20 - mfc1 ta4, $f21 + mfc1 ta3, $f20 + mfc1 ta0, $f21 b get_ft_d_done get_ft_d_f22: - mfc1 ta7, $f22 - mfc1 ta4, $f23 + mfc1 ta3, $f22 + mfc1 ta0, $f23 b get_ft_d_done get_ft_d_f24: - mfc1 ta7, $f24 - mfc1 ta4, $f25 + mfc1 ta3, $f24 + mfc1 ta0, $f25 b get_ft_d_done get_ft_d_f26: - mfc1 ta7, $f26 - mfc1 ta4, $f27 + mfc1 ta3, $f26 + mfc1 ta0, $f27 b get_ft_d_done get_ft_d_f28: - mfc1 ta7, $f28 - mfc1 ta4, $f29 + mfc1 ta3, $f28 + mfc1 ta0, $f29 b get_ft_d_done get_ft_d_f30: - mfc1 ta7, $f30 - mfc1 ta4, $f31 + mfc1 ta3, $f30 + mfc1 ta0, $f31 get_ft_d_done: - srl ta5, ta4, 20 # get exponent - and ta5, ta5, 0x7FF - and ta6, ta4, 0xFFFFF # get fraction - srl ta4, ta4, 31 # get sign - bne ta5, DEXP_INF, 1f # is it a signaling NAN? - and v0, ta6, DSIGNAL_NAN + srl ta1, ta0, 20 # get exponent + and ta1, ta1, 0x7FF + and ta2, ta0, 0xFFFFF # get fraction + srl ta0, ta0, 31 # get sign + bne ta1, DEXP_INF, 1f # is it a signaling NAN? + and v0, ta2, DSIGNAL_NAN bne v0, zero, invalid_d 1: /* fall through to get FS */ @@ -2799,9 +2799,9 @@ END(get_ft_fs_d) * t0 contains the sign * t1 contains the (biased) exponent * t2 contains the fraction - * ta4 contains the sign - * ta5 contains the (biased) exponent - * ta6 contains the fraction + * ta0 contains the sign + * ta1 contains the (biased) exponent + * ta2 contains the fraction * *---------------------------------------------------------------------------- */ @@ -2910,57 +2910,57 @@ cmp_ft_s_tbl: .text cmp_ft_s_f0: - mfc1 ta4, $f0 + mfc1 ta0, $f0 b cmp_ft_s_done cmp_ft_s_f2: - mfc1 ta4, $f2 + mfc1 ta0, $f2 b cmp_ft_s_done cmp_ft_s_f4: - mfc1 ta4, $f4 + mfc1 ta0, $f4 b cmp_ft_s_done cmp_ft_s_f6: - mfc1 ta4, $f6 + mfc1 ta0, $f6 b cmp_ft_s_done cmp_ft_s_f8: - mfc1 ta4, $f8 + mfc1 ta0, $f8 b cmp_ft_s_done cmp_ft_s_f10: - mfc1 ta4, $f10 + mfc1 ta0, $f10 b cmp_ft_s_done cmp_ft_s_f12: - mfc1 ta4, $f12 + mfc1 ta0, $f12 b cmp_ft_s_done cmp_ft_s_f14: - mfc1 ta4, $f14 + mfc1 ta0, $f14 b cmp_ft_s_done cmp_ft_s_f16: - mfc1 ta4, $f16 + mfc1 ta0, $f16 b cmp_ft_s_done cmp_ft_s_f18: - mfc1 ta4, $f18 + mfc1 ta0, $f18 b cmp_ft_s_done cmp_ft_s_f20: - mfc1 ta4, $f20 + mfc1 ta0, $f20 b cmp_ft_s_done cmp_ft_s_f22: - mfc1 ta4, $f22 + mfc1 ta0, $f22 b cmp_ft_s_done cmp_ft_s_f24: - mfc1 ta4, $f24 + mfc1 ta0, $f24 b cmp_ft_s_done cmp_ft_s_f26: - mfc1 ta4, $f26 + mfc1 ta0, $f26 b cmp_ft_s_done cmp_ft_s_f28: - mfc1 ta4, $f28 + mfc1 ta0, $f28 b cmp_ft_s_done cmp_ft_s_f30: - mfc1 ta4, $f30 + mfc1 ta0, $f30 cmp_ft_s_done: - srl ta5, ta4, 23 # get exponent - and ta5, ta5, 0xFF - and ta6, ta4, 0x7FFFFF # get fraction - srl ta4, ta4, 31 # get sign + srl ta1, ta0, 23 # get exponent + and ta1, ta1, 0xFF + and ta2, ta0, 0x7FFFFF # get fraction + srl ta0, ta0, 31 # get sign j ra END(get_cmp_s) @@ -2976,10 +2976,10 @@ END(get_cmp_s) * t1 contains the (biased) exponent * t2 contains the fraction * t3 contains the remaining fraction - * ta4 contains the sign - * ta5 contains the (biased) exponent - * ta6 contains the fraction - * ta7 contains the remaining fraction + * ta0 contains the sign + * ta1 contains the (biased) exponent + * ta2 contains the fraction + * ta3 contains the remaining fraction * *---------------------------------------------------------------------------- */ @@ -3104,73 +3104,73 @@ cmp_ft_d_tbl: .text cmp_ft_d_f0: - mfc1 ta7, $f0 - mfc1 ta4, $f1 + mfc1 ta3, $f0 + mfc1 ta0, $f1 b cmp_ft_d_done cmp_ft_d_f2: - mfc1 ta7, $f2 - mfc1 ta4, $f3 + mfc1 ta3, $f2 + mfc1 ta0, $f3 b cmp_ft_d_done cmp_ft_d_f4: - mfc1 ta7, $f4 - mfc1 ta4, $f5 + mfc1 ta3, $f4 + mfc1 ta0, $f5 b cmp_ft_d_done cmp_ft_d_f6: - mfc1 ta7, $f6 - mfc1 ta4, $f7 + mfc1 ta3, $f6 + mfc1 ta0, $f7 b cmp_ft_d_done cmp_ft_d_f8: - mfc1 ta7, $f8 - mfc1 ta4, $f9 + mfc1 ta3, $f8 + mfc1 ta0, $f9 b cmp_ft_d_done cmp_ft_d_f10: - mfc1 ta7, $f10 - mfc1 ta4, $f11 + mfc1 ta3, $f10 + mfc1 ta0, $f11 b cmp_ft_d_done cmp_ft_d_f12: - mfc1 ta7, $f12 - mfc1 ta4, $f13 + mfc1 ta3, $f12 + mfc1 ta0, $f13 b cmp_ft_d_done cmp_ft_d_f14: - mfc1 ta7, $f14 - mfc1 ta4, $f15 + mfc1 ta3, $f14 + mfc1 ta0, $f15 b cmp_ft_d_done cmp_ft_d_f16: - mfc1 ta7, $f16 - mfc1 ta4, $f17 + mfc1 ta3, $f16 + mfc1 ta0, $f17 b cmp_ft_d_done cmp_ft_d_f18: - mfc1 ta7, $f18 - mfc1 ta4, $f19 + mfc1 ta3, $f18 + mfc1 ta0, $f19 b cmp_ft_d_done cmp_ft_d_f20: - mfc1 ta7, $f20 - mfc1 ta4, $f21 + mfc1 ta3, $f20 + mfc1 ta0, $f21 b cmp_ft_d_done cmp_ft_d_f22: - mfc1 ta7, $f22 - mfc1 ta4, $f23 + mfc1 ta3, $f22 + mfc1 ta0, $f23 b cmp_ft_d_done cmp_ft_d_f24: - mfc1 ta7, $f24 - mfc1 ta4, $f25 + mfc1 ta3, $f24 + mfc1 ta0, $f25 b cmp_ft_d_done cmp_ft_d_f26: - mfc1 ta7, $f26 - mfc1 ta4, $f27 + mfc1 ta3, $f26 + mfc1 ta0, $f27 b cmp_ft_d_done cmp_ft_d_f28: - mfc1 ta7, $f28 - mfc1 ta4, $f29 + mfc1 ta3, $f28 + mfc1 ta0, $f29 b cmp_ft_d_done cmp_ft_d_f30: - mfc1 ta7, $f30 - mfc1 ta4, $f31 + mfc1 ta3, $f30 + mfc1 ta0, $f31 cmp_ft_d_done: - srl ta5, ta4, 20 # get exponent - and ta5, ta5, 0x7FF - and ta6, ta4, 0xFFFFF # get fraction - srl ta4, ta4, 31 # get sign + srl ta1, ta0, 20 # get exponent + and ta1, ta1, 0x7FF + and ta2, ta0, 0xFFFFF # get fraction + srl ta0, ta0, 31 # get sign j ra END(get_cmp_d) @@ -3506,16 +3506,16 @@ END(renorm_fs_d) * renorm_ft_s -- * * Results: - * ta5 unbiased exponent - * ta6 normalized fraction + * ta1 unbiased exponent + * ta2 normalized fraction * *---------------------------------------------------------------------------- */ LEAF(renorm_ft_s, 0) /* - * Find out how many leading zero bits are in ta6 and put in t9. + * Find out how many leading zero bits are in ta2 and put in t9. */ - move v0, ta6 + move v0, ta2 move t9, zero srl v1, v0, 16 bne v1, zero, 1f @@ -3541,13 +3541,13 @@ LEAF(renorm_ft_s, 0) bne v1, zero, 1f addu t9, 1 /* - * Now shift ta6 the correct number of bits. + * Now shift ta2 the correct number of bits. */ 1: subu t9, t9, SLEAD_ZEROS # dont count normal leading zeros - li ta5, SEXP_MIN - subu ta5, ta5, t9 # adjust exponent - sll ta6, ta6, t9 + li ta1, SEXP_MIN + subu ta1, ta1, t9 # adjust exponent + sll ta2, ta2, t9 j ra END(renorm_ft_s) @@ -3555,19 +3555,19 @@ END(renorm_ft_s) * renorm_ft_d -- * * Results: - * ta5 unbiased exponent - * ta6,ta7 normalized fraction + * ta1 unbiased exponent + * ta2,ta3 normalized fraction * *---------------------------------------------------------------------------- */ LEAF(renorm_ft_d, 0) /* - * Find out how many leading zero bits are in ta6,ta7 and put in t9. + * Find out how many leading zero bits are in ta2,ta3 and put in t9. */ - move v0, ta6 + move v0, ta2 move t9, zero - bne ta6, zero, 1f - move v0, ta7 + bne ta2, zero, 1f + move v0, ta3 addu t9, 32 1: srl v1, v0, 16 @@ -3594,23 +3594,23 @@ LEAF(renorm_ft_d, 0) bne v1, zero, 1f addu t9, 1 /* - * Now shift ta6,ta7 the correct number of bits. + * Now shift ta2,ta3 the correct number of bits. */ 1: subu t9, t9, DLEAD_ZEROS # dont count normal leading zeros - li ta5, DEXP_MIN - subu ta5, ta5, t9 # adjust exponent + li ta1, DEXP_MIN + subu ta1, ta1, t9 # adjust exponent li v0, 32 blt t9, v0, 1f subu t9, t9, v0 # shift fraction left >= 32 bits - sll ta6, ta7, t9 - move ta7, zero + sll ta2, ta3, t9 + move ta3, zero j ra 1: subu v0, v0, t9 # shift fraction left < 32 bits - sll ta6, ta6, t9 - srl v1, ta7, v0 - or ta6, ta6, v1 - sll ta7, ta7, t9 + sll ta2, ta2, t9 + srl v1, ta3, v0 + or ta2, ta2, v1 + sll ta3, ta3, t9 j ra END(renorm_ft_d) diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S index 920416d7fd0..ac897c90276 100644 --- a/sys/arch/mips64/mips64/tlbhandler.S +++ b/sys/arch/mips64/mips64/tlbhandler.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlbhandler.S,v 1.5 2004/09/10 08:58:27 pefo Exp $ */ +/* $OpenBSD: tlbhandler.S,v 1.6 2004/09/10 09:32:13 pefo Exp $ */ /* * Copyright (c) 1995-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -382,7 +382,7 @@ LEAF(tlb_write_indexed, 0) ITLBNOPFIX lw a2, 8(a1) lw a3, 12(a1) - dmfc0 ta4, COP_0_TLB_HI # Save the current PID. + dmfc0 ta0, COP_0_TLB_HI # Save the current PID. dmtc0 a2, COP_0_TLB_LO0 # Set up entry low0. dmtc0 a3, COP_0_TLB_LO1 # Set up entry low1. @@ -401,7 +401,7 @@ LEAF(tlb_write_indexed, 0) nop nop - dmtc0 ta4, COP_0_TLB_HI # Restore the PID. + dmtc0 ta0, COP_0_TLB_HI # Restore the PID. nop dmtc0 zero, COP_0_TLB_PG_MASK # Default mask value. mtc0 v1, COP_0_STATUS_REG # Restore the status register @@ -419,30 +419,30 @@ LEAF(tlb_flush, 0) mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - mfc0 ta5, COP_0_TLB_WIRED + mfc0 ta1, COP_0_TLB_WIRED LA v0, KSEG0_BASE # invalid address - dmfc0 ta4, COP_0_TLB_HI # Save the PID + dmfc0 ta0, COP_0_TLB_HI # Save the PID dmtc0 v0, COP_0_TLB_HI # Mark entry high as invalid dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry0. dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. /* - * Align the starting value (ta5) and the upper bound (a0). + * Align the starting value (ta1) and the upper bound (a0). */ 1: - mtc0 ta5, COP_0_TLB_INDEX # Set the index register. - addu ta5, ta5, 1 # Increment index. + mtc0 ta1, COP_0_TLB_INDEX # Set the index register. + addu ta1, ta1, 1 # Increment index. nop nop nop tlbwi # Write the TLB entry. nop nop - bne ta5, a0, 1b + bne ta1, a0, 1b nop - dmtc0 ta4, COP_0_TLB_HI # Restore the PID + dmtc0 ta0, COP_0_TLB_HI # Restore the PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -458,7 +458,7 @@ LEAF(tlb_flush_addr, 0) ITLBNOPFIX li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 # Make shure valid hi value. - dmfc0 ta4, COP_0_TLB_HI # Get current PID + dmfc0 ta0, COP_0_TLB_HI # Get current PID dmtc0 a0, COP_0_TLB_HI # look for addr & PID nop nop @@ -468,11 +468,11 @@ LEAF(tlb_flush_addr, 0) nop nop # Delay for effect nop - LA ta5, KSEG0_BASE # Load invalid entry. + LA ta1, KSEG0_BASE # Load invalid entry. mfc0 v0, COP_0_TLB_INDEX # See what we got bltz v0, 1f # index < 0 => !found nop - dmtc0 ta5, COP_0_TLB_HI # Mark entry high as invalid + dmtc0 ta1, COP_0_TLB_HI # Mark entry high as invalid dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry. dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry. @@ -486,7 +486,7 @@ LEAF(tlb_flush_addr, 0) nop nop 1: - dmtc0 ta4, COP_0_TLB_HI # restore PID + dmtc0 ta0, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -500,10 +500,10 @@ LEAF(tlb_update, 0) mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - and ta5, a0, 0x1000 # ta5 = Even/Odd flag + and ta1, a0, 0x1000 # ta1 = Even/Odd flag li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 - dmfc0 ta4, COP_0_TLB_HI # Save current PID + dmfc0 ta0, COP_0_TLB_HI # Save current PID dmtc0 a0, COP_0_TLB_HI # Init high reg and a2, a1, PG_G # Copy global bit nop @@ -512,7 +512,7 @@ LEAF(tlb_update, 0) tlbp # Probe for the entry. dsll a1, a1, 34 dsrl a1, a1, 34 - bne ta5, zero, 2f # Decide even odd + bne ta1, zero, 2f # Decide even odd mfc0 v0, COP_0_TLB_INDEX # See what we got # EVEN bltz v0, 1f # index < 0 => !found @@ -576,7 +576,7 @@ LEAF(tlb_update, 0) 4: # Make shure pipeline nop # advances before we nop # uses the tlb. - dmtc0 ta4, COP_0_TLB_HI # restore PID + dmtc0 ta0, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -601,21 +601,21 @@ LEAF(tlb_read, 0) nop nop nop - mfc0 ta4, COP_0_TLB_PG_MASK # fetch the hi entry - dmfc0 ta5, COP_0_TLB_HI # fetch the hi entry - dmfc0 ta6, COP_0_TLB_LO0 # See what we got - dmfc0 ta7, COP_0_TLB_LO1 # See what we got + mfc0 ta0, COP_0_TLB_PG_MASK # fetch the hi entry + dmfc0 ta1, COP_0_TLB_HI # fetch the hi entry + dmfc0 ta2, COP_0_TLB_LO0 # See what we got + dmfc0 ta3, COP_0_TLB_LO1 # See what we got dmtc0 v0, COP_0_TLB_HI # restore PID nop nop nop # wait for PID active mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX - sw ta4, 0(a1) - sw ta5, 4(a1) - sw ta6, 8(a1) + sw ta0, 0(a1) + sw ta1, 4(a1) + sw ta2, 8(a1) j ra - sw ta7, 12(a1) + sw ta3, 12(a1) END(tlb_read) /*---------------------------------------------------------------- tlb_get_pid |