diff options
Diffstat (limited to 'sys')
57 files changed, 780 insertions, 1614 deletions
diff --git a/sys/arch/pica/conf/files.pica b/sys/arch/pica/conf/files.pica index 0001e1d074d..863f030084b 100644 --- a/sys/arch/pica/conf/files.pica +++ b/sys/arch/pica/conf/files.pica @@ -1,4 +1,4 @@ -# $OpenBSD: files.pica,v 1.4 1996/05/15 07:09:08 pefo Exp $ +# $OpenBSD: files.pica,v 1.5 1996/06/06 23:06:17 deraadt Exp $ # $NetBSD: files.pica,v 1.16 1995/04/30 10:11:00 cgd Exp $ # # maxpartitions must be first item in files.${ARCH} @@ -16,7 +16,6 @@ file arch/pica/pica/conf.c file arch/pica/pica/cpu_exec.c file arch/pica/pica/disksubr.c file arch/pica/dev/dma.c -file arch/pica/pica/exec_elf.c file arch/pica/pica/machdep.c file arch/pica/pica/mainbus.c file arch/pica/pica/minidebug.c diff --git a/sys/arch/pica/dev/asc.c b/sys/arch/pica/dev/asc.c index a9dae3585a7..a5d106cfc6a 100644 --- a/sys/arch/pica/dev/asc.c +++ b/sys/arch/pica/dev/asc.c @@ -720,17 +720,17 @@ asc_reset(asc, regs) * Reset chip and wait till done */ regs->asc_cmd = ASC_CMD_RESET; - MachEmptyWriteBuffer(); DELAY(25); + wbflush(); DELAY(25); /* spec says this is needed after reset */ regs->asc_cmd = ASC_CMD_NOP; - MachEmptyWriteBuffer(); DELAY(25); + wbflush(); DELAY(25); /* * Set up various chip parameters */ regs->asc_ccf = asc->ccf; - MachEmptyWriteBuffer(); DELAY(25); + wbflush(); DELAY(25); regs->asc_sel_timo = asc->timeout_250; /* restore our ID */ regs->asc_cnfg1 = asc->sc_id | ASC_CNFG1_P_CHECK; @@ -741,7 +741,7 @@ asc_reset(asc, regs) ASC_TC_PUT(regs, 0); regs->asc_syn_p = asc->min_period; regs->asc_syn_o = 0; /* async for now */ - MachEmptyWriteBuffer(); + wbflush(); } /* @@ -1257,7 +1257,7 @@ printf("asc_intr: fifo flush %d len %d fifo %x\n", fifo, len, regs->asc_fifo); */ done: - MachEmptyWriteBuffer(); + wbflush(); /* * If the next interrupt comes in immediatly the interrupt * dispatcher (which we are returning to) will catch it @@ -1781,13 +1781,13 @@ asc_sendsync(asc, status, ss, ir) /* send the extended synchronous negotiation message */ regs->asc_fifo = SCSI_EXTENDED_MSG; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = 3; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = SCSI_SYNCHRONOUS_XFER; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = SCSI_MIN_PERIOD; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = ASC_MAX_OFFSET; /* state to resume after we see the sync reply message */ state->script = asc->script + 2; @@ -1812,13 +1812,13 @@ asc_replysync(asc, status, ss, ir) #endif /* send synchronous transfer in response to a request */ regs->asc_fifo = SCSI_EXTENDED_MSG; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = 3; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = SCSI_SYNCHRONOUS_XFER; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = asc_to_scsi_period[state->sync_period] * asc->tb_ticks; - MachEmptyWriteBuffer(); + wbflush(); regs->asc_fifo = state->sync_offset; regs->asc_cmd = ASC_CMD_XFER_INFO; readback(regs->asc_cmd); diff --git a/sys/arch/pica/dev/dma.c b/sys/arch/pica/dev/dma.c index 4c897db593f..c2e744e598f 100644 --- a/sys/arch/pica/dev/dma.c +++ b/sys/arch/pica/dev/dma.c @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * from: @(#)rz.c 8.1 (Berkeley) 7/29/93 - * $Id: dma.c,v 1.4 1996/05/02 07:59:37 pefo Exp $ + * $Id: dma.c,v 1.5 1996/06/06 23:06:26 deraadt Exp $ */ /* @@ -86,7 +86,7 @@ picaDmaInit() free_dma_pte->queue.next = NULL; free_dma_pte->queue.size = PICA_TL_SIZE / sizeof(dma_pte_t); - out32(PICA_SYS_TL_BASE, MACH_UNCACHED_TO_PHYS(map)); + out32(PICA_SYS_TL_BASE, UNCACHED_TO_PHYS(map)); out32(PICA_SYS_TL_LIMIT, PICA_TL_SIZE); out32(PICA_SYS_TL_IVALID, 0); } @@ -194,7 +194,7 @@ picaDmaTLBMap(dma_softc_t *sc) va = sc->req_va; while(nbytes > 0) { if(va < VM_MIN_KERNEL_ADDRESS) { - pa = MACH_CACHED_TO_PHYS(va); + pa = CACHED_TO_PHYS(va); } else { pa = pmap_extract(vm_map_pmap(phys_map), va); @@ -251,7 +251,7 @@ picaDmaStart(sc, addr, size, datain) sc->mode |= DMA_DIR_WRITE; regs->dma_enab = PICA_DMA_ENAB_RUN | PICA_DMA_ENAB_WRITE; } - MachEmptyWriteBuffer(); + wbflush(); } /* diff --git a/sys/arch/pica/dev/if_sn.c b/sys/arch/pica/dev/if_sn.c index 12bb28dde7e..089b6867c92 100644 --- a/sys/arch/pica/dev/if_sn.c +++ b/sys/arch/pica/dev/if_sn.c @@ -51,8 +51,7 @@ typedef unsigned char uchar; #define SWR(a, x) (a) = (x) #define SRD(a) ((a) & 0xffff) -#include <machine/machConst.h> -#define wbflush() MachEmptyWriteBuffer() +#include <machine/cpu.h> /* * Statistics collected over time @@ -498,7 +497,6 @@ void snreset(sc) struct sn_softc *sc; { - printf("snreset\n"); snstop(sc); sninit(sc); } diff --git a/sys/arch/pica/include/ansi.h b/sys/arch/pica/include/ansi.h index 1b329b0d39c..59add98be6e 100644 --- a/sys/arch/pica/include/ansi.h +++ b/sys/arch/pica/include/ansi.h @@ -1,3 +1,4 @@ +/* $OpenBSD: ansi.h,v 1.2 1996/06/06 23:06:29 deraadt Exp $ */ /* $NetBSD: ansi.h,v 1.5 1994/10/26 21:09:33 cgd Exp $ */ /*- diff --git a/sys/arch/pica/include/asm.h b/sys/arch/pica/include/asm.h index f1dbf9e7b93..5b3683f86b1 100644 --- a/sys/arch/pica/include/asm.h +++ b/sys/arch/pica/include/asm.h @@ -1,3 +1,5 @@ +/* $OpenBSD: asm.h,v 1.2 1996/06/06 23:06:30 deraadt Exp $ */ + /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -33,15 +35,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 - * $Id: asm.h,v 1.1 1996/05/02 08:18:33 pefo Exp $ - */ - -/* - * machAsmDefs.h -- - * - * Macros used when writing assembler programs. - * * Copyright (C) 1989 Digital Equipment Corporation. * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby granted, @@ -49,10 +42,6 @@ * Digital Equipment Corporation makes no representations about the * suitability of this software for any purpose. It is provided "as is" * without express or implied warranty. - * - * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, - * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) - * $Id: asm.h,v 1.1 1996/05/02 08:18:33 pefo Exp $ */ #ifndef _MACHASMDEFS diff --git a/sys/arch/pica/include/autoconf.h b/sys/arch/pica/include/autoconf.h index 42538ef9c36..a65e08cc8e6 100644 --- a/sys/arch/pica/include/autoconf.h +++ b/sys/arch/pica/include/autoconf.h @@ -1,3 +1,4 @@ +/* $OpenBSD: autoconf.h,v 1.2 1996/06/06 23:06:31 deraadt Exp $ */ /* $NetBSD: autoconf.h,v 1.1 1995/02/13 23:07:31 cgd Exp $ */ /* diff --git a/sys/arch/pica/include/bsd-aout.h b/sys/arch/pica/include/bsd-aout.h index 5d496ff1d09..df9ab03dcb4 100644 --- a/sys/arch/pica/include/bsd-aout.h +++ b/sys/arch/pica/include/bsd-aout.h @@ -1,3 +1,5 @@ +/* $OpenBSD: bsd-aout.h,v 1.2 1996/06/06 23:06:32 deraadt Exp $ */ + /* bsd-aout.h 4.4bsd a.out format, for backwards compatibility... */ diff --git a/sys/arch/pica/include/bus.h b/sys/arch/pica/include/bus.h index e6a5f66e126..21a3d42b122 100644 --- a/sys/arch/pica/include/bus.h +++ b/sys/arch/pica/include/bus.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bus.h,v 1.1 1996/05/02 08:18:34 pefo Exp $ */ +/* $OpenBSD: bus.h,v 1.2 1996/06/06 23:06:33 deraadt Exp $ */ /* $NetBSD: bus.h,v 1.2 1996/04/05 23:59:37 thorpej Exp $ */ /* @@ -31,8 +31,8 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef _I386_BUS_H_ -#define _I386_BUS_H_ +#ifndef _PICA_BUS_H_ +#define _PICA_BUS_H_ #include <machine/pio.h> @@ -123,4 +123,4 @@ void bus_mem_unmap __P((bus_chipset_tag_t t, bus_mem_handle_t memh, #define bus_from_host_4(t, v) (v) #define bus_from_host_8(t, v) (v) -#endif /* _I386_BUS_H_ */ +#endif /* _PICA_BUS_H_ */ diff --git a/sys/arch/pica/include/cdefs.h b/sys/arch/pica/include/cdefs.h index 1b4a6cc51ee..335a97be479 100644 --- a/sys/arch/pica/include/cdefs.h +++ b/sys/arch/pica/include/cdefs.h @@ -1,3 +1,4 @@ +/* $OpenBSD: cdefs.h,v 1.2 1996/06/06 23:06:34 deraadt Exp $ */ /* $NetBSD: cdefs.h,v 1.3 1995/05/03 06:04:54 mellon Exp $ */ /* diff --git a/sys/arch/pica/include/cpu.h b/sys/arch/pica/include/cpu.h index 6f46be6068b..8675e596585 100644 --- a/sys/arch/pica/include/cpu.h +++ b/sys/arch/pica/include/cpu.h @@ -1,3 +1,5 @@ +/* $OpenBSD: cpu.h,v 1.2 1996/06/06 23:06:35 deraadt Exp $ */ + /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -33,14 +35,244 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 - * $Id: cpu.h,v 1.1 1995/10/18 10:39:11 deraadt Exp $ */ #ifndef _CPU_H_ #define _CPU_H_ -#include <machine/machConst.h> +#ifdef _KERNEL + +#define KUSEG_ADDR 0x0 +#define CACHED_MEMORY_ADDR 0x80000000 +#define UNCACHED_MEMORY_ADDR 0xa0000000 +#define KSEG2_ADDR 0xc0000000 +#define MAX_MEM_ADDR 0xbe000000 +#define RESERVED_ADDR 0xbfc80000 + +#define CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) +#define PHYS_TO_CACHED(x) ((unsigned)(x) | CACHED_MEMORY_ADDR) +#define UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) +#define PHYS_TO_UNCACHED(x) ((unsigned)(x) | UNCACHED_MEMORY_ADDR) +#define VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR) + +#define CODE_START 0x80080000 + +/* + * The bits in the cause register. + * + * CR_BR_DELAY Exception happened in branch delay slot. + * CR_COP_ERR Coprocessor error. + * CR_IP Interrupt pending bits defined below. + * CR_EXC_CODE The exception type (see exception codes below). + */ +#define CR_BR_DELAY 0x80000000 +#define CR_COP_ERR 0x30000000 +#define CR_EXC_CODE 0x0000007C +#define CR_IP 0x0000FF00 +#define CR_EXC_CODE_SHIFT 2 + +/* + * The bits in the status register. All bits are active when set to 1. + */ +#define SR_COP_USABILITY 0xf0000000 +#define SR_COP_0_BIT 0x10000000 +#define SR_COP_1_BIT 0x20000000 +#define SR_RP 0x08000000 +#define SR_FR_32 0x04000000 +#define SR_RE 0x02000000 +#define SR_BOOT_EXC_VEC 0x00400000 +#define SR_TLB_SHUTDOWN 0x00200000 +#define SR_SOFT_RESET 0x00100000 +#define SR_DIAG_CH 0x00040000 +#define SR_DIAG_CE 0x00020000 +#define SR_DIAG_PE 0x00010000 +#define SR_KX 0x00000080 +#define SR_SX 0x00000040 +#define SR_UX 0x00000020 +#define SR_KSU_MASK 0x00000018 +#define SR_KSU_USER 0x00000010 +#define SR_KSU_SUPER 0x00000008 +#define SR_KSU_KERNEL 0x00000000 +#define SR_ERL 0x00000004 +#define SR_EXL 0x00000002 +#define SR_INT_ENAB 0x00000001 +/*#define SR_INT_MASK 0x0000ff00*/ + +/* + * The interrupt masks. + * If a bit in the mask is 1 then the interrupt is enabled (or pending). + */ +#define INT_MASK 0x7f00 +#define INT_MASK_5 0x8000 /* Not used (on chip timer) */ +#define INT_MASK_4 0x4000 +#define INT_MASK_3 0x2000 +#define INT_MASK_2 0x1000 +#define INT_MASK_1 0x0800 +#define INT_MASK_0 0x0400 +#define HARD_INT_MASK 0x7c00 +#define SOFT_INT_MASK_1 0x0200 +#define SOFT_INT_MASK_0 0x0100 + +/* + * The bits in the context register. + */ +#define CNTXT_PTE_BASE 0xFF800000 +#define CNTXT_BAD_VPN2 0x007FFFF0 + +/* + * Location of exception vectors. + */ +#define RESET_EXC_VEC 0xBFC00000 +#define TLB_MISS_EXC_VEC 0x80000000 +#define XTLB_MISS_EXC_VEC 0x80000080 +#define CACHE_ERR_EXC_VEC 0x80000100 +#define GEN_EXC_VEC 0x80000180 + +/* + * Coprocessor 0 registers: + */ +#define COP_0_TLB_INDEX $0 +#define COP_0_TLB_RANDOM $1 +#define COP_0_TLB_LO0 $2 +#define COP_0_TLB_LO1 $3 +#define COP_0_TLB_CONTEXT $4 +#define COP_0_TLB_PG_MASK $5 +#define COP_0_TLB_WIRED $6 +#define COP_0_BAD_VADDR $8 +#define COP_0_TLB_HI $10 +#define COP_0_STATUS_REG $12 +#define COP_0_CAUSE_REG $13 +#define COP_0_EXC_PC $14 +#define COP_0_PRID $15 +#define COP_0_CONFIG $16 +#define COP_0_LLADDR $17 +#define COP_0_WATCH_LO $18 +#define COP_0_WATCH_HI $19 +#define COP_0_TLB_XCONTEXT $20 +#define COP_0_ECC $26 +#define COP_0_CACHE_ERR $27 +#define COP_0_TAG_LO $28 +#define COP_0_TAG_HI $29 +#define COP_0_ERROR_PC $30 + +/* + * Values for the code field in a break instruction. + */ +#define BREAK_INSTR 0x0000000d +#define BREAK_VAL_MASK 0x03ff0000 +#define BREAK_VAL_SHIFT 16 +#define BREAK_KDB_VAL 512 +#define BREAK_SSTEP_VAL 513 +#define BREAK_BRKPT_VAL 514 +#define BREAK_SOVER_VAL 515 +#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) +#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) +#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) +#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) + +/* + * Mininum and maximum cache sizes. + */ +#define MIN_CACHE_SIZE (16 * 1024) +#define MAX_CACHE_SIZE (256 * 1024) + +/* + * The floating point version and status registers. + */ +#define FPC_ID $0 +#define FPC_CSR $31 + +/* + * The floating point coprocessor status register bits. + */ +#define FPC_ROUNDING_BITS 0x00000003 +#define FPC_ROUND_RN 0x00000000 +#define FPC_ROUND_RZ 0x00000001 +#define FPC_ROUND_RP 0x00000002 +#define FPC_ROUND_RM 0x00000003 +#define FPC_STICKY_BITS 0x0000007c +#define FPC_STICKY_INEXACT 0x00000004 +#define FPC_STICKY_UNDERFLOW 0x00000008 +#define FPC_STICKY_OVERFLOW 0x00000010 +#define FPC_STICKY_DIV0 0x00000020 +#define FPC_STICKY_INVALID 0x00000040 +#define FPC_ENABLE_BITS 0x00000f80 +#define FPC_ENABLE_INEXACT 0x00000080 +#define FPC_ENABLE_UNDERFLOW 0x00000100 +#define FPC_ENABLE_OVERFLOW 0x00000200 +#define FPC_ENABLE_DIV0 0x00000400 +#define FPC_ENABLE_INVALID 0x00000800 +#define FPC_EXCEPTION_BITS 0x0003f000 +#define FPC_EXCEPTION_INEXACT 0x00001000 +#define FPC_EXCEPTION_UNDERFLOW 0x00002000 +#define FPC_EXCEPTION_OVERFLOW 0x00004000 +#define FPC_EXCEPTION_DIV0 0x00008000 +#define FPC_EXCEPTION_INVALID 0x00010000 +#define FPC_EXCEPTION_UNIMPL 0x00020000 +#define FPC_COND_BIT 0x00800000 +#define FPC_FLUSH_BIT 0x01000000 +#define FPC_MBZ_BITS 0xfe7c0000 + +/* + * Constants to determine if have a floating point instruction. + */ +#define OPCODE_SHIFT 26 +#define OPCODE_C1 0x11 + +/* + * The low part of the TLB entry. + */ +#define VMTLB_PF_NUM 0x3fffffc0 +#define VMTLB_ATTR_MASK 0x00000038 +#define VMTLB_MOD_BIT 0x00000004 +#define VMTLB_VALID_BIT 0x00000002 +#define VMTLB_GLOBAL_BIT 0x00000001 + +#define VMTLB_PHYS_PAGE_SHIFT 6 + +/* + * The high part of the TLB entry. + */ +#define VMTLB_VIRT_PAGE_NUM 0xffffe000 +#define VMTLB_PID 0x000000ff +#define VMTLB_PID_SHIFT 0 +#define VMTLB_VIRT_PAGE_SHIFT 12 + +/* + * The number of TLB entries and the first one that write random hits. + */ +#define VMNUM_TLB_ENTRIES 48 +#define VMWIRED_ENTRIES 8 + +/* + * The number of process id entries. + */ +#define VMNUM_PIDS 256 + +/* + * TLB probe return codes. + */ +#define VMTLB_NOT_FOUND 0 +#define VMTLB_FOUND 1 +#define VMTLB_FOUND_WITH_PATCH 2 +#define VMTLB_PROBE_ERROR 3 + +/* + * Kernel virtual address for user page table entries + * (i.e., the address for the context register). + */ +#define VMPTE_BASE 0xFF800000 + +#endif /* _KERNEL */ /* * Exported definitions unique to pica/mips cpu support. @@ -56,6 +288,7 @@ #define cpu_set_init_frame(p, fp) /* nothing */ #define cpu_swapout(p) panic("cpu_swapout: can't get here"); +#ifndef _LOCORE /* * Arguments to hardclock and gatherstats encapsulate the previous * machine state in an opaque clockframe. @@ -65,9 +298,8 @@ struct clockframe { int sr; /* status register at time of interrupt */ }; -#define CLKF_USERMODE(framep) ((framep)->sr & MACH_SR_KSU_USER) -#define CLKF_BASEPRI(framep) \ - ((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENAB)) == 0) +#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) +#define CLKF_BASEPRI(framep) ((~(framep)->sr & (INT_MASK|SR_INT_ENAB)) == 0) #define CLKF_PC(framep) ((framep)->pc) #define CLKF_INTR(framep) (0) @@ -126,6 +358,8 @@ union cpuprid { { "console_device", CTLTYPE_STRUCT }, \ } +#endif /* !_LOCORE */ + /* * MIPS CPU types (cp_imp). */ @@ -165,7 +399,7 @@ union cpuprid { #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ #define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */ -#ifdef _KERNEL +#if defined(_KERNEL) && !defined(_LOCORE) union cpuprid cpu_id; union cpuprid fpu_id; u_int machPrimaryDataCacheSize; diff --git a/sys/arch/pica/include/disklabel.h b/sys/arch/pica/include/disklabel.h index f84cf756a1c..40e913434b4 100644 --- a/sys/arch/pica/include/disklabel.h +++ b/sys/arch/pica/include/disklabel.h @@ -1,3 +1,4 @@ +/* $OpenBSD: disklabel.h,v 1.2 1996/06/06 23:06:36 deraadt Exp $ */ /* $NetBSD: disklabel.h,v 1.2 1995/01/18 06:37:55 mellon Exp $ */ /* diff --git a/sys/arch/pica/include/display.h b/sys/arch/pica/include/display.h index 60406dce661..06ab0512ed2 100644 --- a/sys/arch/pica/include/display.h +++ b/sys/arch/pica/include/display.h @@ -1,7 +1,8 @@ +/* $OpenBSD: display.h,v 1.2 1996/06/06 23:06:36 deraadt Exp $ */ + /* * IBM PC display definitions * - * $Id: display.h,v 1.1 1995/10/18 10:39:15 deraadt Exp $ */ /* Color attributes for foreground text */ diff --git a/sys/arch/pica/include/elf.h b/sys/arch/pica/include/elf.h index 5cb8b03421d..acdbbed98b4 100644 --- a/sys/arch/pica/include/elf.h +++ b/sys/arch/pica/include/elf.h @@ -1,3 +1,4 @@ +/* $OpenBSD: elf.h,v 1.2 1996/06/06 23:06:38 deraadt Exp $ */ /* $NetBSD: elf.h,v 1.2 1995/03/28 18:19:14 jtc Exp $ */ /* diff --git a/sys/arch/pica/include/endian.h b/sys/arch/pica/include/endian.h index 82c1194223c..25566c74236 100644 --- a/sys/arch/pica/include/endian.h +++ b/sys/arch/pica/include/endian.h @@ -1,3 +1,4 @@ +/* $OpenBSD: endian.h,v 1.3 1996/06/06 23:06:38 deraadt Exp $ */ /* $NetBSD: endian.h,v 1.4 1994/10/26 21:09:38 cgd Exp $ */ /* diff --git a/sys/arch/pica/include/exec.h b/sys/arch/pica/include/exec.h index d7ec6218317..88cb0cf451d 100644 --- a/sys/arch/pica/include/exec.h +++ b/sys/arch/pica/include/exec.h @@ -1,3 +1,4 @@ +/* $OpenBSD: exec.h,v 1.4 1996/06/06 23:06:39 deraadt Exp $ */ /* $NetBSD: exec.h,v 1.5 1994/10/26 21:09:39 cgd Exp $ */ /*- diff --git a/sys/arch/pica/include/float.h b/sys/arch/pica/include/float.h index 2c172c75763..2381312497d 100644 --- a/sys/arch/pica/include/float.h +++ b/sys/arch/pica/include/float.h @@ -1,3 +1,4 @@ +/* $OpenBSD: float.h,v 1.2 1996/06/06 23:06:40 deraadt Exp $ */ /* $NetBSD: float.h,v 1.7 1995/06/20 20:45:50 jtc Exp $ */ /* diff --git a/sys/arch/pica/include/ieeefp.h b/sys/arch/pica/include/ieeefp.h index 65ea3fed16c..d33b628596e 100644 --- a/sys/arch/pica/include/ieeefp.h +++ b/sys/arch/pica/include/ieeefp.h @@ -1,3 +1,5 @@ +/* $OpenBSD: ieeefp.h,v 1.2 1996/06/06 23:06:41 deraadt Exp $ */ + /* * Written by J.T. Conklin, Apr 11, 1995 * Public domain. diff --git a/sys/arch/pica/include/kbdreg.h b/sys/arch/pica/include/kbdreg.h index 10d0795352d..6c890fefbdd 100644 --- a/sys/arch/pica/include/kbdreg.h +++ b/sys/arch/pica/include/kbdreg.h @@ -1,7 +1,8 @@ +/* $OpenBSD: kbdreg.h,v 1.2 1996/06/06 23:06:42 deraadt Exp $ */ + /* * Keyboard definitions * - * $Id: kbdreg.h,v 1.1 1995/10/18 10:39:15 deraadt Exp $ */ #define KBSTATP (PICA_SYS_KBD + 0x61) /* controller status port (I) */ diff --git a/sys/arch/pica/include/kdbparam.h b/sys/arch/pica/include/kdbparam.h index 9104c87aa3c..b77f9b96af7 100644 --- a/sys/arch/pica/include/kdbparam.h +++ b/sys/arch/pica/include/kdbparam.h @@ -1,3 +1,4 @@ +/* $OpenBSD: kdbparam.h,v 1.2 1996/06/06 23:06:44 deraadt Exp $ */ /* $NetBSD: kdbparam.h,v 1.4 1994/10/26 21:09:42 cgd Exp $ */ /*- @@ -52,13 +53,13 @@ #define LPRMODE "%R" #define OFFMODE "+%R" -#define SETBP(ins) MACH_BREAK_BRKPT +#define SETBP(ins) BREAK_BRKPT /* return the program counter value modified if we are in a delay slot */ #define kdbgetpc(pcb) (kdbvar[kdbvarchk('t')] < 0 ? \ (pcb).pcb_regs[34] + 4 : (pcb).pcb_regs[34]) #define kdbishiddenreg(p) ((p) >= &kdbreglist[33]) -#define kdbisbreak(type) (((type) & MACH_CR_EXC_CODE) == 0x24) +#define kdbisbreak(type) (((type) & CR_EXC_CODE) == 0x24) /* check for address wrap around */ #define kdbaddrwrap(addr,newaddr) (((addr)^(newaddr)) >> 31) diff --git a/sys/arch/pica/include/limits.h b/sys/arch/pica/include/limits.h index b692e2885c6..4bad604ea0c 100644 --- a/sys/arch/pica/include/limits.h +++ b/sys/arch/pica/include/limits.h @@ -1,3 +1,4 @@ +/* $OpenBSD: limits.h,v 1.2 1996/06/06 23:06:45 deraadt Exp $ */ /* $NetBSD: limits.h,v 1.8 1995/03/28 18:19:16 jtc Exp $ */ /* diff --git a/sys/arch/pica/include/machAsmDefs.h b/sys/arch/pica/include/machAsmDefs.h deleted file mode 100644 index dfc42fcff23..00000000000 --- a/sys/arch/pica/include/machAsmDefs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * Ralph Campbell. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 - * $Id: machAsmDefs.h,v 1.1 1995/10/18 10:39:12 deraadt Exp $ - */ - -/* - * machAsmDefs.h -- - * - * Macros used when writing assembler programs. - * - * Copyright (C) 1989 Digital Equipment Corporation. - * Permission to use, copy, modify, and distribute this software and - * its documentation for any purpose and without fee is hereby granted, - * provided that the above copyright notice appears in all copies. - * Digital Equipment Corporation makes no representations about the - * suitability of this software for any purpose. It is provided "as is" - * without express or implied warranty. - * - * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, - * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) - * $Id: machAsmDefs.h,v 1.1 1995/10/18 10:39:12 deraadt Exp $ - */ - -#ifndef _MACHASMDEFS -#define _MACHASMDEFS - -#include <machine/regdef.h> - -/* - * Define -pg profile entry code. - */ -#if defined(GPROF) || defined(PROF) -#define MCOUNT .set noreorder; \ - .set noat; \ - move $1,$31; \ - jal _mcount; \ - subu sp,sp,8; \ - .set reorder; \ - .set at; -#else -#define MCOUNT -#endif - -/* - * LEAF(x) - * - * Declare a leaf routine. - */ -#define LEAF(x) \ - .globl x; \ - .ent x, 0; \ -x: ; \ - .frame sp, 0, ra; \ - MCOUNT - -/* - * NLEAF(x) - * - * Declare a non-profiled leaf routine. - */ -#define NLEAF(x) \ - .globl x; \ - .ent x, 0; \ -x: ; \ - .frame sp, 0, ra - -/* - * ALEAF -- declare alternate entry to a leaf routine. - */ -#define ALEAF(x) \ - .globl x; \ -x: - -/* - * NON_LEAF(x) - * - * Declare a non-leaf routine (a routine that makes other C calls). - */ -#define NON_LEAF(x, fsize, retpc) \ - .globl x; \ - .ent x, 0; \ -x: ; \ - .frame sp, fsize, retpc; \ - MCOUNT - -/* - * NNON_LEAF(x) - * - * Declare a non-profiled non-leaf routine - * (a routine that makes other C calls). - */ -#define NNON_LEAF(x, fsize, retpc) \ - .globl x; \ - .ent x, 0; \ -x: ; \ - .frame sp, fsize, retpc - -/* - * END(x) - * - * Mark end of a procedure. - */ -#define END(x) \ - .end x - -#define STAND_FRAME_SIZE 24 -#define STAND_RA_OFFSET 20 - -/* - * Macros to panic and printf from assembly language. - */ -#define PANIC(msg) \ - la a0, 9f; \ - jal panic; \ - MSG(msg) - -#define PRINTF(msg) \ - la a0, 9f; \ - jal printf; \ - MSG(msg) - -#define MSG(msg) \ - .rdata; \ -9: .asciiz msg; \ - .text - -#define ASMSTR(str) \ - .asciiz str; \ - .align 3 - -#endif /* _MACHASMDEFS */ diff --git a/sys/arch/pica/include/machConst.h b/sys/arch/pica/include/machConst.h deleted file mode 100644 index bdbeb576662..00000000000 --- a/sys/arch/pica/include/machConst.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * Ralph Campbell and Rick Macklem. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)machConst.h 8.1 (Berkeley) 6/10/93 - * $Id: machConst.h,v 1.1 1995/10/18 10:39:12 deraadt Exp $ - * - * machConst.h -- - * - * Machine dependent constants. - * - * Copyright (C) 1989 Digital Equipment Corporation. - * Permission to use, copy, modify, and distribute this software and - * its documentation for any purpose and without fee is hereby granted, - * provided that the above copyright notice appears in all copies. - * Digital Equipment Corporation makes no representations about the - * suitability of this software for any purpose. It is provided "as is" - * without express or implied warranty. - * - * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, - * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) - * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, - * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) - * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, - * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) - * $Id: machConst.h,v 1.1 1995/10/18 10:39:12 deraadt Exp $ - */ - -#ifndef _MACHCONST -#define _MACHCONST - -#define MACH_KUSEG_ADDR 0x0 -#define MACH_CACHED_MEMORY_ADDR 0x80000000 -#define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 -#define MACH_KSEG2_ADDR 0xc0000000 -#define MACH_MAX_MEM_ADDR 0xbe000000 -#define MACH_RESERVED_ADDR 0xbfc80000 - -#define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) -#define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) -#define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) -#define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) -#define MACH_VA_TO_CINDEX(x) \ - ((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR) - -#define MACH_CODE_START 0x80080000 - -/* - * The bits in the cause register. - * - * MACH_CR_BR_DELAY Exception happened in branch delay slot. - * MACH_CR_COP_ERR Coprocessor error. - * MACH_CR_IP Interrupt pending bits defined below. - * MACH_CR_EXC_CODE The exception type (see exception codes below). - */ -#define MACH_CR_BR_DELAY 0x80000000 -#define MACH_CR_COP_ERR 0x30000000 -#define MACH_CR_EXC_CODE 0x0000007C -#define MACH_CR_IP 0x0000FF00 -#define MACH_CR_EXC_CODE_SHIFT 2 - -/* - * The bits in the status register. All bits are active when set to 1. - */ -#define MACH_SR_COP_USABILITY 0xf0000000 -#define MACH_SR_COP_0_BIT 0x10000000 -#define MACH_SR_COP_1_BIT 0x20000000 -#define MACH_SR_RP 0x08000000 -#define MACH_SR_FR_32 0x04000000 -#define MACH_SR_RE 0x02000000 -#define MACH_SR_BOOT_EXC_VEC 0x00400000 -#define MACH_SR_TLB_SHUTDOWN 0x00200000 -#define MACH_SR_SOFT_RESET 0x00100000 -#define MACH_SR_DIAG_CH 0x00040000 -#define MACH_SR_DIAG_CE 0x00020000 -#define MACH_SR_DIAG_PE 0x00010000 -#define MACH_SR_KX 0x00000080 -#define MACH_SR_SX 0x00000040 -#define MACH_SR_UX 0x00000020 -#define MACH_SR_KSU_MASK 0x00000018 -#define MACH_SR_KSU_USER 0x00000010 -#define MACH_SR_KSU_SUPER 0x00000008 -#define MACH_SR_KSU_KERNEL 0x00000000 -#define MACH_SR_ERL 0x00000004 -#define MACH_SR_EXL 0x00000002 -#define MACH_SR_INT_ENAB 0x00000001 -/*#define MACH_SR_INT_MASK 0x0000ff00*/ - -/* - * The interrupt masks. - * If a bit in the mask is 1 then the interrupt is enabled (or pending). - */ -#define MACH_INT_MASK 0x7f00 -#define MACH_INT_MASK_5 0x8000 /* Not used (on chip timer) */ -#define MACH_INT_MASK_4 0x4000 -#define MACH_INT_MASK_3 0x2000 -#define MACH_INT_MASK_2 0x1000 -#define MACH_INT_MASK_1 0x0800 -#define MACH_INT_MASK_0 0x0400 -#define MACH_HARD_INT_MASK 0x7c00 -#define MACH_SOFT_INT_MASK_1 0x0200 -#define MACH_SOFT_INT_MASK_0 0x0100 - -/* - * The bits in the context register. - */ -#define MACH_CNTXT_PTE_BASE 0xFF800000 -#define MACH_CNTXT_BAD_VPN2 0x007FFFF0 - -/* - * Location of exception vectors. - */ -#define MACH_RESET_EXC_VEC 0xBFC00000 -#define MACH_TLB_MISS_EXC_VEC 0x80000000 -#define MACH_XTLB_MISS_EXC_VEC 0x80000080 -#define MACH_CACHE_ERR_EXC_VEC 0x80000100 -#define MACH_GEN_EXC_VEC 0x80000180 - -/* - * Coprocessor 0 registers: - */ -#define MACH_COP_0_TLB_INDEX $0 -#define MACH_COP_0_TLB_RANDOM $1 -#define MACH_COP_0_TLB_LO0 $2 -#define MACH_COP_0_TLB_LO1 $3 -#define MACH_COP_0_TLB_CONTEXT $4 -#define MACH_COP_0_TLB_PG_MASK $5 -#define MACH_COP_0_TLB_WIRED $6 -#define MACH_COP_0_BAD_VADDR $8 -#define MACH_COP_0_TLB_HI $10 -#define MACH_COP_0_STATUS_REG $12 -#define MACH_COP_0_CAUSE_REG $13 -#define MACH_COP_0_EXC_PC $14 -#define MACH_COP_0_PRID $15 -#define MACH_COP_0_CONFIG $16 -#define MACH_COP_0_LLADDR $17 -#define MACH_COP_0_WATCH_LO $18 -#define MACH_COP_0_WATCH_HI $19 -#define MACH_COP_0_TLB_XCONTEXT $20 -#define MACH_COP_0_ECC $26 -#define MACH_COP_0_CACHE_ERR $27 -#define MACH_COP_0_TAG_LO $28 -#define MACH_COP_0_TAG_HI $29 -#define MACH_COP_0_ERROR_PC $30 - -/* - * Values for the code field in a break instruction. - */ -#define MACH_BREAK_INSTR 0x0000000d -#define MACH_BREAK_VAL_MASK 0x03ff0000 -#define MACH_BREAK_VAL_SHIFT 16 -#define MACH_BREAK_KDB_VAL 512 -#define MACH_BREAK_SSTEP_VAL 513 -#define MACH_BREAK_BRKPT_VAL 514 -#define MACH_BREAK_SOVER_VAL 515 -#define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ - (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) -#define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ - (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) -#define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ - (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) -#define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \ - (MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT)) - -/* - * Mininum and maximum cache sizes. - */ -#define MACH_MIN_CACHE_SIZE (16 * 1024) -#define MACH_MAX_CACHE_SIZE (256 * 1024) - -/* - * The floating point version and status registers. - */ -#define MACH_FPC_ID $0 -#define MACH_FPC_CSR $31 - -/* - * The floating point coprocessor status register bits. - */ -#define MACH_FPC_ROUNDING_BITS 0x00000003 -#define MACH_FPC_ROUND_RN 0x00000000 -#define MACH_FPC_ROUND_RZ 0x00000001 -#define MACH_FPC_ROUND_RP 0x00000002 -#define MACH_FPC_ROUND_RM 0x00000003 -#define MACH_FPC_STICKY_BITS 0x0000007c -#define MACH_FPC_STICKY_INEXACT 0x00000004 -#define MACH_FPC_STICKY_UNDERFLOW 0x00000008 -#define MACH_FPC_STICKY_OVERFLOW 0x00000010 -#define MACH_FPC_STICKY_DIV0 0x00000020 -#define MACH_FPC_STICKY_INVALID 0x00000040 -#define MACH_FPC_ENABLE_BITS 0x00000f80 -#define MACH_FPC_ENABLE_INEXACT 0x00000080 -#define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 -#define MACH_FPC_ENABLE_OVERFLOW 0x00000200 -#define MACH_FPC_ENABLE_DIV0 0x00000400 -#define MACH_FPC_ENABLE_INVALID 0x00000800 -#define MACH_FPC_EXCEPTION_BITS 0x0003f000 -#define MACH_FPC_EXCEPTION_INEXACT 0x00001000 -#define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 -#define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 -#define MACH_FPC_EXCEPTION_DIV0 0x00008000 -#define MACH_FPC_EXCEPTION_INVALID 0x00010000 -#define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 -#define MACH_FPC_COND_BIT 0x00800000 -#define MACH_FPC_FLUSH_BIT 0x01000000 -#define MACH_FPC_MBZ_BITS 0xfe7c0000 - -/* - * Constants to determine if have a floating point instruction. - */ -#define MACH_OPCODE_SHIFT 26 -#define MACH_OPCODE_C1 0x11 - -/* - * The low part of the TLB entry. - */ -#define VMMACH_TLB_PF_NUM 0x3fffffc0 -#define VMMACH_TLB_ATTR_MASK 0x00000038 -#define VMMACH_TLB_MOD_BIT 0x00000004 -#define VMMACH_TLB_VALID_BIT 0x00000002 -#define VMMACH_TLB_GLOBAL_BIT 0x00000001 - -#define VMMACH_TLB_PHYS_PAGE_SHIFT 6 - -/* - * The high part of the TLB entry. - */ -#define VMMACH_TLB_VIRT_PAGE_NUM 0xffffe000 -#define VMMACH_TLB_PID 0x000000ff -#define VMMACH_TLB_PID_SHIFT 0 -#define VMMACH_TLB_VIRT_PAGE_SHIFT 12 - -/* - * The number of TLB entries and the first one that write random hits. - */ -#define VMMACH_NUM_TLB_ENTRIES 48 -#define VMMACH_WIRED_ENTRIES 8 - -/* - * The number of process id entries. - */ -#define VMMACH_NUM_PIDS 256 - -/* - * TLB probe return codes. - */ -#define VMMACH_TLB_NOT_FOUND 0 -#define VMMACH_TLB_FOUND 1 -#define VMMACH_TLB_FOUND_WITH_PATCH 2 -#define VMMACH_TLB_PROBE_ERROR 3 - -/* - * Kernel virtual address for user page table entries - * (i.e., the address for the context register). - */ -#define VMMACH_PTE_BASE 0xFF800000 - -#endif /* _MACHCONST */ diff --git a/sys/arch/pica/include/mips_opcode.h b/sys/arch/pica/include/mips_opcode.h index 7301b3d6548..4ff925bba08 100644 --- a/sys/arch/pica/include/mips_opcode.h +++ b/sys/arch/pica/include/mips_opcode.h @@ -1,3 +1,5 @@ +/* $OpenBSD: mips_opcode.h,v 1.2 1996/06/06 23:06:50 deraadt Exp $ */ + /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -34,7 +36,6 @@ * SUCH DAMAGE. * * from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93 - * $Id: mips_opcode.h,v 1.1 1995/10/18 10:39:13 deraadt Exp $ */ /* diff --git a/sys/arch/pica/include/mouse.h b/sys/arch/pica/include/mouse.h index 9c26917d77e..366cb5ee690 100644 --- a/sys/arch/pica/include/mouse.h +++ b/sys/arch/pica/include/mouse.h @@ -1,3 +1,4 @@ +/* $OpenBSD: mouse.h,v 1.2 1996/06/06 23:06:52 deraadt Exp $ */ /* $NetBSD: mouse.h,v 1.4 1994/10/27 04:16:10 cgd Exp $ */ /*- diff --git a/sys/arch/pica/include/param.h b/sys/arch/pica/include/param.h index 10f068449c1..23cc08d97f4 100644 --- a/sys/arch/pica/include/param.h +++ b/sys/arch/pica/include/param.h @@ -1,3 +1,5 @@ +/* $OpenBSD: param.h,v 1.4 1996/06/06 23:06:53 deraadt Exp $ */ + /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -35,11 +37,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: machparam.h 1.11 89/08/14 - * - * + * from: Utah Hdr: machparam.h 1.11 89/08/14 * from: @(#)param.h 8.1 (Berkeley) 6/10/93 - * $Id: param.h,v 1.3 1996/05/02 07:59:39 pefo Exp $ */ /* diff --git a/sys/arch/pica/include/pcb.h b/sys/arch/pica/include/pcb.h index 200a8d5a57e..717ed8682e8 100644 --- a/sys/arch/pica/include/pcb.h +++ b/sys/arch/pica/include/pcb.h @@ -1,3 +1,5 @@ +/* $OpenBSD: pcb.h,v 1.2 1996/06/06 23:06:55 deraadt Exp $ */ + /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -35,10 +37,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: pcb.h 1.13 89/04/23 - * + * from: Utah Hdr: pcb.h 1.13 89/04/23 * from: @(#)pcb.h 8.1 (Berkeley) 6/10/93 - * $Id: pcb.h,v 1.1 1995/10/18 10:39:13 deraadt Exp $ */ /* diff --git a/sys/arch/pica/include/pccons.h b/sys/arch/pica/include/pccons.h index bd8899fa60b..ab377b9a71b 100644 --- a/sys/arch/pica/include/pccons.h +++ b/sys/arch/pica/include/pccons.h @@ -1,7 +1,8 @@ +/* $OpenBSD: pccons.h,v 1.3 1996/06/06 23:06:56 deraadt Exp $ */ + /* * pccons.h -- pccons ioctl definitions * - * $Id: pccons.h,v 1.2 1996/05/01 18:23:41 pefo Exp $ */ #ifndef _PCCONS_H_ diff --git a/sys/arch/pica/include/pio.h b/sys/arch/pica/include/pio.h index 80981ef743c..d56e7b8be03 100644 --- a/sys/arch/pica/include/pio.h +++ b/sys/arch/pica/include/pio.h @@ -1,3 +1,4 @@ +/* $OpenBSD: pio.h,v 1.3 1996/06/06 23:06:57 deraadt Exp $ */ /* $NetBSD: pio.h,v 1.11 1995/04/22 03:59:59 mycroft Exp $ */ /* diff --git a/sys/arch/pica/include/pmap.h b/sys/arch/pica/include/pmap.h index bc06048c681..d53fa0ce14f 100644 --- a/sys/arch/pica/include/pmap.h +++ b/sys/arch/pica/include/pmap.h @@ -1,3 +1,5 @@ +/* $OpenBSD: pmap.h,v 1.3 1996/06/06 23:06:59 deraadt Exp $ */ + /* * Copyright (c) 1987 Carnegie-Mellon University * Copyright (c) 1992, 1993 @@ -35,7 +37,6 @@ * SUCH DAMAGE. * * from: @(#)pmap.h 8.1 (Berkeley) 6/10/93 - * $Id: pmap.h,v 1.2 1996/05/01 18:23:46 pefo Exp $ */ #ifndef _PMAP_MACHINE_ diff --git a/sys/arch/pica/include/proc.h b/sys/arch/pica/include/proc.h index 202d9562314..4cdb693c301 100644 --- a/sys/arch/pica/include/proc.h +++ b/sys/arch/pica/include/proc.h @@ -1,3 +1,4 @@ +/* $OpenBSD: proc.h,v 1.2 1996/06/06 23:07:00 deraadt Exp $ */ /* $NetBSD: proc.h,v 1.4 1994/10/26 21:09:52 cgd Exp $ */ /* diff --git a/sys/arch/pica/include/profile.h b/sys/arch/pica/include/profile.h index 11e2d0ef118..821922edfc1 100644 --- a/sys/arch/pica/include/profile.h +++ b/sys/arch/pica/include/profile.h @@ -1,3 +1,5 @@ +/* $OpenBSD: profile.h,v 1.4 1996/06/06 23:07:01 deraadt Exp $ */ + /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -34,7 +36,6 @@ * SUCH DAMAGE. * * from: @(#)profile.h 8.1 (Berkeley) 6/10/93 - * $Id: profile.h,v 1.3 1996/05/01 18:23:48 pefo Exp $ */ #define _MCOUNT_DECL static void ___mcount diff --git a/sys/arch/pica/include/psl.h b/sys/arch/pica/include/psl.h index 80366abca5a..8de0bebec15 100644 --- a/sys/arch/pica/include/psl.h +++ b/sys/arch/pica/include/psl.h @@ -1,3 +1,5 @@ +/* $OpenBSD: psl.h,v 1.2 1996/06/06 23:07:03 deraadt Exp $ */ + /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -34,35 +36,34 @@ * SUCH DAMAGE. * * from: @(#)psl.h 8.1 (Berkeley) 6/10/93 - * $Id: psl.h,v 1.1 1995/10/18 10:39:13 deraadt Exp $ */ #include <machine/machConst.h> -#define PSL_LOWIPL (MACH_INT_MASK | MACH_SR_INT_ENAB) +#define PSL_LOWIPL (INT_MASK | SR_INT_ENAB) #define PSL_USERSET ( \ - MACH_SR_KSU_USER | \ - MACH_SR_INT_ENAB | \ - MACH_SR_EXL | \ - MACH_INT_MASK) + SR_KSU_USER | \ + SR_INT_ENAB | \ + SR_EXL | \ + INT_MASK) #define PSL_USERCLR ( \ - MACH_SR_COP_USABILITY | \ - MACH_SR_BOOT_EXC_VEC | \ - MACH_SR_TLB_SHUTDOWN | \ - MACH_SR_PARITY_ERR | \ - MACH_SR_CACHE_MISS | \ - MACH_SR_PARITY_ZERO | \ - MACH_SR_SWAP_CACHES | \ - MACH_SR_ISOL_CACHES | \ - MACH_SR_KU_CUR | \ - MACH_SR_INT_ENA_CUR | \ - MACH_SR_MBZ) + SR_COP_USABILITY | \ + SR_BOOT_EXC_VEC | \ + SR_TLB_SHUTDOWN | \ + SR_PARITY_ERR | \ + SR_CACHE_MISS | \ + SR_PARITY_ZERO | \ + SR_SWAP_CACHES | \ + SR_ISOL_CACHES | \ + SR_KU_CUR | \ + SR_INT_ENA_CUR | \ + SR_MBZ) /* * Macros to decode processor status word. */ -#define USERMODE(ps) (((ps) & MACH_SR_KSU_MASK) == MACH_SR_KSU_USER) -#define BASEPRI(ps) (((ps) & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) \ - == (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) +#define USERMODE(ps) (((ps) & SR_KSU_MASK) == SR_KSU_USER) +#define BASEPRI(ps) (((ps) & (INT_MASK | SR_INT_ENA_PREV)) \ + == (INT_MASK | SR_INT_ENA_PREV)) diff --git a/sys/arch/pica/include/pte.h b/sys/arch/pica/include/pte.h index 898b653b7ec..20fc65dd7d6 100644 --- a/sys/arch/pica/include/pte.h +++ b/sys/arch/pica/include/pte.h @@ -1,3 +1,5 @@ +/* $OpenBSD: pte.h,v 1.3 1996/06/06 23:07:04 deraadt Exp $ */ + /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -35,10 +37,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: pte.h 1.11 89/09/03 - * + * from: Utah Hdr: pte.h 1.11 89/09/03 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 - * $Id: pte.h,v 1.2 1996/05/02 07:59:40 pefo Exp $ */ /* diff --git a/sys/arch/pica/include/ptrace.h b/sys/arch/pica/include/ptrace.h index 3605d68866f..3d780346db3 100644 --- a/sys/arch/pica/include/ptrace.h +++ b/sys/arch/pica/include/ptrace.h @@ -1,3 +1,5 @@ +/* $OpenBSD: ptrace.h,v 1.3 1996/06/06 23:07:06 deraadt Exp $ */ + /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -31,7 +33,6 @@ * SUCH DAMAGE. * * from: @(#)ptrace.h 8.1 (Berkeley) 6/10/93 - * $Id: ptrace.h,v 1.2 1996/05/01 18:23:50 pefo Exp $ */ /* diff --git a/sys/arch/pica/include/reg.h b/sys/arch/pica/include/reg.h index f91820dc359..3f8361d5940 100644 --- a/sys/arch/pica/include/reg.h +++ b/sys/arch/pica/include/reg.h @@ -1,3 +1,4 @@ +/* $OpenBSD: reg.h,v 1.3 1996/06/06 23:07:07 deraadt Exp $ */ /* $NetBSD: reg.h,v 1.6 1995/12/20 02:00:27 jonathan Exp $ */ /* @@ -37,8 +38,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: reg.h 1.1 90/07/09 - * + * from: Utah Hdr: reg.h 1.1 90/07/09 * @(#)reg.h 8.2 (Berkeley) 1/11/94 */ diff --git a/sys/arch/pica/include/regdef.h b/sys/arch/pica/include/regdef.h index 46216b57d00..b30530af7e2 100644 --- a/sys/arch/pica/include/regdef.h +++ b/sys/arch/pica/include/regdef.h @@ -1,3 +1,4 @@ +/* $OpenBSD: regdef.h,v 1.2 1996/06/06 23:07:09 deraadt Exp $ */ /* $NetBSD: regdef.h,v 1.4 1994/10/26 21:09:58 cgd Exp $ */ /* diff --git a/sys/arch/pica/include/regnum.h b/sys/arch/pica/include/regnum.h index 506646d3b22..903d63d4f6c 100644 --- a/sys/arch/pica/include/regnum.h +++ b/sys/arch/pica/include/regnum.h @@ -1,3 +1,4 @@ +/* $OpenBSD: regnum.h,v 1.2 1996/06/06 23:07:10 deraadt Exp $ */ /* $NetBSD: reg.h,v 1.5 1995/01/18 06:40:12 mellon Exp $ */ /* @@ -37,8 +38,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: reg.h 1.1 90/07/09 - * + * from: Utah Hdr: reg.h 1.1 90/07/09 * @(#)reg.h 8.2 (Berkeley) 1/11/94 */ diff --git a/sys/arch/pica/include/reloc.h b/sys/arch/pica/include/reloc.h index 4c5c5cd3ceb..df72d1580fc 100644 --- a/sys/arch/pica/include/reloc.h +++ b/sys/arch/pica/include/reloc.h @@ -1,3 +1,5 @@ +/* $OpenBSD: reloc.h,v 1.3 1996/06/06 23:07:12 deraadt Exp $ */ + /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -31,9 +33,7 @@ * SUCH DAMAGE. * * from: @(#)reloc.h 8.1 (Berkeley) 6/10/93 - * $Id: reloc.h,v 1.2 1996/05/01 18:23:53 pefo Exp $ - * - * from: Header: reloc.h,v 1.6 92/06/20 09:59:37 torek Exp + * from: Header: reloc.h,v 1.6 92/06/20 09:59:37 torek Exp */ #if 0 diff --git a/sys/arch/pica/include/setjmp.h b/sys/arch/pica/include/setjmp.h index c50d15c79b5..c8dc96433a8 100644 --- a/sys/arch/pica/include/setjmp.h +++ b/sys/arch/pica/include/setjmp.h @@ -1,3 +1,4 @@ +/* $OpenBSD: setjmp.h,v 1.2 1996/06/06 23:07:13 deraadt Exp $ */ /* $NetBSD: setjmp.h,v 1.1 1994/12/20 10:37:05 cgd Exp $ */ /* diff --git a/sys/arch/pica/include/signal.h b/sys/arch/pica/include/signal.h index 9fa32788dc5..3b878ef68e0 100644 --- a/sys/arch/pica/include/signal.h +++ b/sys/arch/pica/include/signal.h @@ -1,3 +1,4 @@ +/* $OpenBSD: signal.h,v 1.2 1996/06/06 23:07:15 deraadt Exp $ */ /* $NetBSD: signal.h,v 1.6 1995/01/18 06:42:01 mellon Exp $ */ /* diff --git a/sys/arch/pica/include/stdarg.h b/sys/arch/pica/include/stdarg.h index 73f3b6e0a1a..14a640553f0 100644 --- a/sys/arch/pica/include/stdarg.h +++ b/sys/arch/pica/include/stdarg.h @@ -1,3 +1,4 @@ +/* $OpenBSD: stdarg.h,v 1.2 1996/06/06 23:07:16 deraadt Exp $ */ /* $NetBSD: stdarg.h,v 1.7 1995/03/28 18:19:28 jtc Exp $ */ /*- diff --git a/sys/arch/pica/include/trap.h b/sys/arch/pica/include/trap.h index 2b977477b88..5513663f8f9 100644 --- a/sys/arch/pica/include/trap.h +++ b/sys/arch/pica/include/trap.h @@ -1,3 +1,5 @@ +/* $OpenBSD: trap.h,v 1.2 1996/06/06 23:07:18 deraadt Exp $ */ + /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -35,10 +37,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: trap.h 1.1 90/07/09 - * + * from: Utah Hdr: trap.h 1.1 90/07/09 * from: @(#)trap.h 8.1 (Berkeley) 6/10/93 - * $Id: trap.h,v 1.1 1995/10/18 10:39:15 deraadt Exp $ */ /* diff --git a/sys/arch/pica/include/types.h b/sys/arch/pica/include/types.h index 74135094d9b..543afe4c733 100644 --- a/sys/arch/pica/include/types.h +++ b/sys/arch/pica/include/types.h @@ -1,3 +1,4 @@ +/* $OpenBSD: types.h,v 1.4 1996/06/06 23:07:19 deraadt Exp $ */ /* $NetBSD: types.h,v 1.10 1995/07/06 03:39:43 cgd Exp $ */ /*- diff --git a/sys/arch/pica/include/varargs.h b/sys/arch/pica/include/varargs.h index 8cb900dc521..4d6cc865be1 100644 --- a/sys/arch/pica/include/varargs.h +++ b/sys/arch/pica/include/varargs.h @@ -1,3 +1,4 @@ +/* $OpenBSD: varargs.h,v 1.3 1996/06/06 23:07:21 deraadt Exp $ */ /* $NetBSD: varargs.h,v 1.8 1995/03/28 18:19:30 jtc Exp $ */ /*- diff --git a/sys/arch/pica/include/vmparam.h b/sys/arch/pica/include/vmparam.h index a8b159f6ddf..9a7b5170f5b 100644 --- a/sys/arch/pica/include/vmparam.h +++ b/sys/arch/pica/include/vmparam.h @@ -1,3 +1,4 @@ +/* $OpenBSD: vmparam.h,v 1.3 1996/06/06 23:07:23 deraadt Exp $ */ /* $NetBSD: vmparam.h,v 1.5 1994/10/26 21:10:10 cgd Exp $ */ /* @@ -37,8 +38,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: Utah Hdr: vmparam.h 1.16 91/01/18 - * + * from: Utah Hdr: vmparam.h 1.16 91/01/18 * @(#)vmparam.h 8.2 (Berkeley) 4/22/94 */ diff --git a/sys/arch/pica/pica/clock.c b/sys/arch/pica/pica/clock.c index b648306ed62..0ce8e648779 100644 --- a/sys/arch/pica/pica/clock.c +++ b/sys/arch/pica/pica/clock.c @@ -38,7 +38,7 @@ * from: Utah Hdr: clock.c 1.18 91/01/21 * * from: @(#)clock.c 8.1 (Berkeley) 6/10/93 - * $Id: clock.c,v 1.4 1996/05/15 07:09:10 pefo Exp $ + * $Id: clock.c,v 1.5 1996/06/06 23:07:28 deraadt Exp $ */ #include <sys/param.h> @@ -47,7 +47,7 @@ #include <sys/device.h> #include <machine/autoconf.h> -#include <machine/machConst.h> +#include <machine/cpu.h> #include <pica/pica/clockvar.h> #include <pica/pica/picatype.h> diff --git a/sys/arch/pica/pica/exec_elf.c b/sys/arch/pica/pica/exec_elf.c deleted file mode 100644 index a934ab322ac..00000000000 --- a/sys/arch/pica/pica/exec_elf.c +++ /dev/null @@ -1,630 +0,0 @@ -/* $NetBSD: exec_elf.c,v 1.3 1995/09/16 00:28:08 thorpej Exp $ */ - -/* - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/proc.h> -#include <sys/malloc.h> -#include <sys/namei.h> -#include <sys/vnode.h> -#include <sys/exec.h> -#include <sys/exec_elf.h> -#include <sys/syscall.h> -#include <sys/signalvar.h> - -#include <sys/mman.h> -#include <vm/vm.h> -#include <vm/vm_param.h> -#include <vm/vm_map.h> - -#include <machine/cpu.h> -#include <machine/reg.h> -#include <machine/exec.h> - -#ifdef COMPAT_LINUX -#include <compat/linux/linux_exec.h> -#endif - -#ifdef COMPAT_SVR4 -#include <compat/svr4/svr4_exec.h> -#endif - -int (*elf_probe_funcs[])() = { -#ifdef COMPAT_SVR4 - svr4_elf_probe, -#endif -#ifdef COMPAT_LINUX - linux_elf_probe -#endif -}; - -static int elf_set_segment __P((struct exec_package *, u_long, u_long, - int)); -static int elf_read_from __P((struct proc *, struct vnode *, u_long, - caddr_t, int)); -static void elf_load_psection __P((struct exec_vmcmd_set *, - struct vnode *, Elf32_Phdr *, u_long *, u_long *, int *)); - -#define ELF_ALIGN(a, b) ((a) & ~((b) - 1)) - -/* - * This is the basic elf emul. - */ - -extern char sigcode[], esigcode[]; -#ifdef SYSCALL_DEBUG -extern char *syscallnames[]; -#endif - -struct emul emul_elf = { - "netbsd", - NULL, - sendsig, - SYS_syscall, - SYS_MAXSYSCALL, - sysent, -#ifdef SYSCALL_DEBUG - syscallnames, -#else - NULL, -#endif - sizeof(AuxInfo) * 8, - elf_copyargs, - setregs, - sigcode, - esigcode, -}; - -/* - * Copy arguments onto the stack in the normal way, but add some - * extra information in case of dynamic binding. - */ -void * -elf_copyargs(pack, arginfo, stack, argp) - struct exec_package *pack; - struct ps_strings *arginfo; - void *stack; - void *argp; -{ - char **cpp = stack; - char *dp, *sp; - size_t len; - void *nullp = NULL; - int argc = arginfo->ps_nargvstr; - int envc = arginfo->ps_nenvstr; - AuxInfo *a; - struct elf_args *ap; - - if (copyout(&argc, cpp++, sizeof(argc))) - return NULL; - - dp = (char *) (cpp + argc + envc + 2 + pack->ep_emul->e_arglen); - sp = argp; - - /* XXX don't copy them out, remap them! */ - arginfo->ps_argvstr = cpp; /* remember location of argv for later */ - - for (; --argc >= 0; sp += len, dp += len) - if (copyout(&dp, cpp++, sizeof(dp)) || - copyoutstr(sp, dp, ARG_MAX, &len)) - return NULL; - - if (copyout(&nullp, cpp++, sizeof(nullp))) - return NULL; - - arginfo->ps_envstr = cpp; /* remember location of envp for later */ - - for (; --envc >= 0; sp += len, dp += len) - if (copyout(&dp, cpp++, sizeof(dp)) || - copyoutstr(sp, dp, ARG_MAX, &len)) - return NULL; - - if (copyout(&nullp, cpp++, sizeof(nullp))) - return NULL; - - /* - * Push extra arguments on the stack needed by dynamically - * linked binaries - */ - a = (AuxInfo *) cpp; - if ((ap = (struct elf_args *) pack->ep_emul_arg)) { - - a->au_id = AUX_phdr; - a->au_v = ap->arg_phaddr; - a++; - - a->au_id = AUX_phent; - a->au_v = ap->arg_phentsize; - a++; - - a->au_id = AUX_phnum; - a->au_v = ap->arg_phnum; - a++; - - a->au_id = AUX_pagesz; - a->au_v = NBPG; - a++; - - a->au_id = AUX_base; - a->au_v = ap->arg_interp; - a++; - - a->au_id = AUX_flags; - a->au_v = 0; - a++; - - a->au_id = AUX_entry; - a->au_v = ap->arg_entry; - a++; - - a->au_id = AUX_null; - a->au_v = 0; - a++; - - free((char *) ap, M_TEMP); - } - return a; -} - -/* - * elf_check_header(): - * - * Check header for validity; return 0 of ok ENOEXEC if error - * - * XXX machine type needs to be moved to <machine/param.h> so - * just one comparison can be done. Unfortunately, there is both - * em_486 and em_386, so this would not work on the i386. - */ -int -elf_check_header(eh, type) - Elf32_Ehdr *eh; - int type; -{ - - if (bcmp(eh->e_ident, Elf32_e_ident, Elf32_e_siz) != 0) - return ENOEXEC; - - switch (eh->e_machine) { - /* XXX */ -#ifdef i386 - case Elf32_em_386: - case Elf32_em_486: -#endif -#ifdef sparc - case Elf32_em_sparc: -#endif -#ifdef mips - case Elf32_em_mips: -#endif - break; - - default: - return ENOEXEC; - } - - if (eh->e_type != type) - return ENOEXEC; - - return 0; -} - -/* - * elf_load_psection(): - * - * Load a psection at the appropriate address - */ -static void -elf_load_psection(vcset, vp, ph, addr, size, prot) - struct exec_vmcmd_set *vcset; - struct vnode *vp; - Elf32_Phdr *ph; - u_long *addr; - u_long *size; - int *prot; -{ - u_long uaddr, msize, psize, rm, rf; - long diff, offset; - - /* - * If the user specified an address, then we load there. - */ - if (*addr != ELF32_NO_ADDR) { - if (ph->p_align > 1) { - *addr = ELF_ALIGN(*addr + ph->p_align, ph->p_align); - uaddr = ELF_ALIGN(ph->p_vaddr, ph->p_align); - } else - uaddr = ph->p_vaddr; - diff = ph->p_vaddr - uaddr; - } else { - *addr = uaddr = ph->p_vaddr; - if (ph->p_align > 1) - *addr = ELF_ALIGN(uaddr, ph->p_align); - diff = uaddr - *addr; - } - - *prot |= (ph->p_flags & Elf32_pf_r) ? VM_PROT_READ : 0; - *prot |= (ph->p_flags & Elf32_pf_w) ? VM_PROT_WRITE : 0; - *prot |= (ph->p_flags & Elf32_pf_x) ? VM_PROT_EXECUTE : 0; - - offset = ph->p_offset - diff; - *size = ph->p_filesz + diff; - msize = ph->p_memsz + diff; - psize = round_page(*size); - - if(ph->p_flags & Elf32_pf_w) { - psize = trunc_page(*size); - NEW_VMCMD(vcset, vmcmd_map_pagedvn, psize, *addr, vp, offset, *prot); - if(psize != *size) { - NEW_VMCMD(vcset, vmcmd_map_readvn, *size - psize, *addr + psize, vp, offset + psize, *prot); - } - } - else { - NEW_VMCMD(vcset, vmcmd_map_pagedvn, psize, *addr, vp, offset, *prot); - } - - /* - * Check if we need to extend the size of the segment - */ - rm = round_page(*addr + msize); - rf = round_page(*addr + *size); - - if (rm != rf) { - NEW_VMCMD(vcset, vmcmd_map_zero, rm - rf, rf, NULLVP, 0, *prot); - *size = msize; - } -} - -/* - * elf_set_segment(): - * - * Decide if the segment is text or data, depending on the protection - * and set it appropriately - */ -static int -elf_set_segment(epp, vaddr, size, prot) - struct exec_package *epp; - u_long vaddr; - u_long size; - int prot; -{ - /* - * Kludge: Unfortunately the current implementation of - * exec package assumes a single text and data segment. - * In Elf we can have more, but here we limit ourselves - * to two and hope :-( - * We also assume that the text is r-x, and data is rwx or rw-. - */ - switch (prot) { - case (VM_PROT_READ | VM_PROT_EXECUTE): - if (epp->ep_tsize != ELF32_NO_ADDR) - return ENOEXEC; - epp->ep_taddr = vaddr; - epp->ep_tsize = size; - break; - - case (VM_PROT_READ | VM_PROT_WRITE): - case (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE): - if (epp->ep_dsize != ELF32_NO_ADDR) - return ENOEXEC; - epp->ep_daddr = vaddr; - epp->ep_dsize = size; - break; - - default: - return ENOEXEC; - } - return 0; -} - -/* - * elf_read_from(): - * - * Read from vnode into buffer at offset. - */ -static int -elf_read_from(p, vp, off, buf, size) - struct vnode *vp; - u_long off; - struct proc *p; - caddr_t buf; - int size; -{ - int error; - int resid; - - if ((error = vn_rdwr(UIO_READ, vp, buf, size, - off, UIO_SYSSPACE, IO_NODELOCKED, p->p_ucred, - &resid, p)) != 0) - return error; - /* - * See if we got all of it - */ - if (resid != 0) - return error; - return 0; -} - -/* - * elf_load_file(): - * - * Load a file (interpreter/library) pointed to by path - * [stolen from coff_load_shlib()]. Made slightly generic - * so it might be used externally. - */ -int -elf_load_file(p, path, vcset, entry, ap, last) - struct proc *p; - char *path; - struct exec_vmcmd_set *vcset; - u_long *entry; - struct elf_args *ap; - u_long *last; -{ - int error, i; - struct nameidata nd; - Elf32_Ehdr eh; - Elf32_Phdr *ph = NULL; - u_long phsize; - char *bp = NULL; - u_long addr = *last; - - bp = path; - /* - * 1. open file - * 2. read filehdr - * 3. map text, data, and bss out of it using VM_* - */ - NDINIT(&nd, LOOKUP, FOLLOW, UIO_SYSSPACE, path, p); - if ((error = namei(&nd)) != 0) { - return error; - } - if ((error = elf_read_from(p, nd.ni_vp, 0, (caddr_t) &eh, - sizeof(eh))) != 0) - goto bad; - - if ((error = elf_check_header(&eh, Elf32_et_dyn)) != 0) - goto bad; - - phsize = eh.e_phnum * sizeof(Elf32_Phdr); - ph = (Elf32_Phdr *) malloc(phsize, M_TEMP, M_WAITOK); - - if ((error = elf_read_from(p, nd.ni_vp, eh.e_phoff, - (caddr_t) ph, phsize)) != 0) - goto bad; - - /* - * Load all the necessary sections - */ - for (i = 0; i < eh.e_phnum; i++) { - u_long size = 0; - int prot = 0; - - switch (ph[i].p_type) { - case Elf32_pt_load: - elf_load_psection(vcset, nd.ni_vp, &ph[i], &addr, - &size, &prot); - /* Assume that the text segment is r-x only */ - if ((prot & PROT_WRITE) == 0) { - *entry = addr + eh.e_entry - ph[i].p_vaddr; - ap->arg_interp = addr; - } - addr += size; - break; - - case Elf32_pt_dynamic: - case Elf32_pt_phdr: - case Elf32_pt_note: - break; - - default: - break; - } - } - -bad: - if (ph != NULL) - free((char *) ph, M_TEMP); - - *last = addr; - vrele(nd.ni_vp); - return error; -} - -/* - * exec_elf_makecmds(): Prepare an Elf binary's exec package - * - * First, set of the various offsets/lengths in the exec package. - * - * Then, mark the text image busy (so it can be demand paged) or error - * out if this is not possible. Finally, set up vmcmds for the - * text, data, bss, and stack segments. - * - */ -int -exec_elf_makecmds(p, epp) - struct proc *p; - struct exec_package *epp; -{ - Elf32_Ehdr *eh = epp->ep_hdr; - Elf32_Phdr *ph, *pp; - int error, i, n; - char interp[MAXPATHLEN]; - u_long pos = 0, phsize; - - if (epp->ep_hdrvalid < sizeof(Elf32_Ehdr)) - return ENOEXEC; - - if (elf_check_header(eh, Elf32_et_exec)) - return ENOEXEC; - - /* - * check if vnode is in open for writing, because we want to - * demand-page out of it. if it is, don't do it, for various - * reasons - */ - if (epp->ep_vp->v_writecount != 0) { -#ifdef DIAGNOSTIC - if (epp->ep_vp->v_flag & VTEXT) - panic("exec: a VTEXT vnode has writecount != 0\n"); -#endif - return ETXTBSY; - } - /* - * Allocate space to hold all the program headers, and read them - * from the file - */ - phsize = eh->e_phnum * sizeof(Elf32_Phdr); - ph = (Elf32_Phdr *) malloc(phsize, M_TEMP, M_WAITOK); - - if ((error = elf_read_from(p, epp->ep_vp, eh->e_phoff, - (caddr_t) ph, phsize)) != 0) - goto bad; - - epp->ep_tsize = ELF32_NO_ADDR; - epp->ep_dsize = ELF32_NO_ADDR; - - interp[0] = '\0'; - - for (i = 0; i < eh->e_phnum; i++) { - pp = &ph[i]; - if (pp->p_type == Elf32_pt_interp) { - if (pp->p_filesz >= sizeof(interp)) - goto bad; - if ((error = elf_read_from(p, epp->ep_vp, pp->p_offset, - (caddr_t) interp, pp->p_filesz)) != 0) - goto bad; - break; - } - } - - /* - * OK, we want a slightly different twist of the - * standard emulation package for "real" elf. - */ - epp->ep_emul = &emul_elf; - pos = ELF32_NO_ADDR; - - /* - * On the same architecture, we may be emulating different systems. - * See which one will accept this executable. This currently only - * applies to Linux and SVR4 on the i386. - * - * Probe functions would normally see if the interpreter (if any) - * exists. Emulation packages may possibly replace the interpreter in - * interp[] with a changed path (/emul/xxx/<path>), and also - * set the ep_emul field in the exec package structure. - */ - if ((n = sizeof elf_probe_funcs / sizeof elf_probe_funcs[0])) { - error = ENOEXEC; - for (i = 0; i < n && error; i++) - error = elf_probe_funcs[i](p, epp, interp, &pos); - - if (error) - goto bad; - } - - /* - * Load all the necessary sections - */ - for (i = 0; i < eh->e_phnum; i++) { - u_long addr = ELF32_NO_ADDR, size = 0; - int prot = 0; - - pp = &ph[i]; - - switch (ph[i].p_type) { - case Elf32_pt_load: - elf_load_psection(&epp->ep_vmcmds, epp->ep_vp, - &ph[i], &addr, &size, &prot); - if ((error = elf_set_segment(epp, addr, size, - prot)) != 0) - goto bad; - break; - - case Elf32_pt_shlib: - error = ENOEXEC; - goto bad; - - case Elf32_pt_interp: - /* Already did this one */ - case Elf32_pt_dynamic: - case Elf32_pt_phdr: - case Elf32_pt_note: - break; - - default: - /* - * Not fatal, we don't need to understand everything - * :-) - */ - break; - } - } - - /* - * Check if we found a dynamically linked binary and arrange to load - * it's interpreter - */ - if (interp[0]) { - struct elf_args *ap; - - ap = (struct elf_args *) malloc(sizeof(struct elf_args), - M_TEMP, M_WAITOK); - if ((error = elf_load_file(p, interp, &epp->ep_vmcmds, - &epp->ep_entry, ap, &pos)) != 0) { - free((char *) ap, M_TEMP); - goto bad; - } - /* Arrange to load the program headers. */ - pos = ELF_ALIGN(pos + NBPG, NBPG); - ap->arg_phaddr = pos; - NEW_VMCMD(&epp->ep_vmcmds, vmcmd_map_readvn, phsize, - pos, epp->ep_vp, eh->e_phoff, - VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE); - pos += phsize; - - ap->arg_phentsize = eh->e_phentsize; - ap->arg_phnum = eh->e_phnum; - ap->arg_entry = eh->e_entry; - - epp->ep_emul_arg = ap; - } else - epp->ep_entry = eh->e_entry; - - free((char *) ph, M_TEMP); - epp->ep_vp->v_flag |= VTEXT; - return exec_aout_setup_stack(p, epp); - -bad: - free((char *) ph, M_TEMP); - kill_vmcmds(&epp->ep_vmcmds); - return ENOEXEC; -} diff --git a/sys/arch/pica/pica/fp.S b/sys/arch/pica/pica/fp.S index 192aa44d4e2..cf51cec0fab 100644 --- a/sys/arch/pica/pica/fp.S +++ b/sys/arch/pica/pica/fp.S @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * from: @(#)fp.s 8.1 (Berkeley) 6/10/93 - * $Id: fp.S,v 1.1 1995/10/18 10:39:18 deraadt Exp $ + * $Id: fp.S,v 1.2 1996/06/06 23:07:32 deraadt Exp $ */ /* @@ -42,8 +42,8 @@ */ #include <machine/regdef.h> -#include <machine/machAsmDefs.h> -#include <machine/machConst.h> +#include <machine/asm.h> +#include <machine/cpu.h> #include "assym.h" @@ -109,10 +109,10 @@ NON_LEAF(MachEmulateFP, STAND_FRAME_SIZE, ra) bgt v0, 4 << 2, ill # illegal format or v1, v1, v0 - cfc1 a1, MACH_FPC_CSR # get exception register + cfc1 a1, FPC_CSR # get exception register lw a3, func_fmt_tbl(v1) # switch on FUNC & FMT - and a1, a1, ~MACH_FPC_EXCEPTION_UNIMPL # clear exception - ctc1 a1, MACH_FPC_CSR + and a1, a1, ~FPC_EXCEPTION_UNIMPL # clear exception + ctc1 a1, FPC_CSR j a3 .rdata @@ -667,8 +667,8 @@ add_sub_s: 3: bne t5, zero, result_ft_s # if FT != 0, result=FT bne t6, zero, result_ft_s - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + bne v0, FPC_ROUND_RM, 1f # round to -infinity? or t0, t0, t4 # compute result sign b result_fs_s 1: @@ -726,8 +726,8 @@ add_sub_s: bne t2, t6, 2f # if same, result=0 move t1, zero # result=0 move t2, zero - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + bne v0, FPC_ROUND_RM, 1f # round to -infinity? or t0, t0, t4 # compute result sign b result_fs_s 1: @@ -790,8 +790,8 @@ add_sub_d: bne t5, zero, result_ft_d # if FT != 0, result=FT bne t6, zero, result_ft_d bne t7, zero, result_ft_d - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + bne v0, FPC_ROUND_RM, 1f # round to -infinity? or t0, t0, t4 # compute result sign b result_fs_d 1: @@ -884,8 +884,8 @@ add_sub_d: move t1, zero # result=0 move t2, zero move t3, zero - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + bne v0, FPC_ROUND_RM, 1f # round to -infinity? or t0, t0, t4 # compute result sign b result_fs_d 1: @@ -1080,10 +1080,10 @@ div_s: 3: bne t5, zero, 2f # is FT zero? bne t6, zero, 1f - or a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0 - and v0, a1, MACH_FPC_ENABLE_DIV0 # trap enabled? + or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 + and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions li t1, SEXP_INF # result is infinity move t2, zero b result_fs_s @@ -1154,10 +1154,10 @@ div_d: bne t5, zero, 2f # is FT zero? bne t6, zero, 1f bne t7, zero, 1f - or a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0 - and v0, a1, MACH_FPC_ENABLE_DIV0 # trap enabled? + or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 + and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # Save exceptions + ctc1 a1, FPC_CSR # Save exceptions li t1, DEXP_INF # result is infinity move t2, zero move t3, zero @@ -1506,10 +1506,10 @@ cvt_w: * round result (t0 is sign, t2 is integer part, t3 is fractional part). */ 2: - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1538,10 +1538,10 @@ cvt_w: * Handle inexact exception. */ inexact_w: - or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT - and v0, a1, MACH_FPC_ENABLE_INEXACT + or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions b result_fs_w /* @@ -1550,10 +1550,10 @@ inexact_w: * or generate an invalid exception. */ overflow_w: - or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW - and v0, a1, MACH_FPC_ENABLE_OVERFLOW + or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW + and v0, a1, FPC_ENABLE_OVERFLOW bne v0, zero, fpe_trap - and v0, a1, MACH_FPC_ENABLE_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, inexact_w # inexact traps enabled? b invalid_w @@ -1563,10 +1563,10 @@ overflow_w: * or generate an invalid exception. */ underflow_w: - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW - and v0, a1, MACH_FPC_ENABLE_UNDERFLOW + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + and v0, a1, FPC_ENABLE_UNDERFLOW bne v0, zero, fpe_trap - and v0, a1, MACH_FPC_ENABLE_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, inexact_w # inexact traps enabled? b invalid_w @@ -1642,29 +1642,29 @@ test_cond: and v0, v0, a0 # condition match instruction? set_cond: bne v0, zero, 1f - and a1, a1, ~MACH_FPC_COND_BIT # clear condition bit + and a1, a1, ~FPC_COND_BIT # clear condition bit b 2f 1: - or a1, a1, MACH_FPC_COND_BIT # set condition bit + or a1, a1, FPC_COND_BIT # set condition bit 2: - ctc1 a1, MACH_FPC_CSR # save condition bit + ctc1 a1, FPC_CSR # save condition bit b done unordered: and v0, a0, COND_UNORDERED # this cmp match unordered? bne v0, zero, 1f - and a1, a1, ~MACH_FPC_COND_BIT # clear condition bit + and a1, a1, ~FPC_COND_BIT # clear condition bit b 2f 1: - or a1, a1, MACH_FPC_COND_BIT # set condition bit + or a1, a1, FPC_COND_BIT # set condition bit 2: and v0, a0, COND_SIGNAL beq v0, zero, 1f # is this a signaling cmp? - or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID - and v0, a1, MACH_FPC_ENABLE_INVALID + or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID + and v0, a1, FPC_ENABLE_INVALID bne v0, zero, fpe_trap 1: - ctc1 a1, MACH_FPC_CSR # save condition bit + ctc1 a1, FPC_CSR # save condition bit b done /* @@ -1729,10 +1729,10 @@ norm_s: norm_noshift_s: move t5, t1 # save unrounded exponent move t6, t2 # save unrounded fraction - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1772,10 +1772,10 @@ inexact_s: and t2, t2, ~SIMPL_ONE # clear implied one bit inexact_nobias_s: jal set_fd_s # save result - or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT - and v0, a1, MACH_FPC_ENABLE_INEXACT + or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions b done /* @@ -1784,18 +1784,18 @@ inexact_nobias_s: * or generate an infinity. */ overflow_s: - or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW - and v0, a1, MACH_FPC_ENABLE_OVERFLOW + or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW + and v0, a1, FPC_ENABLE_OVERFLOW beq v0, zero, 1f subu t1, t1, 192 # bias exponent and t2, t2, ~SIMPL_ONE # clear implied one bit jal set_fd_s # save result b fpe_trap 1: - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 1f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 2f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 2f # round to +infinity bne t0, zero, 3f 1: li t1, SEXP_MAX # result is max finite @@ -1813,7 +1813,7 @@ overflow_s: * "loss of accuracy" is detected as "an inexact result". */ underflow_s: - and v0, a1, MACH_FPC_ENABLE_UNDERFLOW + and v0, a1, FPC_ENABLE_UNDERFLOW beq v0, zero, 1f /* * Underflow is enabled so compute the result and trap. @@ -1821,7 +1821,7 @@ underflow_s: addu t1, t1, 192 # bias exponent and t2, t2, ~SIMPL_ONE # clear implied one bit jal set_fd_s # save result - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW b fpe_trap /* * Underflow is not enabled so compute the result, @@ -1835,15 +1835,15 @@ underflow_s: blt t9, SFRAC_BITS+2, 3f # shift all the bits out? move t1, zero # result is inexact zero move t2, zero - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW /* * Now round the zero result. * Only need to worry about rounding to +- infinity when the sign matches. */ - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, inexact_nobias_s # round to nearest - beq v0, MACH_FPC_ROUND_RZ, inexact_nobias_s # round to zero - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, inexact_nobias_s # round to nearest + beq v0, FPC_ROUND_RZ, inexact_nobias_s # round to zero + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, inexact_nobias_s # if sign is positive, truncate b 2f 1: @@ -1861,10 +1861,10 @@ underflow_s: /* * Now round the denormalized result. */ - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1886,11 +1886,11 @@ underflow_s: move t1, zero # denorm or zero exponent jal set_fd_s # save result beq t8, zero, done # check for exact result - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW - or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT - and v0, a1, MACH_FPC_ENABLE_INEXACT + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions b done /* @@ -1975,10 +1975,10 @@ norm_noshift_d: move t5, t1 # save unrounded exponent move t6, t2 # save unrounded fraction (MS) move t7, t3 # save unrounded fraction (LS) - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -2022,10 +2022,10 @@ inexact_d: and t2, t2, ~DIMPL_ONE # clear implied one bit inexact_nobias_d: jal set_fd_d # save result - or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT - and v0, a1, MACH_FPC_ENABLE_INEXACT + or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions b done /* @@ -2034,18 +2034,18 @@ inexact_nobias_d: * or generate an infinity. */ overflow_d: - or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW - and v0, a1, MACH_FPC_ENABLE_OVERFLOW + or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW + and v0, a1, FPC_ENABLE_OVERFLOW beq v0, zero, 1f subu t1, t1, 1536 # bias exponent and t2, t2, ~DIMPL_ONE # clear implied one bit jal set_fd_d # save result b fpe_trap 1: - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 1f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 2f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 2f # round to +infinity bne t0, zero, 3f 1: li t1, DEXP_MAX # result is max finite @@ -2065,7 +2065,7 @@ overflow_d: * "loss of accuracy" is detected as "an inexact result". */ underflow_d: - and v0, a1, MACH_FPC_ENABLE_UNDERFLOW + and v0, a1, FPC_ENABLE_UNDERFLOW beq v0, zero, 1f /* * Underflow is enabled so compute the result and trap. @@ -2073,7 +2073,7 @@ underflow_d: addu t1, t1, 1536 # bias exponent and t2, t2, ~DIMPL_ONE # clear implied one bit jal set_fd_d # save result - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW b fpe_trap /* * Underflow is not enabled so compute the result, @@ -2089,15 +2089,15 @@ underflow_d: move t1, zero # result is inexact zero move t2, zero move t3, zero - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW /* * Now round the zero result. * Only need to worry about rounding to +- infinity when the sign matches. */ - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, inexact_nobias_d # round to nearest - beq v0, MACH_FPC_ROUND_RZ, inexact_nobias_d # round to zero - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, inexact_nobias_d # round to nearest + beq v0, FPC_ROUND_RZ, inexact_nobias_d # round to zero + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, inexact_nobias_d # if sign is positive, truncate b 2f 1: @@ -2129,10 +2129,10 @@ underflow_d: * Now round the denormalized result. */ 2: - and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode - beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest - beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, FPC_ROUNDING_BITS # get rounding mode + beq v0, FPC_ROUND_RN, 3f # round to nearest + beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) + beq v0, FPC_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -2158,11 +2158,11 @@ underflow_d: move t1, zero # denorm or zero exponent jal set_fd_d # save result beq t8, zero, done # check for exact result - or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW - or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT - and v0, a1, MACH_FPC_ENABLE_INEXACT + or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT + and v0, a1, FPC_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions b done /* @@ -2170,10 +2170,10 @@ underflow_d: * the result is a quiet NAN. */ invalid_s: # trap invalid operation - or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID - and v0, a1, MACH_FPC_ENABLE_INVALID + or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID + and v0, a1, FPC_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions move t0, zero # result is a quiet NAN li t1, SEXP_INF li t2, SQUIET_NAN @@ -2185,10 +2185,10 @@ invalid_s: # trap invalid operation * the result is a quiet NAN. */ invalid_d: # trap invalid operation - or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID - and v0, a1, MACH_FPC_ENABLE_INVALID + or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID + and v0, a1, FPC_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions move t0, zero # result is a quiet NAN li t1, DEXP_INF li t2, DQUIET_NAN0 @@ -2201,10 +2201,10 @@ invalid_d: # trap invalid operation * the result is INT_MAX or INT_MIN. */ invalid_w: # trap invalid operation - or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID - and v0, a1, MACH_FPC_ENABLE_INVALID + or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID + and v0, a1, FPC_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions bne t0, zero, 1f li t2, INT_MAX # result is INT_MAX b result_fs_w @@ -2217,14 +2217,14 @@ invalid_w: # trap invalid operation */ fpe_trap: move a2, a1 # code = FP CSR - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions break 0 /* * Send an illegal instruction signal to the current process. */ ill: - ctc1 a1, MACH_FPC_CSR # save exceptions + ctc1 a1, FPC_CSR # save exceptions move a2, a0 # code = FP instruction break 0 diff --git a/sys/arch/pica/pica/locore.S b/sys/arch/pica/pica/locore.S index 93fef1d5299..d060326c166 100644 --- a/sys/arch/pica/pica/locore.S +++ b/sys/arch/pica/pica/locore.S @@ -49,7 +49,7 @@ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) * * from: @(#)locore.s 8.5 (Berkeley) 1/4/94 - * $Id: locore.S,v 1.4 1996/05/15 08:08:29 pefo Exp $ + * $Id: locore.S,v 1.5 1996/06/06 23:07:35 deraadt Exp $ */ /* @@ -63,6 +63,7 @@ #include <machine/param.h> #include <machine/psl.h> #include <machine/asm.h> +#include <machine/cpu.h> #include <machine/regnum.h> #include <machine/pte.h> @@ -77,8 +78,8 @@ .globl start start: - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts - mtc0 zero, MACH_COP_0_CAUSE_REG # Clear soft interrupts + mtc0 zero, COP_0_STATUS_REG # Disable interrupts + mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts /* * Initialize stack and call machine startup. @@ -89,15 +90,15 @@ start: jal mips_init # mips_init(argc, argv, envp) sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger - li t0, MACH_SR_COP_1_BIT # Disable interrupts and - mtc0 t0, MACH_COP_0_STATUS_REG # enable the fp coprocessor + li t0, SR_COP_1_BIT # Disable interrupts and + mtc0 t0, COP_0_STATUS_REG # enable the fp coprocessor li sp, KERNELSTACK - START_FRAME # switch to standard stack - mfc0 t0, MACH_COP_0_PRID # read processor ID register + mfc0 t0, COP_0_PRID # read processor ID register nop nop # wait for new status to nop # to be effective nop - cfc1 t1, MACH_FPC_ID # read FPU ID register + cfc1 t1, FPC_ID # read FPU ID register sw t0, cpu_id # save PRID register sw t1, fpu_id # save FPU ID register jal main # main(regs) @@ -107,8 +108,8 @@ start: * Restore user registers and return. */ .set noat - li v0, MACH_SR_EXL - mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level bit. + li v0, SR_EXL + mtc0 v0, COP_0_STATUS_REG # set exeption level bit. lw a0, UADDR+U_PCB_REGS+(SR * 4) lw t0, UADDR+U_PCB_REGS+(MULLO * 4) lw t1, UADDR+U_PCB_REGS+(MULHI * 4) @@ -117,9 +118,9 @@ start: lw a0, UADDR+U_PCB_REGS+(PC * 4) lw AT, UADDR+U_PCB_REGS+(AST * 4) lw v0, UADDR+U_PCB_REGS+(V0 * 4) - dmtc0 a0, MACH_COP_0_EXC_PC # set return address + dmtc0 a0, COP_0_EXC_PC # set return address li a0, PSL_USERSET - mtc0 a0, MACH_COP_0_STATUS_REG # switch to user mode + mtc0 a0, COP_0_STATUS_REG # switch to user mode lw v1, UADDR+U_PCB_REGS+(V1 * 4) lw a0, UADDR+U_PCB_REGS+(A0 * 4) lw a1, UADDR+U_PCB_REGS+(A1 * 4) @@ -398,7 +399,7 @@ ALEAF(savectx) sw s1, U_PCB_CONTEXT+4(a0) sw s2, U_PCB_CONTEXT+8(a0) sw s3, U_PCB_CONTEXT+12(a0) - mfc0 v0, MACH_COP_0_STATUS_REG + mfc0 v0, COP_0_STATUS_REG sw s4, U_PCB_CONTEXT+16(a0) sw s5, U_PCB_CONTEXT+20(a0) sw s6, U_PCB_CONTEXT+24(a0) @@ -504,10 +505,10 @@ LEAF(switch_exit) lw t0, P_UPTE+0(v1) # t0 = first u. pte lw t1, P_UPTE+4(v1) # t1 = 2nd u. pte li v0, UADDR # v0 = first HI entry - mtc0 zero, MACH_COP_0_TLB_INDEX # set the index register - dmtc0 v0, MACH_COP_0_TLB_HI # init high entry - dmtc0 t0, MACH_COP_0_TLB_LO0 # init low entry0 - dmtc0 t1, MACH_COP_0_TLB_LO1 # init low entry1 + mtc0 zero, COP_0_TLB_INDEX # set the index register + dmtc0 v0, COP_0_TLB_HI # init high entry + dmtc0 t0, COP_0_TLB_LO0 # init low entry0 + dmtc0 t1, COP_0_TLB_LO1 # init low entry1 nop tlbwi # Write the TLB entry. nop @@ -524,8 +525,8 @@ END(switch_exit) * profiling. */ LEAF(idle) - li t0, (MACH_INT_MASK | MACH_SR_INT_ENAB) - mtc0 t0, MACH_COP_0_STATUS_REG # enable all interrupts + li t0, (INT_MASK | SR_INT_ENAB) + mtc0 t0, COP_0_STATUS_REG # enable all interrupts sw zero, curproc # set curproc NULL for stats 1: lw t0, whichqs # look for non-empty queue @@ -533,7 +534,7 @@ LEAF(idle) beq t0, zero, 1b nop b sw1 - mtc0 zero, MACH_COP_0_STATUS_REG # Disable all interrupts + mtc0 zero, COP_0_STATUS_REG # Disable all interrupts END(idle) /* @@ -551,7 +552,7 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra) sw s1, UADDR+U_PCB_CONTEXT+4 sw s2, UADDR+U_PCB_CONTEXT+8 sw s3, UADDR+U_PCB_CONTEXT+12 - mfc0 t0, MACH_COP_0_STATUS_REG # t0 = saved status register + mfc0 t0, COP_0_STATUS_REG # t0 = saved status register sw s4, UADDR+U_PCB_CONTEXT+16 sw s5, UADDR+U_PCB_CONTEXT+20 sw s6, UADDR+U_PCB_CONTEXT+24 @@ -562,7 +563,7 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra) addu t2, t2, 1 sw t2, cnt+V_SWTCH beq t1, zero, idle # if none, idle - mtc0 zero, MACH_COP_0_STATUS_REG # Disable all interrupts + mtc0 zero, COP_0_STATUS_REG # Disable all interrupts sw1: nop # wait for intrs disabled nop @@ -613,10 +614,10 @@ sw1: * NOTE: This is hard coded to UPAGES == 2. * Also, there should be no TLB faults at this point. */ - mtc0 zero, MACH_COP_0_TLB_INDEX # set the index register - dmtc0 v0, MACH_COP_0_TLB_HI # init high entry - dmtc0 t0, MACH_COP_0_TLB_LO0 # init low entry0 - dmtc0 t1, MACH_COP_0_TLB_LO1 # init low entry1 + mtc0 zero, COP_0_TLB_INDEX # set the index register + dmtc0 v0, COP_0_TLB_HI # init high entry + dmtc0 t0, COP_0_TLB_LO0 # init low entry0 + dmtc0 t1, COP_0_TLB_LO1 # init low entry1 nop tlbwi # Write the TLB entry. nop # Delay for effect @@ -639,7 +640,7 @@ sw1: lw s7, UADDR+U_PCB_CONTEXT+28 lw sp, UADDR+U_PCB_CONTEXT+32 lw s8, UADDR+U_PCB_CONTEXT+36 - mtc0 v0, MACH_COP_0_STATUS_REG + mtc0 v0, COP_0_STATUS_REG j ra li v0, 1 # possible return to 'savectx()' END(cpu_switch) @@ -801,13 +802,13 @@ END(_remque) .globl MachTLBMiss MachTLBMiss: .set noat - dmfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + dmfc0 k0, COP_0_BAD_VADDR # get the virtual address lw k1, UADDR+U_PCB_SEGTAB # get the current segment table bltz k0, 1f # kernel address space -> srl k0, k0, SEGSHIFT - 2 # compute segment table index andi k0, k0, 0x7fc # PMAP_SEGTABSIZ-1 addu k1, k1, k0 - dmfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address + dmfc0 k0, COP_0_BAD_VADDR # get the virtual address lw k1, 0(k1) # get pointer to segment map srl k0, k0, PGSHIFT - 2 # compute segment map index andi k0, k0, ((NPTEPG/2) - 1) << 3 @@ -817,10 +818,10 @@ MachTLBMiss: lw k1, 4(k1) dsll k0, k0, 34 dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO0 + dmtc0 k0, COP_0_TLB_LO0 dsll k1, k1, 34 dsrl k1, k1, 34 - dmtc0 k1, MACH_COP_0_TLB_LO1 + dmtc0 k1, COP_0_TLB_LO1 nop tlbwr # update TLB nop @@ -851,13 +852,13 @@ MachException: * Find out what mode we came from and jump to the proper handler. */ .set noat - mfc0 k0, MACH_COP_0_STATUS_REG # Get the status register - mfc0 k1, MACH_COP_0_CAUSE_REG # Get the cause register value. - and k0, k0, MACH_SR_KSU_USER # test for user mode + mfc0 k0, COP_0_STATUS_REG # Get the status register + mfc0 k1, COP_0_CAUSE_REG # Get the cause register value. + and k0, k0, SR_KSU_USER # test for user mode # sneaky but the bits are # with us........ sll k0, k0, 3 # shift user bit for cause index - and k1, k1, MACH_CR_EXC_CODE # Mask out the cause bits. + and k1, k1, CR_EXC_CODE # Mask out the cause bits. or k1, k1, k0 # change index to user table 1: la k0, machExceptionTable # get base of the jump table @@ -880,9 +881,9 @@ MachExceptionEnd: */ SlowFault: .set noat - mfc0 k0, MACH_COP_0_STATUS_REG + mfc0 k0, COP_0_STATUS_REG nop - and k0, k0, MACH_SR_KSU_USER + and k0, k0, SR_KSU_USER bne k0, zero, MachUserGenException nop .set at @@ -950,25 +951,25 @@ NNON_LEAF(MachKernGenException, KERN_EXC_FRAME_SIZE, ra) sw a2, KERN_REG_OFFSET + 20(sp) sw a3, KERN_REG_OFFSET + 24(sp) sw t0, KERN_REG_OFFSET + 28(sp) - mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + mfc0 a0, COP_0_STATUS_REG # First arg is the status reg. sw t1, KERN_REG_OFFSET + 32(sp) sw t2, KERN_REG_OFFSET + 36(sp) sw t3, KERN_REG_OFFSET + 40(sp) sw t4, KERN_REG_OFFSET + 44(sp) - mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg. sw t5, KERN_REG_OFFSET + 48(sp) sw t6, KERN_REG_OFFSET + 52(sp) sw t7, KERN_REG_OFFSET + 56(sp) sw t8, KERN_REG_OFFSET + 60(sp) - mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr. + mfc0 a2, COP_0_BAD_VADDR # Third arg is the fault addr. sw t9, KERN_REG_OFFSET + 64(sp) sw ra, KERN_REG_OFFSET + 68(sp) sw v0, KERN_MULT_LO_OFFSET(sp) sw v1, KERN_MULT_HI_OFFSET(sp) - mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + mfc0 a3, COP_0_EXC_PC # Fourth arg is the pc. sw a0, KERN_SR_OFFSET(sp) - mtc0 zero,MACH_COP_0_STATUS_REG # Set kernel no error level + mtc0 zero,COP_0_STATUS_REG # Set kernel no error level /* * Call the exception handler. */ @@ -978,14 +979,14 @@ NNON_LEAF(MachKernGenException, KERN_EXC_FRAME_SIZE, ra) * Restore registers and return from the exception. * v0 contains the return address. */ - mtc0 zero,MACH_COP_0_STATUS_REG # Make shure int disabled + mtc0 zero,COP_0_STATUS_REG # Make shure int disabled lw a0, KERN_SR_OFFSET(sp) lw t0, KERN_MULT_LO_OFFSET(sp) lw t1, KERN_MULT_HI_OFFSET(sp) - mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtc0 a0, COP_0_STATUS_REG # Restore the SR, disable intrs mtlo t0 mthi t1 - dmtc0 v0, MACH_COP_0_EXC_PC # set return address + dmtc0 v0, COP_0_EXC_PC # set return address lw AT, KERN_REG_OFFSET + 0(sp) lw v0, KERN_REG_OFFSET + 4(sp) lw v1, KERN_REG_OFFSET + 8(sp) @@ -1043,22 +1044,22 @@ NNON_LEAF(MachUserGenException, STAND_FRAME_SIZE, ra) sw t2, UADDR+U_PCB_REGS+(T2 * 4) sw t3, UADDR+U_PCB_REGS+(T3 * 4) sw t4, UADDR+U_PCB_REGS+(T4 * 4) - mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + mfc0 a0, COP_0_STATUS_REG # First arg is the status reg. sw t5, UADDR+U_PCB_REGS+(T5 * 4) sw t6, UADDR+U_PCB_REGS+(T6 * 4) sw t7, UADDR+U_PCB_REGS+(T7 * 4) sw s0, UADDR+U_PCB_REGS+(S0 * 4) - mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg. sw s1, UADDR+U_PCB_REGS+(S1 * 4) sw s2, UADDR+U_PCB_REGS+(S2 * 4) sw s3, UADDR+U_PCB_REGS+(S3 * 4) sw s4, UADDR+U_PCB_REGS+(S4 * 4) - mfc0 a2, MACH_COP_0_BAD_VADDR # Third arg is the fault addr + mfc0 a2, COP_0_BAD_VADDR # Third arg is the fault addr sw s5, UADDR+U_PCB_REGS+(S5 * 4) sw s6, UADDR+U_PCB_REGS+(S6 * 4) sw s7, UADDR+U_PCB_REGS+(S7 * 4) sw t8, UADDR+U_PCB_REGS+(T8 * 4) - mfc0 a3, MACH_COP_0_EXC_PC # Fourth arg is the pc. + mfc0 a3, COP_0_EXC_PC # Fourth arg is the pc. sw t9, UADDR+U_PCB_REGS+(T9 * 4) sw gp, UADDR+U_PCB_REGS+(GP * 4) sw sp, UADDR+U_PCB_REGS+(SP * 4) @@ -1073,34 +1074,34 @@ NNON_LEAF(MachUserGenException, STAND_FRAME_SIZE, ra) sw a3, STAND_RA_OFFSET(sp) # for debugging .set at # Turn off fpu and enter kernel mode - and t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MACH_SR_KSU_MASK | MACH_SR_INT_ENAB) + and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB) .set noat /* * Call the exception handler. */ jal trap - mtc0 t0, MACH_COP_0_STATUS_REG + mtc0 t0, COP_0_STATUS_REG /* * Restore user registers and return. * First disable interrupts and set exeption level. */ - mtc0 zero, MACH_COP_0_STATUS_REG # disable int + mtc0 zero, COP_0_STATUS_REG # disable int nop nop nop - li v0, MACH_SR_EXL - mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level + li v0, SR_EXL + mtc0 v0, COP_0_STATUS_REG # set exeption level lw a0, UADDR+U_PCB_REGS+(SR * 4) lw t0, UADDR+U_PCB_REGS+(MULLO * 4) lw t1, UADDR+U_PCB_REGS+(MULHI * 4) - mtc0 a0, MACH_COP_0_STATUS_REG # still exeption level + mtc0 a0, COP_0_STATUS_REG # still exeption level mtlo t0 mthi t1 lw a0, UADDR+U_PCB_REGS+(PC * 4) lw AT, UADDR+U_PCB_REGS+(AST * 4) lw v0, UADDR+U_PCB_REGS+(V0 * 4) - dmtc0 a0, MACH_COP_0_EXC_PC # set return address + dmtc0 a0, COP_0_EXC_PC # set return address lw v1, UADDR+U_PCB_REGS+(V1 * 4) lw a0, UADDR+U_PCB_REGS+(A0 * 4) lw a1, UADDR+U_PCB_REGS+(A1 * 4) @@ -1174,24 +1175,24 @@ NNON_LEAF(MachKernIntr, KINTR_FRAME_SIZE, ra) sw a2, KINTR_REG_OFFSET + 20(sp) sw a3, KINTR_REG_OFFSET + 24(sp) sw t0, KINTR_REG_OFFSET + 28(sp) - mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + mfc0 a0, COP_0_STATUS_REG # First arg is the status reg. sw t1, KINTR_REG_OFFSET + 32(sp) sw t2, KINTR_REG_OFFSET + 36(sp) sw t3, KINTR_REG_OFFSET + 40(sp) sw t4, KINTR_REG_OFFSET + 44(sp) - mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg. sw t5, KINTR_REG_OFFSET + 48(sp) sw t6, KINTR_REG_OFFSET + 52(sp) sw t7, KINTR_REG_OFFSET + 56(sp) sw t8, KINTR_REG_OFFSET + 60(sp) - mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + mfc0 a2, COP_0_EXC_PC # Third arg is the pc. sw t9, KINTR_REG_OFFSET + 64(sp) sw ra, KINTR_REG_OFFSET + 68(sp) sw v0, KINTR_MULT_LO_OFFSET(sp) sw v1, KINTR_MULT_HI_OFFSET(sp) sw a0, KINTR_SR_OFFSET(sp) - mtc0 zero, MACH_COP_0_STATUS_REG # Reset exl, trap possible. + mtc0 zero, COP_0_STATUS_REG # Reset exl, trap possible. /* * Call the interrupt handler. */ @@ -1200,17 +1201,17 @@ NNON_LEAF(MachKernIntr, KINTR_FRAME_SIZE, ra) /* * Restore registers and return from the interrupt. */ - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupt + mtc0 zero, COP_0_STATUS_REG # Disable interrupt lw a0, KINTR_SR_OFFSET(sp) lw t0, KINTR_MULT_LO_OFFSET(sp) lw t1, KINTR_MULT_HI_OFFSET(sp) - mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtc0 a0, COP_0_STATUS_REG # Restore the SR, disable intrs mtlo t0 mthi t1 lw a0, STAND_RA_OFFSET(sp) lw AT, KINTR_REG_OFFSET + 0(sp) lw v0, KINTR_REG_OFFSET + 4(sp) - dmtc0 a0, MACH_COP_0_EXC_PC # set return address + dmtc0 a0, COP_0_EXC_PC # set return address lw v1, KINTR_REG_OFFSET + 8(sp) lw a0, KINTR_REG_OFFSET + 12(sp) lw a1, KINTR_REG_OFFSET + 16(sp) @@ -1269,17 +1270,17 @@ NNON_LEAF(MachUserIntr, STAND_FRAME_SIZE, ra) sw a2, UADDR+U_PCB_REGS+(A2 * 4) sw a3, UADDR+U_PCB_REGS+(A3 * 4) sw t0, UADDR+U_PCB_REGS+(T0 * 4) - mfc0 a0, MACH_COP_0_STATUS_REG # First arg is the status reg. + mfc0 a0, COP_0_STATUS_REG # First arg is the status reg. sw t1, UADDR+U_PCB_REGS+(T1 * 4) sw t2, UADDR+U_PCB_REGS+(T2 * 4) sw t3, UADDR+U_PCB_REGS+(T3 * 4) sw t4, UADDR+U_PCB_REGS+(T4 * 4) - mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg. + mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg. sw t5, UADDR+U_PCB_REGS+(T5 * 4) sw t6, UADDR+U_PCB_REGS+(T6 * 4) sw t7, UADDR+U_PCB_REGS+(T7 * 4) sw t8, UADDR+U_PCB_REGS+(T8 * 4) - mfc0 a2, MACH_COP_0_EXC_PC # Third arg is the pc. + mfc0 a2, COP_0_EXC_PC # Third arg is the pc. sw t9, UADDR+U_PCB_REGS+(T9 * 4) sw gp, UADDR+U_PCB_REGS+(GP * 4) sw sp, UADDR+U_PCB_REGS+(SP * 4) @@ -1292,9 +1293,9 @@ NNON_LEAF(MachUserIntr, STAND_FRAME_SIZE, ra) la gp, _gp # switch to kernel GP # Turn off fpu and enter kernel mode .set at - and t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MACH_SR_INT_ENAB | MACH_SR_KSU_MASK) + and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK) .set noat - mtc0 t0, MACH_COP_0_STATUS_REG + mtc0 t0, COP_0_STATUS_REG /* * Call the interrupt handler. */ @@ -1303,23 +1304,23 @@ NNON_LEAF(MachUserIntr, STAND_FRAME_SIZE, ra) /* * Restore registers and return from the interrupt. */ - mtc0 zero, MACH_COP_0_STATUS_REG + mtc0 zero, COP_0_STATUS_REG nop nop nop - li v0, MACH_SR_EXL - mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level bit. + li v0, SR_EXL + mtc0 v0, COP_0_STATUS_REG # set exeption level bit. lw a0, UADDR+U_PCB_REGS+(SR * 4) lw v0, astpending # any pending interrupts? - mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs + mtc0 a0, COP_0_STATUS_REG # Restore the SR, disable intrs bne v0, zero, 1f # dont restore, call softintr lw t0, UADDR+U_PCB_REGS+(MULLO * 4) lw t1, UADDR+U_PCB_REGS+(MULHI * 4) lw a0, UADDR+U_PCB_REGS+(PC * 4) lw AT, UADDR+U_PCB_REGS+(AST * 4) lw v0, UADDR+U_PCB_REGS+(V0 * 4) - dmtc0 a0, MACH_COP_0_EXC_PC # set return address + dmtc0 a0, COP_0_EXC_PC # set return address lw v1, UADDR+U_PCB_REGS+(V1 * 4) lw a0, UADDR+U_PCB_REGS+(A0 * 4) lw a1, UADDR+U_PCB_REGS+(A1 * 4) @@ -1355,32 +1356,32 @@ NNON_LEAF(MachUserIntr, STAND_FRAME_SIZE, ra) sw s6, UADDR+U_PCB_REGS+(S6 * 4) sw s7, UADDR+U_PCB_REGS+(S7 * 4) sw s8, UADDR+U_PCB_REGS+(S8 * 4) - li t0, MACH_HARD_INT_MASK | MACH_SR_INT_ENAB + li t0, HARD_INT_MASK | SR_INT_ENAB /* * Call the software interrupt handler. */ jal softintr - mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts (spl0) + mtc0 t0, COP_0_STATUS_REG # enable interrupts (spl0) /* * Restore user registers and return. NOTE: interrupts are enabled. */ - mtc0 zero, MACH_COP_0_STATUS_REG + mtc0 zero, COP_0_STATUS_REG nop nop nop - li v0, MACH_SR_EXL - mtc0 v0, MACH_COP_0_STATUS_REG # set exeption level bit. + li v0, SR_EXL + mtc0 v0, COP_0_STATUS_REG # set exeption level bit. lw a0, UADDR+U_PCB_REGS+(SR * 4) lw t0, UADDR+U_PCB_REGS+(MULLO * 4) lw t1, UADDR+U_PCB_REGS+(MULHI * 4) - mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts + mtc0 a0, COP_0_STATUS_REG # this should disable interrupts mtlo t0 mthi t1 lw a0, UADDR+U_PCB_REGS+(PC * 4) lw AT, UADDR+U_PCB_REGS+(AST * 4) lw v0, UADDR+U_PCB_REGS+(V0 * 4) - dmtc0 a0, MACH_COP_0_EXC_PC # set return address + dmtc0 a0, COP_0_EXC_PC # set return address lw v1, UADDR+U_PCB_REGS+(V1 * 4) lw a0, UADDR+U_PCB_REGS+(A0 * 4) lw a1, UADDR+U_PCB_REGS+(A1 * 4) @@ -1430,7 +1431,7 @@ END(MachUserIntr) */ NLEAF(MachTLBInvalidException) .set noat - dmfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address + dmfc0 k0, COP_0_BAD_VADDR # get the fault address li k1, VM_MIN_KERNEL_ADDRESS # compute index subu k0, k0, k1 lw k1, Sysmapsize # index within range? @@ -1446,7 +1447,7 @@ NLEAF(MachTLBInvalidException) bne k0, zero, KernTLBIOdd nop - mfc0 k0, MACH_COP_0_TLB_INDEX + mfc0 k0, COP_0_TLB_INDEX nop bltz k0, sys_stk_chk sltiu k0, k0, 8 @@ -1456,13 +1457,13 @@ NLEAF(MachTLBInvalidException) dsll k0, k0, 34 # get rid of "wired" bit dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO0 # load PTE entry + dmtc0 k0, COP_0_TLB_LO0 # load PTE entry and k0, k0, PG_V # check for valid entry beq k0, zero, MachKernGenException # PTE invalid lw k0, 4(k1) # get odd PTE entry dsll k0, k0, 34 dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO1 # load PTE entry + dmtc0 k0, COP_0_TLB_LO1 # load PTE entry nop tlbwi # write TLB nop @@ -1473,7 +1474,7 @@ NLEAF(MachTLBInvalidException) eret KernTLBIOdd: - mfc0 k0, MACH_COP_0_TLB_INDEX + mfc0 k0, COP_0_TLB_INDEX nop bltz k0, sys_stk_chk sltiu k0, k0, 8 @@ -1483,13 +1484,13 @@ KernTLBIOdd: dsll k0, k0, 34 # get rid of wired bit dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO1 # save PTE entry + dmtc0 k0, COP_0_TLB_LO1 # save PTE entry and k0, k0, PG_V # check for valid entry beq k0, zero, MachKernGenException # PTE invalid lw k0, -4(k1) # get even PTE entry dsll k0, k0, 34 dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO0 # save PTE entry + dmtc0 k0, COP_0_TLB_LO0 # save PTE entry nop tlbwi # update TLB nop @@ -1518,7 +1519,7 @@ END(MachTLBInvalidException) */ NLEAF(MachTLBMissException) .set noat - dmfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address + dmfc0 k0, COP_0_BAD_VADDR # get the fault address li k1, VM_MIN_KERNEL_ADDRESS # compute index subu k0, k0, k1 lw k1, Sysmapsize # index within range? @@ -1533,10 +1534,10 @@ NLEAF(MachTLBMissException) lw k1, 4(k1) # get odd PTE entry dsll k0, k0, 34 # get rid of "wired" bit dsrl k0, k0, 34 - dmtc0 k0, MACH_COP_0_TLB_LO0 # load PTE entry + dmtc0 k0, COP_0_TLB_LO0 # load PTE entry dsll k1, k1, 34 dsrl k1, k1, 34 - dmtc0 k1, MACH_COP_0_TLB_LO1 # load PTE entry + dmtc0 k1, COP_0_TLB_LO1 # load PTE entry nop tlbwr # write TLB nop @@ -1556,14 +1557,14 @@ sys_stk_chk: sw sp, 24(a0) move sp, a0 la a0, 1f - mfc0 a2, MACH_COP_0_STATUS_REG - mfc0 a3, MACH_COP_0_CAUSE_REG - dmfc0 a1, MACH_COP_0_EXC_PC + mfc0 a2, COP_0_STATUS_REG + mfc0 a3, COP_0_CAUSE_REG + dmfc0 a1, COP_0_EXC_PC sw a2, 16(sp) sw a3, 20(sp) move a2, ra jal printf - dmfc0 a3, MACH_COP_0_BAD_VADDR + dmfc0 a3, COP_0_BAD_VADDR .data 1: .asciiz "ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n" @@ -1579,37 +1580,37 @@ END(MachTLBMissException) */ LEAF(setsoftclock) - mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register + mfc0 v0, COP_0_CAUSE_REG # read cause register nop - or v0, v0, MACH_SOFT_INT_MASK_0 # set soft clock interrupt - mtc0 v0, MACH_COP_0_CAUSE_REG # save it + or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt + mtc0 v0, COP_0_CAUSE_REG # save it j ra nop END(setsoftclock) LEAF(clearsoftclock) - mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register + mfc0 v0, COP_0_CAUSE_REG # read cause register nop - and v0, v0, ~MACH_SOFT_INT_MASK_0 # clear soft clock interrupt - mtc0 v0, MACH_COP_0_CAUSE_REG # save it + and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt + mtc0 v0, COP_0_CAUSE_REG # save it j ra nop END(clearsoftclock) LEAF(setsoftnet) - mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register + mfc0 v0, COP_0_CAUSE_REG # read cause register nop - or v0, v0, MACH_SOFT_INT_MASK_1 # set soft net interrupt - mtc0 v0, MACH_COP_0_CAUSE_REG # save it + or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt + mtc0 v0, COP_0_CAUSE_REG # save it j ra nop END(setsoftnet) LEAF(clearsoftnet) - mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register + mfc0 v0, COP_0_CAUSE_REG # read cause register nop - and v0, v0, ~MACH_SOFT_INT_MASK_1 # clear soft net interrupt - mtc0 v0, MACH_COP_0_CAUSE_REG # save it + and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt + mtc0 v0, COP_0_CAUSE_REG # save it j ra nop END(clearsoftnet) @@ -1619,100 +1620,100 @@ END(clearsoftnet) */ LEAF(MachEnableIntr) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register + mfc0 v0, COP_0_STATUS_REG # read status register nop - or v0, v0, MACH_SR_INT_ENAB - mtc0 v0, MACH_COP_0_STATUS_REG # enable all interrupts + or v0, v0, SR_INT_ENAB + mtc0 v0, COP_0_STATUS_REG # enable all interrupts j ra nop END(MachEnableIntr) LEAF(spl0) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register + mfc0 v0, COP_0_STATUS_REG # read status register nop - or t0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) - mtc0 t0, MACH_COP_0_STATUS_REG # enable all interrupts + or t0, v0, (INT_MASK | SR_INT_ENAB) + mtc0 t0, COP_0_STATUS_REG # enable all interrupts j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(spl0) LEAF(splsoftclock) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~MACH_SOFT_INT_MASK_0 # disable soft clock + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~SOFT_INT_MASK_0 # disable soft clock and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(splsoftclock) LEAF(splsoftnet) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(splsoftnet) LEAF(Mach_spl0) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_0|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_0|SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl0) LEAF(Mach_spl1) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_1|MACH_SOFT_INT_MASK_0|MACH_SOFT_INT_MASK_1) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_1|SOFT_INT_MASK_0|SOFT_INT_MASK_1) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl1) LEAF(Mach_spl2) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_2|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_2|SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl2) LEAF(Mach_spl3) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_3|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_3|SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl3) LEAF(Mach_spl4) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_4|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_4|SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl4) LEAF(Mach_spl5) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~(MACH_INT_MASK_5|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0) + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~(INT_MASK_5|SOFT_INT_MASK_1|SOFT_INT_MASK_0) and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(Mach_spl5) /* @@ -1721,13 +1722,13 @@ END(Mach_spl5) */ LEAF(splhigh) ALEAF(_splhigh) - mfc0 v0, MACH_COP_0_STATUS_REG # read status register - li t0, ~MACH_SR_INT_ENAB # disable all interrupts + mfc0 v0, COP_0_STATUS_REG # read status register + li t0, ~SR_INT_ENAB # disable all interrupts and t0, t0, v0 - mtc0 t0, MACH_COP_0_STATUS_REG # save it + mtc0 t0, COP_0_STATUS_REG # save it nop # 3 ins to disable j ra - and v0, v0, (MACH_INT_MASK | MACH_SR_INT_ENAB) + and v0, v0, (INT_MASK | SR_INT_ENAB) END(splhigh) /* @@ -1735,11 +1736,11 @@ END(splhigh) */ LEAF(splx) ALEAF(_splx) - mfc0 v0, MACH_COP_0_STATUS_REG - li t0, ~(MACH_INT_MASK | MACH_SR_INT_ENAB) + mfc0 v0, COP_0_STATUS_REG + li t0, ~(INT_MASK | SR_INT_ENAB) and t0, t0, v0 or t0, t0, a0 - mtc0 t0, MACH_COP_0_STATUS_REG + mtc0 t0, COP_0_STATUS_REG nop # 3 ins to disable j ra nop @@ -1747,11 +1748,11 @@ END(splx) /*---------------------------------------------------------------------------- * - * MachEmptyWriteBuffer -- + * wbflush -- * * Return when the write buffer is empty. * - * MachEmptyWriteBuffer() + * wbflush() * * Results: * None. @@ -1761,12 +1762,12 @@ END(splx) * *---------------------------------------------------------------------------- */ -LEAF(MachEmptyWriteBuffer) +LEAF(wbflush) nop sync j ra nop -END(MachEmptyWriteBuffer) +END(wbflush) /*-------------------------------------------------------------------------- * @@ -1787,20 +1788,20 @@ END(MachEmptyWriteBuffer) *-------------------------------------------------------------------------- */ LEAF(MachTLBWriteIndexed) - mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts nop lw a2, 8(a1) lw a3, 12(a1) - dmfc0 t0, MACH_COP_0_TLB_HI # Save the current PID. + dmfc0 t0, COP_0_TLB_HI # Save the current PID. - dmtc0 a2, MACH_COP_0_TLB_LO0 # Set up entry low0. - dmtc0 a3, MACH_COP_0_TLB_LO1 # Set up entry low1. + dmtc0 a2, COP_0_TLB_LO0 # Set up entry low0. + dmtc0 a3, COP_0_TLB_LO1 # Set up entry low1. lw a2, 0(a1) lw a3, 4(a1) - mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index. - dmtc0 a2, MACH_COP_0_TLB_PG_MASK # Set up entry mask. - dmtc0 a3, MACH_COP_0_TLB_HI # Set up entry high. + mtc0 a0, COP_0_TLB_INDEX # Set the index. + dmtc0 a2, COP_0_TLB_PG_MASK # Set up entry mask. + dmtc0 a3, COP_0_TLB_HI # Set up entry high. nop tlbwi # Write the TLB nop @@ -1808,11 +1809,11 @@ LEAF(MachTLBWriteIndexed) nop # Delay for effect nop - dmtc0 t0, MACH_COP_0_TLB_HI # Restore the PID. + dmtc0 t0, COP_0_TLB_HI # Restore the PID. nop - dmtc0 zero, MACH_COP_0_TLB_PG_MASK # Default mask value. + dmtc0 zero, COP_0_TLB_PG_MASK # Default mask value. j ra - mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + mtc0 v1, COP_0_STATUS_REG # Restore the status register END(MachTLBWriteIndexed) /*-------------------------------------------------------------------------- @@ -1833,7 +1834,7 @@ END(MachTLBWriteIndexed) *-------------------------------------------------------------------------- */ LEAF(MachSetPID) - dmtc0 a0, MACH_COP_0_TLB_HI # Write the hi reg value + dmtc0 a0, COP_0_TLB_HI # Write the hi reg value j ra nop END(MachSetPID) @@ -1856,7 +1857,7 @@ END(MachSetPID) *-------------------------------------------------------------------------- */ LEAF(MachSetWIRED) - mtc0 a0, MACH_COP_0_TLB_WIRED + mtc0 a0, COP_0_TLB_WIRED j ra nop END(MachSetWIRED) @@ -1878,7 +1879,7 @@ END(MachSetWIRED) *-------------------------------------------------------------------------- */ LEAF(MachGetWIRED) - mfc0 v0, MACH_COP_0_TLB_WIRED + mfc0 v0, COP_0_TLB_WIRED j ra nop END(MachGetWIRED) @@ -1901,22 +1902,22 @@ END(MachGetWIRED) *-------------------------------------------------------------------------- */ LEAF(MachTLBFlush) - mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts - mfc0 t1, MACH_COP_0_TLB_WIRED - li t2, VMMACH_NUM_TLB_ENTRIES - li v0, MACH_CACHED_MEMORY_ADDR # invalid address - dmfc0 t0, MACH_COP_0_TLB_HI # Save the PID - - dmtc0 v0, MACH_COP_0_TLB_HI # Mark entry high as invalid - dmtc0 zero, MACH_COP_0_TLB_LO0 # Zero out low entry0. - dmtc0 zero, MACH_COP_0_TLB_LO1 # Zero out low entry1. - mtc0 zero, MACH_COP_0_TLB_PG_MASK # Zero out mask entry. + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts + mfc0 t1, COP_0_TLB_WIRED + li t2, VMNUM_TLB_ENTRIES + li v0, CACHED_MEMORY_ADDR # invalid address + dmfc0 t0, COP_0_TLB_HI # Save the PID + + dmtc0 v0, COP_0_TLB_HI # Mark entry high as invalid + dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry0. + dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry1. + mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. /* * Align the starting value (t1) and the upper bound (t2). */ 1: - mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register. + mtc0 t1, COP_0_TLB_INDEX # Set the index register. addu t1, t1, 1 # Increment index. tlbwi # Write the TLB entry. nop @@ -1924,9 +1925,9 @@ LEAF(MachTLBFlush) bne t1, t2, 1b nop - dmtc0 t0, MACH_COP_0_TLB_HI # Restore the PID + dmtc0 t0, COP_0_TLB_HI # Restore the PID j ra - mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + mtc0 v1, COP_0_STATUS_REG # Restore the status register END(MachTLBFlush) @@ -1948,13 +1949,13 @@ END(MachTLBFlush) *-------------------------------------------------------------------------- */ LEAF(MachTLBFlushAddr) - mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts nop li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 # Make shure valid hi value. - dmfc0 t0, MACH_COP_0_TLB_HI # Get current PID - dmtc0 a0, MACH_COP_0_TLB_HI # look for addr & PID + dmfc0 t0, COP_0_TLB_HI # Get current PID + dmtc0 a0, COP_0_TLB_HI # look for addr & PID nop nop nop @@ -1962,14 +1963,14 @@ LEAF(MachTLBFlushAddr) nop nop # Delay for effect nop - mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got - li t1, MACH_CACHED_MEMORY_ADDR # Load invalid entry. + mfc0 v0, COP_0_TLB_INDEX # See what we got + li t1, CACHED_MEMORY_ADDR # Load invalid entry. bltz v0, 1f # index < 0 => !found nop - dmtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid + dmtc0 t1, COP_0_TLB_HI # Mark entry high as invalid - dmtc0 zero, MACH_COP_0_TLB_LO0 # Zero out low entry. - dmtc0 zero, MACH_COP_0_TLB_LO1 # Zero out low entry. + dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry. + dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry. nop tlbwi nop @@ -1977,9 +1978,9 @@ LEAF(MachTLBFlushAddr) nop nop 1: - dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + dmtc0 t0, COP_0_TLB_HI # restore PID j ra - mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + mtc0 v1, COP_0_STATUS_REG # Restore the status register END(MachTLBFlushAddr) /*-------------------------------------------------------------------------- @@ -2000,13 +2001,13 @@ END(MachTLBFlushAddr) *-------------------------------------------------------------------------- */ LEAF(MachTLBUpdate) - mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts and t1, a0, 0x1000 # t1 = Even/Odd flag li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 - dmfc0 t0, MACH_COP_0_TLB_HI # Save current PID - dmtc0 a0, MACH_COP_0_TLB_HI # Init high reg + dmfc0 t0, COP_0_TLB_HI # Save current PID + dmtc0 a0, COP_0_TLB_HI # Init high reg and a2, a1, PG_G # Copy global bit nop nop @@ -2014,7 +2015,7 @@ LEAF(MachTLBUpdate) dsll a1, a1, 34 dsrl a1, a1, 34 bne t1, zero, 2f # Decide even odd - mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got + mfc0 v0, COP_0_TLB_INDEX # See what we got # EVEN nop bltz v0, 1f # index < 0 => !found @@ -2024,16 +2025,16 @@ LEAF(MachTLBUpdate) nop nop nop - dmtc0 a1, MACH_COP_0_TLB_LO0 # init low reg0. + dmtc0 a1, COP_0_TLB_LO0 # init low reg0. nop tlbwi # update slot found b 4f nop 1: - mtc0 zero, MACH_COP_0_TLB_PG_MASK # init mask. - dmtc0 a0, MACH_COP_0_TLB_HI # init high reg. - dmtc0 a1, MACH_COP_0_TLB_LO0 # init low reg0. - dmtc0 a2, MACH_COP_0_TLB_LO1 # init low reg1. + mtc0 zero, COP_0_TLB_PG_MASK # init mask. + dmtc0 a0, COP_0_TLB_HI # init high reg. + dmtc0 a1, COP_0_TLB_LO0 # init low reg0. + dmtc0 a2, COP_0_TLB_LO1 # init low reg1. nop tlbwr # enter into a random slot b 4f @@ -2048,16 +2049,16 @@ LEAF(MachTLBUpdate) nop nop nop - dmtc0 a1, MACH_COP_0_TLB_LO1 # init low reg1. + dmtc0 a1, COP_0_TLB_LO1 # init low reg1. nop tlbwi # update slot found b 4f nop 3: - mtc0 zero, MACH_COP_0_TLB_PG_MASK # init mask. - dmtc0 a0, MACH_COP_0_TLB_HI # init high reg. - dmtc0 a2, MACH_COP_0_TLB_LO0 # init low reg0. - dmtc0 a1, MACH_COP_0_TLB_LO1 # init low reg1. + mtc0 zero, COP_0_TLB_PG_MASK # init mask. + dmtc0 a0, COP_0_TLB_HI # init high reg. + dmtc0 a2, COP_0_TLB_LO0 # init low reg0. + dmtc0 a1, COP_0_TLB_LO1 # init low reg1. nop tlbwr # enter into a random slot @@ -2066,9 +2067,9 @@ LEAF(MachTLBUpdate) nop # uses the tlb. nop nop - dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + dmtc0 t0, COP_0_TLB_HI # restore PID j ra - mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + mtc0 v1, COP_0_STATUS_REG # Restore the status register END(MachTLBUpdate) /*-------------------------------------------------------------------------- @@ -2090,28 +2091,28 @@ END(MachTLBUpdate) *-------------------------------------------------------------------------- */ LEAF(MachTLBRead) - mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register. - mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts nop nop nop - dmfc0 t0, MACH_COP_0_TLB_HI # Get current PID + dmfc0 t0, COP_0_TLB_HI # Get current PID - mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index register + mtc0 a0, COP_0_TLB_INDEX # Set the index register nop tlbr # Read from the TLB nop nop nop - mfc0 t2, MACH_COP_0_TLB_PG_MASK # fetch the hi entry - dmfc0 t3, MACH_COP_0_TLB_HI # fetch the hi entry - dmfc0 t4, MACH_COP_0_TLB_LO0 # See what we got - dmfc0 t5, MACH_COP_0_TLB_LO1 # See what we got - dmtc0 t0, MACH_COP_0_TLB_HI # restore PID + mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry + dmfc0 t3, COP_0_TLB_HI # fetch the hi entry + dmfc0 t4, COP_0_TLB_LO0 # See what we got + dmfc0 t5, COP_0_TLB_LO1 # See what we got + dmtc0 t0, COP_0_TLB_HI # restore PID nop nop nop # wait for PID active - mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register + mtc0 v1, COP_0_STATUS_REG # Restore the status register sw t2, 0(a1) sw t3, 4(a1) sw t4, 8(a1) @@ -2134,9 +2135,9 @@ END(MachTLBRead) *-------------------------------------------------------------------------- */ LEAF(MachTLBGetPID) - dmfc0 v0, MACH_COP_0_TLB_HI # get PID + dmfc0 v0, COP_0_TLB_HI # get PID j ra - and v0, v0, VMMACH_TLB_PID # mask off PID + and v0, v0, VMTLB_PID # mask off PID END(MachTLBGetPID) @@ -2159,9 +2160,9 @@ END(MachTLBGetPID) *---------------------------------------------------------------------------- */ LEAF(MachSwitchFPState) - mfc0 t1, MACH_COP_0_STATUS_REG # Save old SR - li t0, MACH_SR_COP_1_BIT # enable the coprocessor - mtc0 t0, MACH_COP_0_STATUS_REG + mfc0 t1, COP_0_STATUS_REG # Save old SR + li t0, SR_COP_1_BIT # enable the coprocessor + mtc0 t0, COP_0_STATUS_REG beq a0, zero, 1f # skip save if NULL pointer nop @@ -2170,9 +2171,9 @@ LEAF(MachSwitchFPState) * have completed. */ lw a0, P_ADDR(a0) # get pointer to pcb for proc - cfc1 t0, MACH_FPC_CSR # stall til FP done - cfc1 t0, MACH_FPC_CSR # now get status - li t3, ~MACH_SR_COP_1_BIT + cfc1 t0, FPC_CSR # stall til FP done + cfc1 t0, FPC_CSR # now get status + li t3, ~SR_COP_1_BIT lw t2, U_PCB_REGS+(PS * 4)(a0) # get CPU status register sw t0, U_PCB_FPREGS+(32 * 4)(a0) # save FP status and t2, t2, t3 # clear COP_1 enable bit @@ -2251,11 +2252,11 @@ LEAF(MachSwitchFPState) lwc1 $f30, U_PCB_FPREGS+(30 * 4)(a1) lwc1 $f31, U_PCB_FPREGS+(31 * 4)(a1) - and t0, t0, ~MACH_FPC_EXCEPTION_BITS - ctc1 t0, MACH_FPC_CSR + and t0, t0, ~FPC_EXCEPTION_BITS + ctc1 t0, FPC_CSR nop - mtc0 t1, MACH_COP_0_STATUS_REG # Restore the status register. + mtc0 t1, COP_0_STATUS_REG # Restore the status register. j ra nop END(MachSwitchFPState) @@ -2279,19 +2280,19 @@ END(MachSwitchFPState) */ LEAF(MachSaveCurFPState) lw a0, P_ADDR(a0) # get pointer to pcb for proc - mfc0 t1, MACH_COP_0_STATUS_REG # Disable interrupts and - li t0, MACH_SR_COP_1_BIT # enable the coprocessor - mtc0 t0, MACH_COP_0_STATUS_REG + mfc0 t1, COP_0_STATUS_REG # Disable interrupts and + li t0, SR_COP_1_BIT # enable the coprocessor + mtc0 t0, COP_0_STATUS_REG sw zero, machFPCurProcPtr # indicate state has been saved /* * First read out the status register to make sure that all FP operations * have completed. */ lw t2, U_PCB_REGS+(PS * 4)(a0) # get CPU status register - li t3, ~MACH_SR_COP_1_BIT + li t3, ~SR_COP_1_BIT and t2, t2, t3 # clear COP_1 enable bit - cfc1 t0, MACH_FPC_CSR # stall til FP done - cfc1 t0, MACH_FPC_CSR # now get status + cfc1 t0, FPC_CSR # stall til FP done + cfc1 t0, FPC_CSR # now get status sw t2, U_PCB_REGS+(PS * 4)(a0) # save new status register sw t0, U_PCB_FPREGS+(32 * 4)(a0) # save FP status /* @@ -2330,7 +2331,7 @@ LEAF(MachSaveCurFPState) swc1 $f30, U_PCB_FPREGS+(30 * 4)(a0) swc1 $f31, U_PCB_FPREGS+(31 * 4)(a0) - mtc0 t1, MACH_COP_0_STATUS_REG # Restore the status register. + mtc0 t1, COP_0_STATUS_REG # Restore the status register. j ra nop END(MachSaveCurFPState) @@ -2356,18 +2357,18 @@ END(MachSaveCurFPState) */ NON_LEAF(MachFPTrap, STAND_FRAME_SIZE, ra) subu sp, sp, STAND_FRAME_SIZE - mfc0 t0, MACH_COP_0_STATUS_REG + mfc0 t0, COP_0_STATUS_REG sw ra, STAND_RA_OFFSET(sp) .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) - or t1, t0, MACH_SR_COP_1_BIT - mtc0 t1, MACH_COP_0_STATUS_REG + or t1, t0, SR_COP_1_BIT + mtc0 t1, COP_0_STATUS_REG nop nop nop nop - cfc1 t1, MACH_FPC_CSR # stall til FP done - cfc1 t1, MACH_FPC_CSR # now get status + cfc1 t1, FPC_CSR # stall til FP done + cfc1 t1, FPC_CSR # now get status nop sll t2, t1, (31 - 17) # unimplemented operation? bgez t2, 3f # no, normal trap @@ -2408,16 +2409,16 @@ NON_LEAF(MachFPTrap, STAND_FRAME_SIZE, ra) * Check to see if the instruction to be emulated is a floating-point * instruction. */ - srl a3, a0, MACH_OPCODE_SHIFT - beq a3, MACH_OPCODE_C1, 4f # this should never fail + srl a3, a0, OPCODE_SHIFT + beq a3, OPCODE_C1, 4f # this should never fail nop /* * Send a floating point exception signal to the current process. */ 3: lw a0, curproc # get current process - cfc1 a2, MACH_FPC_CSR # code = FP execptions - ctc1 zero, MACH_FPC_CSR # Clear exceptions + cfc1 a2, FPC_CSR # code = FP execptions + ctc1 zero, FPC_CSR # Clear exceptions jal trapsignal li a1, SIGFPE b FPReturn @@ -2434,10 +2435,10 @@ NON_LEAF(MachFPTrap, STAND_FRAME_SIZE, ra) * Turn off the floating point coprocessor and return. */ FPReturn: - mfc0 t0, MACH_COP_0_STATUS_REG + mfc0 t0, COP_0_STATUS_REG lw ra, STAND_RA_OFFSET(sp) - and t0, t0, ~MACH_SR_COP_1_BIT - mtc0 t0, MACH_COP_0_STATUS_REG + and t0, t0, ~SR_COP_1_BIT + mtc0 t0, COP_0_STATUS_REG j ra addu sp, sp, STAND_FRAME_SIZE END(MachFPTrap) @@ -2460,7 +2461,7 @@ END(MachFPTrap) *---------------------------------------------------------------------------- */ LEAF(MachConfigCache) - mfc0 v0, MACH_COP_0_CONFIG # Get configuration register + mfc0 v0, COP_0_CONFIG # Get configuration register nop srl t1, v0, 9 # Get I cache size. and t1, 3 @@ -2511,7 +2512,7 @@ LEAF(MachFlushCache) /* * Flush the instruction cache. */ - li t0, MACH_CACHED_MEMORY_ADDR + li t0, CACHED_MEMORY_ADDR addu t1, t0, t1 # End address subu t1, t1, 128 1: @@ -2529,7 +2530,7 @@ LEAF(MachFlushCache) /* * Flush the data cache. */ - li t0, MACH_CACHED_MEMORY_ADDR + li t0, CACHED_MEMORY_ADDR addu t1, t0, t2 # End address subu t1, t1, 128 1: @@ -2839,7 +2840,7 @@ L* { L* } */ LEAF(mdbpanic) - break MACH_BREAK_SOVER_VAL + break BREAK_SOVER_VAL j ra nop END(mdbpanic) diff --git a/sys/arch/pica/pica/machdep.c b/sys/arch/pica/pica/machdep.c index 230de8858c9..9491a0c9e51 100644 --- a/sys/arch/pica/pica/machdep.c +++ b/sys/arch/pica/pica/machdep.c @@ -37,7 +37,7 @@ * SUCH DAMAGE. * * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 - * $Id: machdep.c,v 1.8 1996/05/15 07:09:11 pefo Exp $ + * $Id: machdep.c,v 1.9 1996/06/06 23:07:37 deraadt Exp $ */ /* from: Utah Hdr: machdep.c 1.63 91/04/24 */ @@ -259,7 +259,7 @@ mips_init(argc, argv, code) */ MachSetWIRED(0); MachTLBFlush(); - MachSetWIRED(VMMACH_WIRED_ENTRIES); + MachSetWIRED(VMWIRED_ENTRIES); /* * Set up mapping for hardware the way we want it! @@ -302,7 +302,7 @@ mips_init(argc, argv, code) start = v; curproc->p_addr = proc0paddr = (struct user *)v; curproc->p_md.md_regs = proc0paddr->u_pcb.pcb_regs; - firstaddr = MACH_CACHED_TO_PHYS(v); + firstaddr = CACHED_TO_PHYS(v); for (i = 0; i < UPAGES; i+=2) { tlb.tlb_mask = PG_SIZE_4K; tlb.tlb_hi = vad_to_vpn((UADDR + (i << PGSHIFT))) | 1; @@ -325,7 +325,7 @@ mips_init(argc, argv, code) nullproc.p_addr = (struct user *)v; nullproc.p_md.md_regs = nullproc.p_addr->u_pcb.pcb_regs; bcopy("nullproc", nullproc.p_comm, sizeof("nullproc")); - firstaddr = MACH_CACHED_TO_PHYS(v); + firstaddr = CACHED_TO_PHYS(v); for (i = 0; i < UPAGES; i+=2) { nullproc.p_md.md_upte[i] = vad_to_pfn(firstaddr) | PG_V | PG_M | PG_CACHED; nullproc.p_md.md_upte[i+1] = vad_to_pfn(firstaddr + NBPG) | PG_V | PG_M | PG_CACHED; @@ -341,9 +341,9 @@ mips_init(argc, argv, code) */ if (MachTLBMissEnd - MachTLBMiss > 0x80) panic("startup: TLB code too large"); - bcopy(MachTLBMiss, (char *)MACH_TLB_MISS_EXC_VEC, + bcopy(MachTLBMiss, (char *)TLB_MISS_EXC_VEC, MachTLBMissEnd - MachTLBMiss); - bcopy(MachException, (char *)MACH_GEN_EXC_VEC, + bcopy(MachException, (char *)GEN_EXC_VEC, MachExceptionEnd - MachException); /* @@ -398,8 +398,8 @@ mips_init(argc, argv, code) default: physmem = btoc((u_int)v - KERNBASE); - cp = (char *)MACH_PHYS_TO_UNCACHED(physmem << PGSHIFT); - while (cp < (char *)MACH_MAX_MEM_ADDR) { + cp = (char *)PHYS_TO_UNCACHED(physmem << PGSHIFT); + while (cp < (char *)MAX_MEM_ADDR) { if (badaddr(cp, 4)) break; i = *(int *)cp; @@ -409,7 +409,7 @@ mips_init(argc, argv, code) * Have to be tricky here. */ ((int *)cp)[4] = 0x5a5a5a5a; - MachEmptyWriteBuffer(); + wbflush(); if (*(int *)cp != 0xa5a5a5a5) break; *(int *)cp = i; @@ -425,7 +425,7 @@ mips_init(argc, argv, code) * Initialize error message buffer (at end of core). */ maxmem -= btoc(sizeof (struct msgbuf)); - msgbufp = (struct msgbuf *)(MACH_PHYS_TO_CACHED(maxmem << PGSHIFT)); + msgbufp = (struct msgbuf *)(PHYS_TO_CACHED(maxmem << PGSHIFT)); msgbufmapped = 1; /* diff --git a/sys/arch/pica/pica/mem.c b/sys/arch/pica/pica/mem.c index 6e748f1168c..60615295daa 100644 --- a/sys/arch/pica/pica/mem.c +++ b/sys/arch/pica/pica/mem.c @@ -108,7 +108,7 @@ mmrw(dev, uio, flags) c = iov->iov_len; if (v + c > ctob(physmem)) return (EFAULT); - v += MACH_CACHED_MEMORY_ADDR; + v += CACHED_MEMORY_ADDR; error = uiomove((caddr_t)v, c, uio); continue; @@ -116,11 +116,11 @@ mmrw(dev, uio, flags) case 1: v = uio->uio_offset; c = min(iov->iov_len, MAXPHYS); - if (v < MACH_CACHED_MEMORY_ADDR) + if (v < CACHED_MEMORY_ADDR) return (EFAULT); - if (v + c > MACH_PHYS_TO_CACHED(avail_end + + if (v + c > PHYS_TO_CACHED(avail_end + sizeof (struct msgbuf)) && - (v < MACH_KSEG2_ADDR || + (v < KSEG2_ADDR || !kernacc((caddr_t)v, c, uio->uio_rw == UIO_READ ? B_READ : B_WRITE))) return (EFAULT); diff --git a/sys/arch/pica/pica/minidebug.c b/sys/arch/pica/pica/minidebug.c index 62f68d8d027..18d64222674 100644 --- a/sys/arch/pica/pica/minidebug.c +++ b/sys/arch/pica/pica/minidebug.c @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * from: @(#)kadb.c 8.1 (Berkeley) 6/10/93 - * $Id: minidebug.c,v 1.2 1996/05/01 18:16:13 pefo Exp $ + * $Id: minidebug.c,v 1.3 1996/06/06 23:07:41 deraadt Exp $ */ /* @@ -45,7 +45,7 @@ #include <machine/pte.h> #include <vm/vm_prot.h> #undef SP -#include <machine/machConst.h> +#include <machine/cpu.h> #include <machine/reg.h> #include <machine/pcb.h> #include <machine/trap.h> @@ -252,7 +252,7 @@ break_insert() for(i = 0; i < MAXBRK; i++) { if(brk_tab[i].addr != 0) { brk_tab[i].inst = *(u_int *)brk_tab[i].addr; - *(u_int *)brk_tab[i].addr = MACH_BREAK_BRKPT; + *(u_int *)brk_tab[i].addr = BREAK_BRKPT; MachFlushDCache(brk_tab[i].addr,4); MachFlushICache(brk_tab[i].addr,4); } @@ -304,11 +304,11 @@ mdb(causeReg, vadr, p, kernelmode) static int ssandrun; /* Single step and run flag (when cont at brk) */ splhigh(); - cause = (causeReg & MACH_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT; + cause = (causeReg & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT; newaddr = (int)(mdbpcb.pcb_regs[PC]); switch(cause) { case T_BREAK: - if(*(int *)newaddr == MACH_BREAK_SOVER) { + if(*(int *)newaddr == BREAK_SOVER) { break_restore(); mdbpcb.pcb_regs[PC] += 4; printf("\nStop break (panic)\n# "); @@ -317,7 +317,7 @@ static int ssandrun; /* Single step and run flag (when cont at brk) */ printf("\n# "); break; } - if(*(int *)newaddr == MACH_BREAK_BRKPT) { + if(*(int *)newaddr == BREAK_BRKPT) { break_restore(); printf("\rBRK %08x\t",newaddr); if(mdbprintins(*(int *)newaddr, newaddr)) { @@ -565,7 +565,7 @@ mdbsetsstep() if ((int)va < 0) { /* kernel address */ mdb_ss_instr = mdbpeek(va); - mdbpoke((caddr_t)va, MACH_BREAK_SSTEP); + mdbpoke((caddr_t)va, BREAK_SSTEP); MachFlushDCache(va,4); MachFlushICache(va,4); return; @@ -590,7 +590,7 @@ mdbclrsstep(cr) /* read break instruction */ instr = mdbpeek(va); - if (instr != MACH_BREAK_SSTEP) + if (instr != BREAK_SSTEP) return(FALSE); if ((int)va < 0) { diff --git a/sys/arch/pica/pica/pica.c b/sys/arch/pica/pica/pica.c index f4e300ba8a5..b912dd4f219 100644 --- a/sys/arch/pica/pica/pica.c +++ b/sys/arch/pica/pica/pica.c @@ -170,7 +170,7 @@ picaattach(parent, self, aux) sc->sc_devs = pica_cpu_devs[cputype]; /* set up interrupt handlers */ - set_intr(MACH_INT_MASK_1, pica_iointr, 2); + set_intr(INT_MASK_1, pica_iointr, 2); sc->sc_bus.ab_dv = (struct device *)sc; sc->sc_bus.ab_type = BUS_PICA; @@ -230,7 +230,7 @@ pica_intr_establish(ca, handler, val) slot = ca->ca_slot; if(slot == 0) { /* Slot 0 is special, clock */ - set_intr(MACH_INT_MASK_4, pica_clkintr, 1); + set_intr(INT_MASK_4, pica_clkintr, 1); } if(int_table[slot].int_mask != 0) { @@ -315,8 +315,8 @@ pica_clkintr(mask, pc, statusReg, causeReg) hardclock(&cf); /* Re-enable clock interrupts */ - splx(MACH_INT_MASK_4 | MACH_SR_INT_ENAB); + splx(INT_MASK_4 | SR_INT_ENAB); - return(~MACH_INT_MASK_4); /* Keep clock interrupts enabled */ + return(~INT_MASK_4); /* Keep clock interrupts enabled */ } diff --git a/sys/arch/pica/pica/pmap.c b/sys/arch/pica/pica/pmap.c index f4fdc2f71ea..3ef2129fc76 100644 --- a/sys/arch/pica/pica/pmap.c +++ b/sys/arch/pica/pica/pmap.c @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)pmap.c 8.4 (Berkeley) 1/26/94 - * $Id: pmap.c,v 1.3 1996/05/02 07:59:43 pefo Exp $ + * $Id: pmap.c,v 1.4 1996/06/06 23:07:44 deraadt Exp $ */ /* @@ -78,9 +78,8 @@ #include <vm/vm_page.h> #include <vm/vm_pageout.h> -#include <machine/machConst.h> -#include <machine/pte.h> #include <machine/cpu.h> +#include <machine/pte.h> extern vm_page_t vm_page_alloc1 __P((void)); extern void vm_page_free1 __P((vm_page_t)); @@ -206,7 +205,7 @@ pmap_bootstrap(firstaddr) * phys_start and phys_end but its better to use kseg0 addresses * rather than kernel virtual addresses mapped through the TLB. */ - i = maxmem - pica_btop(MACH_CACHED_TO_PHYS(firstaddr)); + i = maxmem - pica_btop(CACHED_TO_PHYS(firstaddr)); valloc(pv_table, struct pv_entry, i); /* @@ -215,7 +214,7 @@ pmap_bootstrap(firstaddr) firstaddr = pica_round_page(firstaddr); bzero((caddr_t)start, firstaddr - start); - avail_start = MACH_CACHED_TO_PHYS(firstaddr); + avail_start = CACHED_TO_PHYS(firstaddr); avail_end = pica_ptob(maxmem); mem_size = avail_end - avail_start; @@ -258,7 +257,7 @@ pmap_bootstrap_alloc(size) if (vm_page_startup_initialized) panic("pmap_bootstrap_alloc: called after startup initialized"); - val = MACH_PHYS_TO_CACHED(avail_start); + val = PHYS_TO_CACHED(avail_start); size = round_page(size); avail_start += size; @@ -354,7 +353,7 @@ pmap_pinit(pmap) mem = vm_page_alloc1(); pmap_zero_page(VM_PAGE_TO_PHYS(mem)); pmap->pm_segtab = stp = (struct segtab *) - MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem)); + PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem)); i = NBPG / sizeof(struct segtab); s = splimp(); while (--i != 0) { @@ -446,7 +445,7 @@ pmap_release(pmap) #endif MachHitFlushDCache(pte, PAGE_SIZE); vm_page_free1( - PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte))); + PHYS_TO_VM_PAGE(CACHED_TO_PHYS(pte))); pmap->pm_segtab->seg_tab[i] = NULL; } s = splimp(); @@ -574,7 +573,7 @@ pmap_remove(pmap, sva, eva) */ if (pmap->pm_tlbgen == tlbpid_gen) { MachTLBFlushAddr(sva | (pmap->pm_tlbpid << - VMMACH_TLB_PID_SHIFT)); + VMTLB_PID_SHIFT)); #ifdef DEBUG remove_stats.flushes++; #endif @@ -736,7 +735,7 @@ pmap_protect(pmap, sva, eva, prot) */ if (pmap->pm_tlbgen == tlbpid_gen) MachTLBUpdate(sva | (pmap->pm_tlbpid << - VMMACH_TLB_PID_SHIFT), entry); + VMTLB_PID_SHIFT), entry); } } } @@ -802,7 +801,7 @@ pmap_page_cache(pa,mode) pte->pt_entry = entry; if (pv->pv_pmap->pm_tlbgen == tlbpid_gen) MachTLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid << - VMMACH_TLB_PID_SHIFT), entry); + VMTLB_PID_SHIFT), entry); } } } @@ -1015,7 +1014,7 @@ pmap_enter(pmap, va, pa, prot, wired) * NOTE: we only support cache flush for read only text. */ if (prot == (VM_PROT_READ | VM_PROT_EXECUTE)) - MachFlushICache(MACH_PHYS_TO_CACHED(pa), PAGE_SIZE); + MachFlushICache(PHYS_TO_CACHED(pa), PAGE_SIZE); if (!pmap->pm_segtab) { /* enter entries into kernel pmap */ @@ -1045,7 +1044,7 @@ pmap_enter(pmap, va, pa, prot, wired) mem = vm_page_alloc1(); pmap_zero_page(VM_PAGE_TO_PHYS(mem)); pmap_segmap(pmap, va) = pte = (pt_entry_t *) - MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem)); + PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem)); #ifdef DIAGNOSTIC for (i = 0; i < NPTEPG; i++) { if ((pte+i)->pt_entry) @@ -1079,7 +1078,7 @@ pmap_enter(pmap, va, pa, prot, wired) pte->pt_entry = npte; if (pmap->pm_tlbgen == tlbpid_gen) j = MachTLBUpdate(va | (pmap->pm_tlbpid << - VMMACH_TLB_PID_SHIFT), npte); + VMTLB_PID_SHIFT), npte); } /* @@ -1256,7 +1255,7 @@ pmap_zero_page(phys) #endif /*XXX FIXME Not very sophisticated */ MachFlushCache(); - p = (int *)MACH_PHYS_TO_CACHED(phys); + p = (int *)PHYS_TO_CACHED(phys); end = p + PAGE_SIZE / sizeof(int); do { p[0] = 0; @@ -1286,8 +1285,8 @@ pmap_copy_page(src, dst) #endif /*XXX FIXME Not very sophisticated */ MachFlushCache(); - s = (int *)MACH_PHYS_TO_CACHED(src); - d = (int *)MACH_PHYS_TO_CACHED(dst); + s = (int *)PHYS_TO_CACHED(src); + d = (int *)PHYS_TO_CACHED(dst); end = s + PAGE_SIZE / sizeof(int); do { tmp0 = s[0]; @@ -1438,7 +1437,7 @@ pmap_alloc_tlbpid(p) pmap = &p->p_vmspace->vm_pmap; if (pmap->pm_tlbgen != tlbpid_gen) { id = tlbpid_cnt; - if (id == VMMACH_NUM_PIDS) { + if (id == VMNUM_PIDS) { MachTLBFlush(); /* reserve tlbpid_gen == 0 to alway mean invalid */ if (++tlbpid_gen == 0) diff --git a/sys/arch/pica/pica/trap.c b/sys/arch/pica/pica/trap.c index f780ee63716..acbbd6545f1 100644 --- a/sys/arch/pica/pica/trap.c +++ b/sys/arch/pica/pica/trap.c @@ -38,7 +38,7 @@ * from: Utah Hdr: trap.c 1.32 91/04/06 * * from: @(#)trap.c 8.5 (Berkeley) 1/11/94 - * $Id: trap.c,v 1.6 1996/05/15 07:09:12 pefo Exp $ + * $Id: trap.c,v 1.7 1996/06/06 23:07:46 deraadt Exp $ */ #include <sys/param.h> @@ -217,7 +217,7 @@ extern void stacktrace(); extern void logstacktrace(); /* extern functions printed by name in stack backtraces */ -extern void idle(), cpu_switch(), splx(), MachEmptyWriteBuffer(); +extern void idle(), cpu_switch(), splx(), wbflush(); extern void MachTLBMiss(); #endif /* DEBUG */ @@ -261,7 +261,7 @@ trap(statusReg, causeReg, vadr, pc, args) #endif cnt.v_trap++; - type = (causeReg & MACH_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT; + type = (causeReg & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT; if (USERMODE(statusReg)) { type |= T_USER; sticks = p->p_sticks; @@ -271,8 +271,8 @@ trap(statusReg, causeReg, vadr, pc, args) * Enable hardware interrupts if they were on before. * We only respond to software interrupts when returning to user mode. */ - if (statusReg & MACH_SR_INT_ENAB) - splx((statusReg & MACH_HARD_INT_MASK) | MACH_SR_INT_ENAB); + if (statusReg & SR_INT_ENAB) + splx((statusReg & HARD_INT_MASK) | SR_INT_ENAB); switch (type) { case T_TLB_MOD: @@ -333,7 +333,7 @@ trap(statusReg, causeReg, vadr, pc, args) entry |= PG_M; pte->pt_entry = entry; vadr = (vadr & ~PGOFSET) | - (pmap->pm_tlbpid << VMMACH_TLB_PID_SHIFT); + (pmap->pm_tlbpid << VMTLB_PID_SHIFT); MachTLBUpdate(vadr, entry); pa = pfn_to_vad(entry); #ifdef ATTR @@ -648,7 +648,7 @@ trap(statusReg, causeReg, vadr, pc, args) p->p_comm, p->p_pid, instr, pc, p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */ #endif - if (p->p_md.md_ss_addr != va || instr != MACH_BREAK_SSTEP) { + if (p->p_md.md_ss_addr != va || instr != BREAK_SSTEP) { i = SIGTRAP; break; } @@ -682,13 +682,13 @@ trap(statusReg, causeReg, vadr, pc, args) break; case T_COP_UNUSABLE+T_USER: - if ((causeReg & MACH_CR_COP_ERR) != 0x10000000) { + if ((causeReg & CR_COP_ERR) != 0x10000000) { i = SIGILL; /* only FPU instructions allowed */ break; } MachSwitchFPState(machFPCurProcPtr, p->p_md.md_regs); machFPCurProcPtr = p; - p->p_md.md_regs[PS] |= MACH_SR_COP_1_BIT; + p->p_md.md_regs[PS] |= SR_COP_1_BIT; p->p_md.md_flags |= MDP_FPUSED; goto out; @@ -850,10 +850,10 @@ interrupt(statusReg, causeReg, pc, what, args) /* * Reenable all non served hardware levels. */ - splx((statusReg & ~causeReg & MACH_HARD_INT_MASK) | MACH_SR_INT_ENAB); + splx((statusReg & ~causeReg & HARD_INT_MASK) | SR_INT_ENAB); - if (mask & MACH_SOFT_INT_MASK_0) { + if (mask & SOFT_INT_MASK_0) { clearsoftclock(); cnt.v_soft++; softclock(); @@ -861,8 +861,8 @@ interrupt(statusReg, causeReg, pc, what, args) /* * Process network interrupt if we trapped or will very soon */ - if ((mask & MACH_SOFT_INT_MASK_1) || - netisr && (statusReg & MACH_SOFT_INT_MASK_1)) { + if ((mask & SOFT_INT_MASK_1) || + netisr && (statusReg & SOFT_INT_MASK_1)) { clearsoftnet(); cnt.v_soft++; intrcnt[1]++; @@ -896,7 +896,7 @@ interrupt(statusReg, causeReg, pc, what, args) } #endif } - if (mask & MACH_SOFT_INT_MASK_0) { + if (mask & SOFT_INT_MASK_0) { clearsoftclock(); intrcnt[0]++; cnt.v_soft++; @@ -923,7 +923,7 @@ set_intr(mask, int_hand, prio) /* * Update external interrupt mask but dont enable clock. */ - out32(PICA_SYS_EXT_IMASK, cpu_int_mask & (~MACH_INT_MASK_4 >> 10)); + out32(PICA_SYS_EXT_IMASK, cpu_int_mask & (~INT_MASK_4 >> 10)); } /* @@ -986,8 +986,8 @@ trapDump(msg) if (trp->cause == 0) break; printf("%s: ADR %x PC %x CR %x SR %x\n", - trap_type[(trp->cause & MACH_CR_EXC_CODE) >> - MACH_CR_EXC_CODE_SHIFT], + trap_type[(trp->cause & CR_EXC_CODE) >> + CR_EXC_CODE_SHIFT], trp->vadr, trp->pc, trp->cause, trp->status); printf(" RA %x SP %x code %d\n", trp->ra, trp->sp, trp->code); } @@ -1016,14 +1016,14 @@ pica_errintr() { #if 0 volatile u_short *sysCSRPtr = - (u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR); + (u_short *)PHYS_TO_UNCACHED(KN01_SYS_CSR); u_short csr; csr = *sysCSRPtr; if (csr & KN01_CSR_MERR) { printf("Memory error at 0x%x\n", - *(unsigned *)MACH_PHYS_TO_UNCACHED(KN01_SYS_ERRADR)); + *(unsigned *)PHYS_TO_UNCACHED(KN01_SYS_ERRADR)); panic("Mem error interrupt"); } *sysCSRPtr = (csr & ~KN01_CSR_MBZ) | 0xff; @@ -1145,9 +1145,9 @@ MachEmulateBranch(regsPtr, instPC, fpcCSR, allowNonBranch) case OP_BCx: case OP_BCy: if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE) - condition = fpcCSR & MACH_FPC_COND_BIT; + condition = fpcCSR & FPC_COND_BIT; else - condition = !(fpcCSR & MACH_FPC_COND_BIT); + condition = !(fpcCSR & FPC_COND_BIT); if (condition) retAddr = GetBranchDest(instPC, inst); else @@ -1183,7 +1183,7 @@ cpu_singlestep(p) register unsigned va; register int *locr0 = p->p_md.md_regs; int i; - int bpinstr = MACH_BREAK_SSTEP; + int bpinstr = BREAK_SSTEP; int curinstr; struct uio uio; struct iovec iov; @@ -1368,7 +1368,7 @@ specialframe: subr = (unsigned) MachKernIntr; else if (pcBetween(MachUserIntr, MachTLBInvalidException)) subr = (unsigned) MachUserIntr; - else if (pcBetween(splx, MachEmptyWriteBuffer)) + else if (pcBetween(splx, wbflush)) subr = (unsigned) splx; else if (pcBetween(cpu_switch, fuword)) subr = (unsigned) cpu_switch; diff --git a/sys/arch/pica/stand/start.S b/sys/arch/pica/stand/start.S index 229867106e7..09114a91b7e 100644 --- a/sys/arch/pica/stand/start.S +++ b/sys/arch/pica/stand/start.S @@ -44,8 +44,8 @@ */ #include <machine/regdef.h> -#include <machine/machConst.h> -#include <machine/machAsmDefs.h> +#include <machine/cpu.h> +#include <machine/asm.h> /* * Frame required for the debugger (if we have any) |