diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/i386/conf/GENERIC | 4 | ||||
| -rw-r--r-- | sys/dev/pci/files.pci | 7 | ||||
| -rw-r--r-- | sys/dev/pci/if_vge.c | 1891 | ||||
| -rw-r--r-- | sys/dev/pci/if_vgereg.h | 697 | ||||
| -rw-r--r-- | sys/dev/pci/if_vgevar.h | 126 |
5 files changed, 2723 insertions, 2 deletions
diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC index 2c23cfe5f38..345a45f5c34 100644 --- a/sys/arch/i386/conf/GENERIC +++ b/sys/arch/i386/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.387 2004/11/17 16:53:05 mickey Exp $ +# $OpenBSD: GENERIC,v 1.388 2004/12/01 01:29:00 pvalchev Exp $ # # GENERIC -- everything that's currently supported # @@ -421,6 +421,7 @@ stge* at pci? # Sundance TC9021 GigE #lge* at pci? # Level1 LXT1001 GigE hme* at pci? # Sun Happy Meal bce* at pci? # Broadcom BCM4401 +vge* at pci? # VIA VT612x # Wireless network cards ath* at pci? # Atheros AR5k (802.11a/b/g) @@ -461,6 +462,7 @@ xmphy* at mii? # XaQti XMAC-II PHYs nsgphy* at mii? # NS gigabit PHYs urlphy* at mii? # Realtek RTL8150L internal PHY rgephy* at mii? # Realtek 8169S/8110S PHY +ciphy* at mii? # Cicada CS8201 10/100/1000 copper PHY ukphy* at mii? # "unknown" PHYs pss0 at isa? port 0x220 irq 7 drq 6 # Personal Sound System diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 5d26b88b4ee..12404c2afa6 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.164 2004/11/22 21:34:35 damien Exp $ +# $OpenBSD: files.pci,v 1.165 2004/12/01 01:28:59 pvalchev Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -478,6 +478,11 @@ device re: ether, ifnet, mii, ifmedia, mii_phy attach re at pci file dev/pci/if_re.c re +# VIA VT6122 +device vge: ether, ifnet, mii, ifmedia, mii_phy +attach vge at pci +file dev/pci/if_vge.c vge + # Sundance Tech./Tamarack TC9021 Gigabit Ethernet device stge: ether, ifnet, mii, ifmedia, mii_phy, mii_bitbang attach stge at pci diff --git a/sys/dev/pci/if_vge.c b/sys/dev/pci/if_vge.c new file mode 100644 index 00000000000..e166569d260 --- /dev/null +++ b/sys/dev/pci/if_vge.c @@ -0,0 +1,1891 @@ +/* $OpenBSD: if_vge.c,v 1.1 2004/12/01 01:29:00 pvalchev Exp $ */ +/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ +/* + * Copyright (c) 2004 + * Bill Paul <wpaul@windriver.com>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. + * + * Written by Bill Paul <wpaul@windriver.com> + * Senior Networking Software Engineer + * Wind River Systems + * + * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> + */ + +/* + * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that + * combines a tri-speed ethernet MAC and PHY, with the following + * features: + * + * o Jumbo frame support up to 16K + * o Transmit and receive flow control + * o IPv4 checksum offload + * o VLAN tag insertion and stripping + * o TCP large send + * o 64-bit multicast hash table filter + * o 64 entry CAM filter + * o 16K RX FIFO and 48K TX FIFO memory + * o Interrupt moderation + * + * The VT6122 supports up to four transmit DMA queues. The descriptors + * in the transmit ring can address up to 7 data fragments; frames which + * span more than 7 data buffers must be coalesced, but in general the + * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments + * long. The receive descriptors address only a single buffer. + * + * There are two peculiar design issues with the VT6122. One is that + * receive data buffers must be aligned on a 32-bit boundary. This is + * not a problem where the VT6122 is used as a LOM device in x86-based + * systems, but on architectures that generate unaligned access traps, we + * have to do some copying. + * + * The other issue has to do with the way 64-bit addresses are handled. + * The DMA descriptors only allow you to specify 48 bits of addressing + * information. The remaining 16 bits are specified using one of the + * I/O registers. If you only have a 32-bit system, then this isn't + * an issue, but if you have a 64-bit system and more than 4GB of + * memory, you must have to make sure your network data buffers reside + * in the same 48-bit 'segment.' + * + * Special thanks to Ryan Fu at VIA Networking for providing documentation + * and sample NICs for testing. + */ + +#include "bpfilter.h" +#include "vlan.h" + +#include <sys/param.h> +#include <sys/endian.h> +#include <sys/systm.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <sys/socket.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_media.h> + +#ifdef INET +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> +#endif + +#if NVLAN > 0 +#include <net/if_types.h> +#include <net/if_vlan_var.h> +#endif + +#if NBPFILTER > 0 +#include <net/bpf.h> +#endif + +#include <dev/mii/mii.h> +#include <dev/mii/miivar.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +#include <dev/pci/if_vgereg.h> +#include <dev/pci/if_vgevar.h> + +int vge_probe (struct device *, void *, void *); +void vge_attach (struct device *, struct device *, void *); + +int vge_encap (struct vge_softc *, struct mbuf *, int); + +int vge_allocmem (struct vge_softc *); +int vge_newbuf (struct vge_softc *, int, struct mbuf *); +int vge_rx_list_init (struct vge_softc *); +int vge_tx_list_init (struct vge_softc *); +void vge_rxeof (struct vge_softc *); +void vge_txeof (struct vge_softc *); +int vge_intr (void *); +void vge_tick (void *); +void vge_tx_task (void *, int); +void vge_start (struct ifnet *); +int vge_ioctl (struct ifnet *, u_long, caddr_t); +int vge_init (struct ifnet *); +void vge_stop (struct vge_softc *); +void vge_watchdog (struct ifnet *); +int vge_ifmedia_upd (struct ifnet *); +void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); + +void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); +void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); + +void vge_miipoll_start (struct vge_softc *); +void vge_miipoll_stop (struct vge_softc *); +int vge_miibus_readreg (struct device *, int, int); +void vge_miibus_writereg (struct device *, int, int, int); +void vge_miibus_statchg (struct device *); + +void vge_cam_clear (struct vge_softc *); +int vge_cam_set (struct vge_softc *, uint8_t *); +void vge_setmulti (struct vge_softc *); +void vge_reset (struct vge_softc *); + +struct cfattach vge_ca = { + sizeof(struct vge_softc), vge_probe, vge_attach +}; + +struct cfdriver vge_cd = { + 0, "vge", DV_IFNET +}; + +#define VGE_PCI_LOIO 0x10 +#define VGE_PCI_LOMEM 0x14 + +int vge_debug = 0; +#define DPRINTF(x) if (vge_debug) printf x +#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x + +const struct pci_matchid vge_devices[] = { + { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, +}; + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +void +vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) +{ + register int i; + u_int16_t word = 0; + + /* + * Enter EEPROM embedded programming mode. In order to + * access the EEPROM at all, we first have to set the + * EELOAD bit in the CHIPCFG2 register. + */ + CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); + CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); + + /* Select the address of the word we want to read */ + CSR_WRITE_1(sc, VGE_EEADDR, addr); + + /* Issue read command */ + CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); + + /* Wait for the done bit to be set. */ + for (i = 0; i < VGE_TIMEOUT; i++) { + if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); + *dest = 0; + return; + } + + /* Read the result */ + word = CSR_READ_2(sc, VGE_EERDDAT); + + /* Turn off EEPROM access mode. */ + CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); + CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); + + *dest = word; +} + +/* + * Read a sequence of words from the EEPROM. + */ +void +vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, + int swap) +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + vge_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (swap) + *ptr = ntohs(word); + else + *ptr = word; + } +} + +void +vge_miipoll_stop(struct vge_softc *sc) +{ + int i; + + CSR_WRITE_1(sc, VGE_MIICMD, 0); + + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) + break; + } + + if (i == VGE_TIMEOUT) + printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); +} + +void +vge_miipoll_start(struct vge_softc *sc) +{ + int i; + + /* First, make sure we're idle. */ + + CSR_WRITE_1(sc, VGE_MIICMD, 0); + CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); + + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); + return; + } + + /* Now enable auto poll mode. */ + + CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); + + /* And make sure it started. */ + + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) + break; + } + + if (i == VGE_TIMEOUT) + printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); +} + +int +vge_miibus_readreg(struct device *dev, int phy, int reg) +{ + struct vge_softc *sc = (struct vge_softc *)dev; + int i, s; + u_int16_t rval = 0; + + if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) + return(0); + + s = splimp(); + + vge_miipoll_stop(sc); + + /* Specify the register we want to read. */ + CSR_WRITE_1(sc, VGE_MIIADDR, reg); + + /* Issue read command. */ + CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); + + /* Wait for the read command bit to self-clear. */ + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) + break; + } + + if (i == VGE_TIMEOUT) + printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); + else + rval = CSR_READ_2(sc, VGE_MIIDATA); + + vge_miipoll_start(sc); + splx(s); + + return (rval); +} + +void +vge_miibus_writereg(struct device *dev, int phy, int reg, int data) +{ + struct vge_softc *sc = (struct vge_softc *)dev; + int i, s; + + if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) + return; + + s = splimp(); + vge_miipoll_stop(sc); + + /* Specify the register we want to write. */ + CSR_WRITE_1(sc, VGE_MIIADDR, reg); + + /* Specify the data we want to write. */ + CSR_WRITE_2(sc, VGE_MIIDATA, data); + + /* Issue write command. */ + CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); + + /* Wait for the write command bit to self-clear. */ + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); + } + + vge_miipoll_start(sc); + splx(s); +} + +void +vge_cam_clear(struct vge_softc *sc) +{ + int i; + + /* + * Turn off all the mask bits. This tells the chip + * that none of the entries in the CAM filter are valid. + * desired entries will be enabled as we fill the filter in. + */ + + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); + CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); + for (i = 0; i < 8; i++) + CSR_WRITE_1(sc, VGE_CAM0 + i, 0); + + /* Clear the VLAN filter too. */ + + CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); + for (i = 0; i < 8; i++) + CSR_WRITE_1(sc, VGE_CAM0 + i, 0); + + CSR_WRITE_1(sc, VGE_CAMADDR, 0); + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); + + sc->vge_camidx = 0; +} + +int +vge_cam_set(struct vge_softc *sc, uint8_t *addr) +{ + int i, error = 0; + + if (sc->vge_camidx == VGE_CAM_MAXADDRS) + return(ENOSPC); + + /* Select the CAM data page. */ + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); + + /* Set the filter entry we want to update and enable writing. */ + CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); + + /* Write the address to the CAM registers */ + for (i = 0; i < ETHER_ADDR_LEN; i++) + CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); + + /* Issue a write command. */ + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); + + /* Wake for it to clear. */ + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(1); + if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); + error = EIO; + goto fail; + } + + /* Select the CAM mask page. */ + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); + + /* Set the mask bit that enables this filter. */ + CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), + 1<<(sc->vge_camidx & 7)); + + sc->vge_camidx++; + +fail: + /* Turn off access to CAM. */ + CSR_WRITE_1(sc, VGE_CAMADDR, 0); + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); + + return (error); +} + +/* + * Program the multicast filter. We use the 64-entry CAM filter + * for perfect filtering. If there's more than 64 multicast addresses, + * we use the hash filter instead. + */ +void +vge_setmulti(struct vge_softc *sc) +{ + struct arpcom *ac = &sc->arpcom; + struct ifnet *ifp = &ac->ac_if; + struct ether_multi *enm; + struct ether_multistep step; + u_int32_t h = 0, hashes[2] = { 0, 0 }; + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); + CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); + return; + } + /* reset existing hash bits */ + CSR_WRITE_4(sc, VGE_MAR0, 0); + CSR_WRITE_4(sc, VGE_MAR1, 0); + + /* program new ones */ + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) + ifp->if_flags |= IFF_ALLMULTI; + h = (ether_crc32_be(enm->enm_addrlo, + ETHER_ADDR_LEN) >> 26) & 0x0000003F; + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + ETHER_NEXT_MULTI(step, enm); + } + CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); + CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); + +#ifdef CAM_FILTERING + struct ifnet *ifp; + u_int32_t h, hashes[2] = { 0, 0 }; + int mcnt = 0; + struct arpcom *ac = &sc->arpcom; + struct ether_multi *enm; + struct ether_multistep step; + + ifp = &sc->arpcom.ac_if; + + /* First, zot all the multicast entries. */ + vge_cam_clear(sc); + CSR_WRITE_4(sc, VGE_MAR0, 0); + CSR_WRITE_4(sc, VGE_MAR1, 0); + + /* + * If the user wants allmulti or promisc mode, enable reception + * of all multicast frames. + */ + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); + CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); + return; + } + + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { + ifp->if_flags |= IFF_ALLMULTI; + mcnt = MAX_NUM_MULTICAST_ADDRESSES; + } + if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) + break; + + h = (ether_crc32_be(enm->enm_addrlo, + ETHER_ADDR_LEN) >> 26) & 0x0000003F; + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + mcnt++; + ETHER_NEXT_MULTI(step, enm); + } + + CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); + CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); +#endif +} + +void +vge_reset(struct vge_softc *sc) +{ + register int i; + + CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); + + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(5); + if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: soft reset timed out", sc->vge_dev.dv_xname); + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); + DELAY(2000); + } + + DELAY(5000); + + CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); + + for (i = 0; i < VGE_TIMEOUT; i++) { + DELAY(5); + if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) + break; + } + + if (i == VGE_TIMEOUT) { + printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); + return; + } + + CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); +} + +/* + * Probe for a VIA gigabit chip. Check the PCI vendor and device + * IDs against our list and return a device name if we find a match. + */ +int +vge_probe(struct device *dev, void *match, void *aux) +{ + return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, + sizeof(vge_devices)/sizeof(vge_devices[0]))); +} + +/* + * Allocate memory for RX/TX rings + */ +int +vge_allocmem(struct vge_softc *sc) +{ + int nseg, rseg; + int i, error; + + nseg = 32; + + /* Allocate DMA'able memory for the TX ring */ + + error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, + VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, + &sc->vge_ldata.vge_tx_list_map); + if (error) + return (ENOMEM); + error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, + ETHER_ALIGN, 0, + &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); + return (ENOMEM); + } + + /* Load the map for the TX ring. */ + error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, + 1, VGE_TX_LIST_SZ, + (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); + memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); + if (error) { + printf("%s: can't map TX dma buffers\n", + sc->vge_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); + return (ENOMEM); + } + + error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, + sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); + bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, + VGE_TX_LIST_SZ); + bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); + return (ENOMEM); + } + + /* Create DMA maps for TX buffers */ + + for (i = 0; i < VGE_TX_DESC_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, + MCLBYTES, 0, BUS_DMA_ALLOCNOW, + &sc->vge_ldata.vge_tx_dmamap[i]); + if (error) { + printf("%s: can't create DMA map for TX\n", + sc->vge_dev.dv_xname); + return (ENOMEM); + } + } + + /* Allocate DMA'able memory for the RX ring */ + + error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, + VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, + &sc->vge_ldata.vge_rx_list_map); + if (error) + return (ENOMEM); + error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, + 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); + return (ENOMEM); + } + + /* Load the map for the RX ring. */ + + error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, + 1, VGE_RX_LIST_SZ, + (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); + memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); + if (error) { + printf("%s: can't map RX dma buffers\n", + sc->vge_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); + return (ENOMEM); + } + error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, + sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); + bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, + VGE_RX_LIST_SZ); + bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); + return (ENOMEM); + } + + /* Create DMA maps for RX buffers */ + + for (i = 0; i < VGE_RX_DESC_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, + MCLBYTES, 0, BUS_DMA_ALLOCNOW, + &sc->vge_ldata.vge_rx_dmamap[i]); + if (error) { + printf("%s: can't create DMA map for RX\n", + sc->vge_dev.dv_xname); + return (ENOMEM); + } + } + + return (0); +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +void +vge_attach(struct device *parent, struct device *self, void *aux) +{ + u_char eaddr[ETHER_ADDR_LEN]; + struct vge_softc *sc = (struct vge_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr = NULL; + struct ifnet *ifp; + int error = 0; + bus_size_t iosize; + pcireg_t command; + + /* + * Map control/status registers. + */ + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | + PCI_COMMAND_MASTER_ENABLE; + pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + + if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) == 0) { + printf(": neither i/o nor mem enabled\n"); + return; + } + + if (command & PCI_COMMAND_MEM_ENABLE) { + if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, + &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { + printf(": can't map mem space\n"); + return; + } + } else { + if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, + &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { + printf(": can't map i/o space\n"); + return; + } + } + + /* Allocate interrupt */ + if (pci_intr_map(pa, &ih)) { + printf(": couldn't map interrupt\n"); + return; + } + intrstr = pci_intr_string(pc, ih); + sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, + sc->vge_dev.dv_xname); + if (sc->vge_intrhand == NULL) { + printf(": couldn't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + return; + } + printf(": %s", intrstr); + + sc->sc_dmat = pa->pa_dmat; + + /* Reset the adapter. */ + vge_reset(sc); + + /* + * Get station address from the EEPROM. + */ + vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); + + bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); + + printf(", address %s\n", + ether_sprintf(sc->arpcom.ac_enaddr)); + + error = vge_allocmem(sc); + + if (error) + return; + + ifp = &sc->arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = vge_ioctl; + ifp->if_start = vge_start; +#ifdef VGE_CSUM_OFFLOAD + ifp->if_capabilities = IFCAP_VLAN_MTU; + ifp->if_hwassist = VGE_CSUM_FEATURES; + ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; +#endif + ifp->if_watchdog = vge_watchdog; + ifp->if_init = vge_init; + ifp->if_baudrate = 1000000000; + IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); + IFQ_SET_READY(&ifp->if_snd); + + /* Set interface name */ + strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); + + /* Do MII setup */ + sc->sc_mii.mii_ifp = ifp; + sc->sc_mii.mii_readreg = vge_miibus_readreg; + sc->sc_mii.mii_writereg = vge_miibus_writereg; + sc->sc_mii.mii_statchg = vge_miibus_statchg; + ifmedia_init(&sc->sc_mii.mii_media, 0, + vge_ifmedia_upd, vge_ifmedia_sts); + mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, + MII_OFFSET_ANY, 0); + if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { + printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); + ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, + 0, NULL); + ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); + } else + ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); + + timeout_set(&sc->timer_handle, vge_tick, sc); + + /* + * Call MI attach routine. + */ + if_attach(ifp); + ether_ifattach(ifp); +} + +int +vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) +{ + struct mbuf *m_new = NULL; + struct vge_rx_desc *r; + bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; + int i; + + if (m == NULL) { + /* Allocate a new mbuf */ + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) + return (ENOBUFS); + + /* Allocate a cluster */ + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + return (ENOBUFS); + } + } else + m_new->m_data = m_new->m_ext.ext_buf; + + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + /* Fix-up alignment so payload is doubleword-aligned */ + /* XXX m_adj(m_new, ETHER_ALIGN); */ + + if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT)) + return (ENOBUFS); + + if (rxmap->dm_nsegs > 1) + goto out; + + /* Map the segments into RX descriptors */ + r = &sc->vge_ldata.vge_rx_list[idx]; + + if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { + printf("%s: tried to map a busy RX descriptor\n", + sc->vge_dev.dv_xname); + goto out; + } + r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); + r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); + r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); + r->vge_sts = 0; + r->vge_ctl = 0; + + /* + * Note: the manual fails to document the fact that for + * proper operation, the driver needs to replenish the RX + * DMA ring 4 descriptors at a time (rather than one at a + * time, like most chips). We can allocate the new buffers + * but we should not set the OWN bits until we're ready + * to hand back 4 of them in one shot. + */ +#define VGE_RXCHUNK 4 + sc->vge_rx_consumed++; + if (sc->vge_rx_consumed == VGE_RXCHUNK) { + for (i = idx; i != idx - sc->vge_rx_consumed; i--) + sc->vge_ldata.vge_rx_list[i].vge_sts |= + htole32(VGE_RDSTS_OWN); + sc->vge_rx_consumed = 0; + } + + sc->vge_ldata.vge_rx_mbuf[idx] = m_new; + + bus_dmamap_sync(sc->sc_dmat, rxmap, 0, + rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); + + return (0); +out: + DPRINTF(("vge_newbuf: out of memory\n")); + if (m_new != NULL) + m_freem(m_new); + return (ENOMEM); +} + +int +vge_tx_list_init(struct vge_softc *sc) +{ + bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); + bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, + (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_tx_list_map, 0, + sc->vge_ldata.vge_tx_list_map->dm_mapsize, + BUS_DMASYNC_PREWRITE); + sc->vge_ldata.vge_tx_prodidx = 0; + sc->vge_ldata.vge_tx_considx = 0; + sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; + + return (0); +} + +/* Init RX descriptors and allocate mbufs with vge_newbuf() + * A ring is used, and last descriptor points to first. */ +int +vge_rx_list_init(struct vge_softc *sc) +{ + int i; + + bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); + bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, + (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); + + sc->vge_rx_consumed = 0; + + for (i = 0; i < VGE_RX_DESC_CNT; i++) { + if (vge_newbuf(sc, i, NULL) == ENOBUFS) + return (ENOBUFS); + } + + /* Flush the RX descriptors */ + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_rx_list_map, + 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, + BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); + + sc->vge_ldata.vge_rx_prodidx = 0; + sc->vge_rx_consumed = 0; + sc->vge_head = sc->vge_tail = NULL; + + return (0); +} + +/* + * RX handler. We support the reception of jumbo frames that have + * been fragmented across multiple 2K mbuf cluster buffers. + */ +void +vge_rxeof(struct vge_softc *sc) +{ + struct mbuf *m; + struct ifnet *ifp; + int i, total_len; + int lim = 0; + struct vge_rx_desc *cur_rx; + u_int32_t rxstat, rxctl; + + ifp = &sc->arpcom.ac_if; + i = sc->vge_ldata.vge_rx_prodidx; + + /* Invalidate the descriptor memory */ + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_rx_list_map, + 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, + BUS_DMASYNC_POSTREAD); + + while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { + struct mbuf *m0 = NULL; + + cur_rx = &sc->vge_ldata.vge_rx_list[i]; + m = sc->vge_ldata.vge_rx_mbuf[i]; + total_len = VGE_RXBYTES(cur_rx); + rxstat = letoh32(cur_rx->vge_sts); + rxctl = letoh32(cur_rx->vge_ctl); + + /* Invalidate the RX mbuf and unload its map */ + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_rx_dmamap[i], + 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_dmat, + sc->vge_ldata.vge_rx_dmamap[i]); + + /* + * If the 'start of frame' bit is set, this indicates + * either the first fragment in a multi-fragment receive, + * or an intermediate fragment. Either way, we want to + * accumulate the buffers. + */ + if (rxstat & VGE_RXPKT_MOF || rxstat & VGE_RXPKT_EOF || + rxstat & VGE_RXPKT_ONEFRAG) + printf("vge_rxeof: bizzarre!\n"); + if (rxstat & VGE_RXPKT_SOF) { + DPRINTF(("vge_rxeof: SOF\n")); + m->m_len = MCLBYTES; + if (sc->vge_head == NULL) + sc->vge_head = sc->vge_tail = m; + else { + m->m_flags &= ~M_PKTHDR; + sc->vge_tail->m_next = m; + sc->vge_tail = m; + } + vge_newbuf(sc, i, NULL); + VGE_RX_DESC_INC(i); + continue; + } + + /* + * Bad/error frames will have the RXOK bit cleared. + * However, there's one error case we want to allow: + * if a VLAN tagged frame arrives and the chip can't + * match it against the CAM filter, it considers this + * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. + * We don't want to drop the frame though: our VLAN + * filtering is done in software. + */ + if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) + && !(rxstat & VGE_RDSTS_CSUMERR)) { + ifp->if_ierrors++; + /* + * If this is part of a multi-fragment packet, + * discard all the pieces. + */ + if (sc->vge_head != NULL) { + m_freem(sc->vge_head); + sc->vge_head = sc->vge_tail = NULL; + } + vge_newbuf(sc, i, m); + VGE_RX_DESC_INC(i); + continue; + } + + /* + * If allocating a replacement mbuf fails, + * reload the current one. + */ + + if (vge_newbuf(sc, i, NULL) == ENOBUFS) { + if (sc->vge_head != NULL) { + m_freem(sc->vge_head); + sc->vge_head = sc->vge_tail = NULL; + } + + m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, + total_len - ETHER_CRC_LEN + ETHER_ALIGN, + 0, ifp, NULL); + vge_newbuf(sc, i, m); + if (m0 == NULL) { + ifp->if_ierrors++; + continue; + } + m_adj(m0, ETHER_ALIGN); + m = m0; + + VGE_RX_DESC_INC(i); + continue; + } + + VGE_RX_DESC_INC(i); + + if (sc->vge_head != NULL) { + m->m_len = total_len % MCLBYTES; + /* + * Special case: if there's 4 bytes or less + * in this buffer, the mbuf can be discarded: + * the last 4 bytes is the CRC, which we don't + * care about anyway. + */ + if (m->m_len <= ETHER_CRC_LEN) { + sc->vge_tail->m_len -= + (ETHER_CRC_LEN - m->m_len); + m_freem(m); + } else { + m->m_len -= ETHER_CRC_LEN; + m->m_flags &= ~M_PKTHDR; + sc->vge_tail->m_next = m; + } + m = sc->vge_head; + sc->vge_head = sc->vge_tail = NULL; + m->m_pkthdr.len = total_len - ETHER_CRC_LEN; + } else + m->m_pkthdr.len = m->m_len = + (total_len - ETHER_CRC_LEN); + +#ifdef __STRICT_ALIGNMENT + bcopy(m->m_data, m->m_data + ETHER_ALIGN, + total_len); + m->m_data += ETHER_ALIGN; +#endif + ifp->if_ipackets++; + m->m_pkthdr.rcvif = ifp; + + /* Do RX checksumming if enabled */ +#ifdef VGE_CSUM_OFFLOAD + if (ifp->if_capenable & IFCAP_RXCSUM) { + + /* Check IP header checksum */ + if (rxctl & VGE_RDCTL_IPPKT) + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if (rxctl & VGE_RDCTL_IPCSUMOK) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + + /* Check TCP/UDP checksum */ + if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && + rxctl & VGE_RDCTL_PROTOCSUMOK) { + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID|CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + + if (rxstat & VGE_RDSTS_VTAG) + VLAN_INPUT_TAG(ifp, m, + ntohs((rxctl & VGE_RDCTL_VLANID)), continue); +#endif + +#if NBPFILTER > 0 + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + ether_input_mbuf(ifp, m); + + lim++; + if (lim == VGE_RX_DESC_CNT) + break; + + } + + /* Flush the RX DMA ring */ + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_rx_list_map, + 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, + BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); + + sc->vge_ldata.vge_rx_prodidx = i; + CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); +} + +void +vge_txeof(struct vge_softc *sc) +{ + struct ifnet *ifp; + u_int32_t txstat; + int idx; + + ifp = &sc->arpcom.ac_if; + idx = sc->vge_ldata.vge_tx_considx; + + /* Invalidate the TX descriptor list */ + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_tx_list_map, + 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, + BUS_DMASYNC_POSTREAD); + + /* Transmitted frames can be now free'd from the TX list */ + while (idx != sc->vge_ldata.vge_tx_prodidx) { + txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); + if (txstat & VGE_TDSTS_OWN) + break; + + m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); + sc->vge_ldata.vge_tx_mbuf[idx] = NULL; + bus_dmamap_unload(sc->sc_dmat, + sc->vge_ldata.vge_tx_dmamap[idx]); + if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) + ifp->if_collisions++; + if (txstat & VGE_TDSTS_TXERR) + ifp->if_oerrors++; + else + ifp->if_opackets++; + + sc->vge_ldata.vge_tx_free++; + VGE_TX_DESC_INC(idx); + } + + /* No changes made to the TX ring, so no flush needed */ + + if (idx != sc->vge_ldata.vge_tx_considx) { + sc->vge_ldata.vge_tx_considx = idx; + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_timer = 0; + } + + /* + * If not all descriptors have been released reaped yet, + * reload the timer so that we will eventually get another + * interrupt that will cause us to re-enter this routine. + * This is done in case the transmitter has gone idle. + */ + if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) + CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); +} + +void +vge_tick(void *xsc) +{ + struct vge_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mii_data *mii = &sc->sc_mii; + int s; + + s = splimp(); + + mii_tick(mii); + + if (sc->vge_link) { + if (!(mii->mii_media_status & IFM_ACTIVE)) + sc->vge_link = 0; + } else { + if (mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->vge_link = 1; + if (!IFQ_IS_EMPTY(&ifp->if_snd)) + vge_start(ifp); + } + } + timeout_add(&sc->timer_handle, hz); + splx(s); +} + +int +vge_intr(void *arg) +{ + struct vge_softc *sc = arg; + struct ifnet *ifp; + u_int32_t status; + int claimed = 0; + + ifp = &sc->arpcom.ac_if; + + if (!(ifp->if_flags & IFF_UP)) + return 0; + + /* Disable interrupts */ + CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); + + for (;;) { + status = CSR_READ_4(sc, VGE_ISR); + DPRINTFN(3, ("vge_intr: status=%#x\n", status)); + + /* If the card has gone away the read returns 0xffffffff. */ + if (status == 0xFFFFFFFF) + break; + + if (status) { + CSR_WRITE_4(sc, VGE_ISR, status); + } + + if ((status & VGE_INTRS) == 0) + break; + + claimed = 1; + + if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) + vge_rxeof(sc); + + if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { + DPRINTFN(2, ("vge_intr: RX error, recovering\n")); + vge_rxeof(sc); + CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); + CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); + } + + if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) + vge_txeof(sc); + + if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { + DPRINTFN(2, ("DMA_STALL\n")); + vge_init(ifp); + } + + if (status & VGE_ISR_LINKSTS) { + timeout_del(&sc->timer_handle); + vge_tick(sc); + } + } + + /* Re-enable interrupts */ + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); + + if (!IFQ_IS_EMPTY(&ifp->if_snd)) + vge_start(ifp); + + return (claimed); +} + +/* + * Encapsulate an mbuf chain into the TX ring by combining it w/ + * the descriptors. + */ +int +vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) +{ + bus_dmamap_t txmap; + struct vge_tx_desc *d = NULL; + struct vge_tx_frag *f; + int error, frag; + + txmap = sc->vge_ldata.vge_tx_dmamap[idx]; +repack: + error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, + m_head, BUS_DMA_NOWAIT); + if (error) { + printf("%s: can't map mbuf (error %d)\n", + sc->vge_dev.dv_xname, error); + return (ENOBUFS); + } + + d = &sc->vge_ldata.vge_tx_list[idx]; + /* If owned by chip, fail */ + if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) + return (ENOBUFS); + + for (frag = 0; frag < txmap->dm_nsegs; frag++) { + /* Check if we have used all 7 fragments. */ + if (frag == VGE_TX_FRAGS) + break; + f = &d->vge_frag[frag]; + f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); + f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); + f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); + } + + /* + * We used up all 7 fragments! Now what we have to do is + * copy the data into a mbuf cluster and map that. + */ + if (frag == VGE_TX_FRAGS) { + struct mbuf *m = NULL; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + m_freem(m_head); + return (ENOBUFS); + } + if (m_head->m_pkthdr.len > MHLEN) { + MCLGET(m, M_DONTWAIT); + if (!(m->m_flags & M_EXT)) { + m_freem(m); + m_freem(m_head); + return (ENOBUFS); + } + } + m_copydata(m_head, 0, m_head->m_pkthdr.len, + mtod(m, caddr_t)); + m->m_pkthdr.len = m->m_len = m_head->m_pkthdr.len; + m_freem(m_head); + m_head = m; + goto repack; + } + + /* This chip does not do auto-padding */ + if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { + f = &d->vge_frag[frag]; + + f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - + m_head->m_pkthdr.len)); + f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); + f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); + m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; + frag++; + } + /* For some reason, we need to tell the card fragment + 1 */ + frag++; + + bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, + BUS_DMASYNC_PREWRITE); + + d->vge_sts = m_head->m_pkthdr.len << 16; + d->vge_ctl = (frag << 28) | VGE_TD_LS_NORM; + + if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) + d->vge_ctl |= VGE_TDCTL_JUMBO; + + sc->vge_ldata.vge_tx_dmamap[idx] = txmap; + sc->vge_ldata.vge_tx_mbuf[idx] = m_head; + sc->vge_ldata.vge_tx_free--; + sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); + + /* + * Set up hardware VLAN tagging. + */ +#ifdef VGE_VLAN + mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); + if (mtag != NULL) + sc->vge_ldata.vge_tx_list[idx].vge_ctl |= + htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); +#endif + + idx++; + + return (0); +} + +/* + * Main transmit routine. + */ +void +vge_start(struct ifnet *ifp) +{ + struct vge_softc *sc; + struct mbuf *m_head = NULL; + int idx, pidx = 0; + + sc = ifp->if_softc; + + if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) + return; + + if (IFQ_IS_EMPTY(&ifp->if_snd)) + return; + + idx = sc->vge_ldata.vge_tx_prodidx; + + pidx = idx - 1; + if (pidx < 0) + pidx = VGE_TX_DESC_CNT - 1; + + while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { + IF_DEQUEUE(&ifp->if_snd, m_head); + + if (m_head == NULL) + break; + + if (vge_encap(sc, m_head, idx)) { + IF_PREPEND(&ifp->if_snd, m_head); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= + htole16(VGE_TXDESC_Q); + + pidx = idx; + VGE_TX_DESC_INC(idx); + + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ +#if NBPFILTER > 0 + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m_head); +#endif + } + + if (idx == sc->vge_ldata.vge_tx_prodidx) { + return; + } + + /* Flush the TX descriptors */ + + bus_dmamap_sync(sc->sc_dmat, + sc->vge_ldata.vge_tx_list_map, + 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, + BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); + + /* Issue a transmit command. */ + CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); + + sc->vge_ldata.vge_tx_prodidx = idx; + + /* + * Use the countdown timer for interrupt moderation. + * 'TX done' interrupts are disabled. Instead, we reset the + * countdown timer, which will begin counting until it hits + * the value in the SSTIMER register, and then trigger an + * interrupt. Each time we set the TIMER0_ENABLE bit, the + * the timer count is reloaded. Only when the transmitter + * is idle will the timer hit 0 and an interrupt fire. + */ + CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + ifp->if_timer = 5; +} + +int +vge_init(struct ifnet *ifp) +{ + struct vge_softc *sc = ifp->if_softc; + int i; + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + vge_stop(sc); + vge_reset(sc); + + /* Initialize RX descriptors list */ + if (vge_rx_list_init(sc) == ENOBUFS) { + printf("%s: init failed: no memory for RX buffers\n", + sc->vge_dev.dv_xname); + vge_stop(sc); + return (ENOBUFS); + } + /* Initialize TX descriptors */ + if (vge_tx_list_init(sc) == ENOBUFS) { + printf("%s: init failed: no memory for TX buffers\n", + sc->vge_dev.dv_xname); + vge_stop(sc); + return (ENOBUFS); + } + + /* Set our station address */ + for (i = 0; i < ETHER_ADDR_LEN; i++) + CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); + + /* + * Set receive FIFO threshold. Also allow transmission and + * reception of VLAN tagged frames. + */ + CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); + CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); + + /* Set DMA burst length */ + CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); + CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); + + CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); + + /* Set collision backoff algorithm */ + CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| + VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); + CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); + + /* Disable LPSEL field in priority resolution */ + CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); + + /* + * Load the addresses of the DMA queues into the chip. + * Note that we only use one transmit queue. + */ + + CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, + VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); + CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); + + CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, + VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); + CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); + CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); + + /* Enable and wake up the RX descriptor queue */ + CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); + CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); + + /* Enable the TX descriptor queue */ + CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); + + /* Set up the receive filter -- allow large frames for VLANs. */ + CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) { + CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); + } + + /* Set capture broadcast bit to capture broadcast frames. */ + if (ifp->if_flags & IFF_BROADCAST) { + CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); + } + + /* Set multicast bit to capture multicast frames. */ + if (ifp->if_flags & IFF_MULTICAST) { + CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); + } + + /* Init the cam filter. */ +#ifdef CAM_FILTERING + vge_cam_clear(sc); +#endif + + /* Init the multicast filter. */ + vge_setmulti(sc); + + /* Enable flow control */ + + CSR_WRITE_1(sc, VGE_CRS2, 0x8B); + + /* Enable jumbo frame reception (if desired) */ + + /* Start the MAC. */ + CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); + CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); + CSR_WRITE_1(sc, VGE_CRS0, + VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); + + /* + * Configure one-shot timer for microsecond + * resulution and load it for 500 usecs. + */ + CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); + CSR_WRITE_2(sc, VGE_SSTIMER, 400); + + /* + * Configure interrupt moderation for receive. Enable + * the holdoff counter and load it, and set the RX + * suppression count to the number of descriptors we + * want to allow before triggering an interrupt. + * The holdoff timer is in units of 20 usecs. + */ + +#ifdef notyet + CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); + /* Select the interrupt holdoff timer page. */ + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); + CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ + + /* Enable use of the holdoff timer. */ + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); + CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); + + /* Select the RX suppression threshold page. */ + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); + CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ + + /* Restore the page select bits. */ + CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); + CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); +#endif + + /* + * Enable interrupts. + */ + CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); + CSR_WRITE_4(sc, VGE_ISR, 0); + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); + + /* Restore BMCR state */ + mii_mediachg(&sc->sc_mii); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + sc->vge_if_flags = 0; + sc->vge_link = 0; + + if (!timeout_pending(&sc->timer_handle)) + timeout_add(&sc->timer_handle, hz); + + return (0); +} + +/* + * Set media options. + */ +int +vge_ifmedia_upd(struct ifnet *ifp) +{ + struct vge_softc *sc = ifp->if_softc; + + return (mii_mediachg(&sc->sc_mii)); +} + +/* + * Report current media status. + */ +void +vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct vge_softc *sc = ifp->if_softc; + + mii_pollstat(&sc->sc_mii); + ifmr->ifm_active = sc->sc_mii.mii_media_active; + ifmr->ifm_status = sc->sc_mii.mii_media_status; +} + +void +vge_miibus_statchg(struct device *dev) +{ + struct vge_softc *sc = (struct vge_softc *)dev; + struct mii_data *mii; + struct ifmedia_entry *ife; + + mii = &sc->sc_mii; + ife = mii->mii_media.ifm_cur; + + /* + * If the user manually selects a media mode, we need to turn + * on the forced MAC mode bit in the DIAGCTL register. If the + * user happens to choose a full duplex mode, we also need to + * set the 'force full duplex' bit. This applies only to + * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC + * mode is disabled, and in 1000baseT mode, full duplex is + * always implied, so we turn on the forced mode bit but leave + * the FDX bit cleared. + */ + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); + CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); + break; + case IFM_1000_T: + CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); + CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); + break; + case IFM_100_TX: + case IFM_10_T: + CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { + CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); + } else { + CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); + } + break; + default: + printf("%s: unknown media type: %x\n", + sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); + break; + } +} + +int +vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct vge_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct ifaddr *ifa = (struct ifaddr *) data; + int s, error = 0; + + s = splimp(); + + if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { + splx(s); + return (error); + } + + switch (command) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + switch (ifa->ifa_addr->sa_family) { +#ifdef INET + case AF_INET: + vge_init(ifp); + arp_ifinit(&sc->arpcom, ifa); + break; +#endif + default: + vge_init(ifp); + break; + } +#if 0 /* XXX mtu gets reset to 0 at ifconfig up for some reason with this */ + case SIOCSIFMTU: + if (ifr->ifr_mtu > ETHERMTU_JUMBO) + error = EINVAL; + else + ifp->if_mtu = ifr->ifr_mtu; + break; +#endif + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING && + ifp->if_flags & IFF_PROMISC && + !(sc->vge_if_flags & IFF_PROMISC)) { + CSR_SETBIT_1(sc, VGE_RXCTL, + VGE_RXCTL_RX_PROMISC); + vge_setmulti(sc); + } else if (ifp->if_flags & IFF_RUNNING && + !(ifp->if_flags & IFF_PROMISC) && + sc->vge_if_flags & IFF_PROMISC) { + CSR_CLRBIT_1(sc, VGE_RXCTL, + VGE_RXCTL_RX_PROMISC); + vge_setmulti(sc); + } else + vge_init(ifp); + } else { + if (ifp->if_flags & IFF_RUNNING) + vge_stop(sc); + } + sc->vge_if_flags = ifp->if_flags; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + error = (command == SIOCADDMULTI) ? + ether_addmulti(ifr, &sc->arpcom) : + ether_delmulti(ifr, &sc->arpcom); + if (error == ENETRESET) { + vge_setmulti(sc); + error = 0; + } + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); + break; + default: + error = EINVAL; + break; + } + + splx(s); + return (error); +} + +void +vge_watchdog(struct ifnet *ifp) +{ + struct vge_softc *sc = ifp->if_softc; + int s; + + s = splnet(); + printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); + ifp->if_oerrors++; + + vge_txeof(sc); + vge_rxeof(sc); + + vge_init(ifp); + + splx(s); +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +void +vge_stop(struct vge_softc *sc) +{ + register int i; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + ifp->if_timer = 0; + if (timeout_pending(&sc->timer_handle)) + timeout_del(&sc->timer_handle); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); + CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); + CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); + CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); + CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); + CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); + + if (sc->vge_head != NULL) { + m_freem(sc->vge_head); + sc->vge_head = sc->vge_tail = NULL; + } + + /* Free the TX list buffers. */ + for (i = 0; i < VGE_TX_DESC_CNT; i++) { + if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { + bus_dmamap_unload(sc->sc_dmat, + sc->vge_ldata.vge_tx_dmamap[i]); + m_freem(sc->vge_ldata.vge_tx_mbuf[i]); + sc->vge_ldata.vge_tx_mbuf[i] = NULL; + } + } + + /* Free the RX list buffers. */ + for (i = 0; i < VGE_RX_DESC_CNT; i++) { + if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { + bus_dmamap_unload(sc->sc_dmat, + sc->vge_ldata.vge_rx_dmamap[i]); + m_freem(sc->vge_ldata.vge_rx_mbuf[i]); + sc->vge_ldata.vge_rx_mbuf[i] = NULL; + } + } +} diff --git a/sys/dev/pci/if_vgereg.h b/sys/dev/pci/if_vgereg.h new file mode 100644 index 00000000000..34c26f5f4bb --- /dev/null +++ b/sys/dev/pci/if_vgereg.h @@ -0,0 +1,697 @@ +/* $OpenBSD: if_vgereg.h,v 1.1 2004/12/01 01:29:00 pvalchev Exp $ */ +/* $FreeBSD: if_vgereg.h,v 1.1 2004/09/10 20:57:45 wpaul Exp $ */ +/* + * Copyright (c) 2004 + * Bill Paul <wpaul@windriver.com>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Register definitions for the VIA VT6122 gigabit ethernet controller. + * Definitions for the built-in copper PHY can be found in vgphy.h. + * + * The VT612x controllers have 256 bytes of register space. The + * manual seems to imply that the registers should all be accessed + * using 32-bit I/O cycles, but some of them are less than 32 bits + * wide. Go figure. + */ + +#ifndef _IF_VGEREG_H_ +#define _IF_VGEREG_H_ + +#define VIA_VENDORID 0x1106 +#define VIA_DEVICEID_61XX 0x3119 + +#define VGE_PAR0 0x00 /* physical address register */ +#define VGE_PAR1 0x02 +#define VGE_PAR2 0x04 +#define VGE_RXCTL 0x06 /* RX control register */ +#define VGE_TXCTL 0x07 /* TX control register */ +#define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ +#define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ +#define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ +#define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ +#define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ +#define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ +#define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ +#define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ +#define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ +#define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ +#define VGE_CAM0 0x10 +#define VGE_CAM1 0x11 +#define VGE_CAM2 0x12 +#define VGE_CAM3 0x13 +#define VGE_CAM4 0x14 +#define VGE_CAM5 0x15 +#define VGE_CAM6 0x16 +#define VGE_CAM7 0x17 +#define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ +#define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */ +#define VGE_INTCTL0 0x20 /* interrupt control register */ +#define VGE_RXSUPPTHR 0x20 +#define VGE_TXSUPPTHR 0x20 +#define VGE_INTHOLDOFF 0x20 +#define VGE_INTCTL1 0x21 /* interrupt control register */ +#define VGE_TXHOSTERR 0x22 /* TX host error status */ +#define VGE_RXHOSTERR 0x23 /* RX host error status */ +#define VGE_ISR 0x24 /* Interrupt status register */ +#define VGE_IMR 0x28 /* Interrupt mask register */ +#define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ +#define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ +#define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ +#define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ +#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ +#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ +#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ +#define VGE_RXQTIMER 0x3E /* RX queue timer pend register */ +#define VGE_TXQTIMER 0x3F /* TX queue timer pend register */ +#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ +#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ +#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ +#define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ +#define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ +#define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ +#define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ +#define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ +#define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ +#define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ +#define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ +#define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ +#define VGE_FIFOTEST0 0x60 /* FIFO test register */ +#define VGE_FIFOTEST1 0x64 /* FIFO test register */ +#define VGE_CAMADDR 0x68 /* CAM address register */ +#define VGE_CAMCTL 0x69 /* CAM control register */ +#define VGE_GFTEST 0x6A +#define VGE_FTSCMD 0x6B +#define VGE_MIICFG 0x6C /* MII port config register */ +#define VGE_MIISTS 0x6D /* MII port status register */ +#define VGE_PHYSTS0 0x6E /* PHY status register */ +#define VGE_PHYSTS1 0x6F /* PHY status register */ +#define VGE_MIICMD 0x70 /* MII command register */ +#define VGE_MIIADDR 0x71 /* MII address register */ +#define VGE_MIIDATA 0x72 /* MII data register */ +#define VGE_SSTIMER 0x74 /* single-shot timer */ +#define VGE_PTIMER 0x76 /* periodic timer */ +#define VGE_CHIPCFG0 0x78 /* chip config A */ +#define VGE_CHIPCFG1 0x79 /* chip config B */ +#define VGE_CHIPCFG2 0x7A /* chip config C */ +#define VGE_CHIPCFG3 0x7B /* chip config D */ +#define VGE_DMACFG0 0x7C /* DMA config 0 */ +#define VGE_DMACFG1 0x7D /* DMA config 1 */ +#define VGE_RXCFG 0x7E /* MAC RX config */ +#define VGE_TXCFG 0x7F /* MAC TX config */ +#define VGE_PWRMGMT 0x82 /* power management shadow register */ +#define VGE_PWRSTAT 0x83 /* power state shadow register */ +#define VGE_MIBCSR 0x84 /* MIB control/status register */ +#define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ +#define VGE_MIBDATA 0x88 /* MIB data register */ +#define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ +#define VGE_EECSUM 0x92 /* EEPROM checksum */ +#define VGE_EECSR 0x93 /* EEPROM control/status */ +#define VGE_EERDDAT 0x94 /* EEPROM embedded read */ +#define VGE_EEADDR 0x96 /* EEPROM address */ +#define VGE_EECMD 0x97 /* EEPROM embedded command */ +#define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ +#define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ +#define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ +#define VGE_DBGCTL 0x9E /* Chip debug control */ +#define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ +#define VGE_WOLCR0S 0xA0 /* WOL0 event set */ +#define VGE_WOLCR1S 0xA1 /* WOL1 event set */ +#define VGE_PWRCFGS 0xA2 /* Power management config set */ +#define VGE_WOLCFGS 0xA3 /* WOL config set */ +#define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ +#define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ +#define VGE_PWRCFGC 0xA6 /* Power management config clear */ +#define VGE_WOLCFGC 0xA7 /* WOL config clear */ +#define VGE_WOLSR0S 0xA8 /* WOL status set */ +#define VGE_WOLSR1S 0xA9 /* WOL status set */ +#define VGE_WOLSR0C 0xAC /* WOL status clear */ +#define VGE_WOLSR1C 0xAD /* WOL status clear */ +#define VGE_WAKEPAT_CRC0 0xB0 +#define VGE_WAKEPAT_CRC1 0xB2 +#define VGE_WAKEPAT_CRC2 0xB4 +#define VGE_WAKEPAT_CRC3 0xB6 +#define VGE_WAKEPAT_CRC4 0xB8 +#define VGE_WAKEPAT_CRC5 0xBA +#define VGE_WAKEPAT_CRC6 0xBC +#define VGE_WAKEPAT_CRC7 0xBE +#define VGE_WAKEPAT_MSK0_0 0xC0 +#define VGE_WAKEPAT_MSK0_1 0xC4 +#define VGE_WAKEPAT_MSK0_2 0xC8 +#define VGE_WAKEPAT_MSK0_3 0xCC +#define VGE_WAKEPAT_MSK1_0 0xD0 +#define VGE_WAKEPAT_MSK1_1 0xD4 +#define VGE_WAKEPAT_MSK1_2 0xD8 +#define VGE_WAKEPAT_MSK1_3 0xDC +#define VGE_WAKEPAT_MSK2_0 0xE0 +#define VGE_WAKEPAT_MSK2_1 0xE4 +#define VGE_WAKEPAT_MSK2_2 0xE8 +#define VGE_WAKEPAT_MSK2_3 0xEC +#define VGE_WAKEPAT_MSK3_0 0xF0 +#define VGE_WAKEPAT_MSK3_1 0xF4 +#define VGE_WAKEPAT_MSK3_2 0xF8 +#define VGE_WAKEPAT_MSK3_3 0xFC + +/* Receive control register */ + +#define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ +#define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ +#define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ +#define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ +#define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ +#define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ +#define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ +#define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ + +/* Transmit control register */ + +#define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ +#define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ + +#define VGE_TXLOOPCTL_OFF 0x00 +#define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 +#define VGE_TXLOOPCTL_EXTERNAL 0x02 + +#define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ +#define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ +#define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ +#define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ + +/* Global command register 0 */ + +#define VGE_CR0_START 0x01 /* start NIC */ +#define VGE_CR0_STOP 0x02 /* stop NIC */ +#define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ +#define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ + +/* Global command register 1 */ + +#define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ +#define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ +#define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ +#define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ +#define VGE_CR1_SOFTRESET 0x80 /* software reset */ + +/* Global command register 2 */ + +#define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ +#define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ +#define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ +#define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ +#define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ +#define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ + +/* Global command register 3 */ + +#define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ +#define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ +#define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ +#define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ +#define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ +#define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ + +/* Interrupt control register */ + +#define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ +#define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ +#define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ +#define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ +#define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ +#define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ +#define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ + +#define VGE_INTMASK_LAYER0 0x00 +#define VGE_INTMASK_LAYER1 0x08 +#define VGE_INTMASK_ALL 0x10 +#define VGE_INTMASK_ALL2 0x18 + +/* Transmit host error status register */ + +#define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ +#define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ +#define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ +#define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ + +/* Receive host error status register */ + +#define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ +#define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ +#define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ +#define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ + +/* Interrupt status register */ + +#define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ +#define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ +#define VGE_ISR_RXOK 0x00000004 /* normal RX done */ +#define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ +#define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ +#define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ +#define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ +#define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ +#define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ +#define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ +#define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ +#define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ +#define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ +#define VGE_ISR_LINKSTS 0x00008000 /* link status change */ +#define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ +#define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ +#define VGE_ISR_PWR 0x00040000 /* wake up power event */ +#define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ +#define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ +#define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ +#define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ +#define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ +#define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ +#define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ +#define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ +#define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ +#define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ +#define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ + +#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ + VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ + VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ + VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \ + VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0) + +/* Interrupt mask register */ + +#define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ +#define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ +#define VGE_IMR_RXOK 0x00000004 /* normal RX done */ +#define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ +#define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ +#define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ +#define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ +#define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ +#define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ +#define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ +#define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ +#define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ +#define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ +#define VGE_IMR_LINKSTS 0x00008000 /* link status change */ +#define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ +#define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ +#define VGE_IMR_PWR 0x00040000 /* wake up power event */ +#define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ +#define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ +#define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ +#define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ +#define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ +#define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ +#define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ +#define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ +#define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ +#define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ +#define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ + +/* TX descriptor queue control/status register */ + +#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ +#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ +#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ +#define VGE_TXQCST_DEAD0 0x0008 /* queue 0 dead indicator */ +#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ +#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ +#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ +#define VGE_TXQCST_DEAD1 0x0080 /* queue 1 dead indicator */ +#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ +#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ +#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ +#define VGE_TXQCST_DEAD2 0x0800 /* queue 2 dead indicator */ +#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ +#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ +#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ +#define VGE_TXQCST_DEAD3 0x8000 /* queue 3 dead indicator */ + +/* RX descriptor queue control/status register */ + +#define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ +#define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ +#define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ +#define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ + +/* RX/TX queue empty interrupt delay timer register */ + +#define VGE_QTIMER_PENDCNT 0x3F +#define VGE_QTIMER_RESOLUTION 0xC0 + +#define VGE_QTIMER_RES_1US 0x00 +#define VGE_QTIMER_RES_4US 0x40 +#define VGE_QTIMER_RES_16US 0x80 +#define VGE_QTIMER_RES_64US 0xC0 + +/* CAM address register */ + +#define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ +#define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ +#define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ + +#define VGE_CAM_MAXADDRS 64 + +/* + * CAM command register + * Note that the page select bits in this register affect three + * different things: + * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the + * page select bits control whether the MAR0/MAR1 registers affect + * the multicast hash filter or the CAM table) + * - The behavior of the interrupt holdoff timer register at offset + * 0x20 (the page select bits allow you to set the interrupt + * holdoff timer, the TX interrupt supression count or the + * RX interrupt supression count) + * - The behavior the WOL pattern programming registers at offset + * 0xC0 (controls which pattern is set) + */ + + +#define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ +#define VGE_CAMCTL_READ 0x08 /* CAM read command */ +#define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ +#define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ +#define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ + +#define VGE_PAGESEL_MAR 0x00 +#define VGE_PAGESEL_CAMMASK 0x40 +#define VGE_PAGESEL_CAMDATA 0x80 + +#define VGE_PAGESEL_INTHLDOFF 0x00 +#define VGE_PAGESEL_TXSUPPTHR 0x40 +#define VGE_PAGESEL_RXSUPPTHR 0x80 + +#define VGE_PAGESEL_WOLPAT0 0x00 +#define VGE_PAGESEL_WOLPAT1 0x40 + +/* MII port config register */ + +#define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ +#define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ +#define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ + +#define VGE_MIIPOLLINT_1024 0x00 +#define VGE_MIIPOLLINT_512 0x40 +#define VGE_MIIPOLLINT_128 0x80 +#define VGE_MIIPOLLINT_64 0xC0 + +/* MII port status register */ + +#define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ + +/* PHY status register */ + +#define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ +#define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ +#define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ +#define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ +#define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ +#define VGE_PHYSTS_LINK 0x40 /* link status */ +#define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ + +/* MII management command register */ + +#define VGE_MIICMD_MDC 0x01 /* clock pin */ +#define VGE_MIICMD_MDI 0x02 /* data in pin */ +#define VGE_MIICMD_MDO 0x04 /* data out pin */ +#define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ +#define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ +#define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ +#define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ +#define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ + +/* MII address register */ + +#define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ + +/* Chip config register A */ + +#define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ +#define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ +#define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ +#define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ +#define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ + +/* Chip config register B */ +/* Note: some of these bits are not documented in the manual! */ + +#define VGE_CHIPCFG1_BAKOPT 0x01 +#define VGE_CHIPCFG1_MBA 0x02 +#define VGE_CHIPCFG1_CAP 0x04 +#define VGE_CHIPCFG1_CRANDOM 0x08 +#define VGE_CHIPCFG1_OFSET 0x10 +#define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ +#define VGE_CHIPCFG1_MIIOPT 0x40 +#define VGE_CHIPCFG1_GTCKOPT 0x80 + +/* Chip config register C */ + +#define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ + +/* Chip config register D */ + +#define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ +#define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ + +/* DMA config register 0 */ + +#define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ + +#define VGE_DMABURST_8 0x00 +#define VGE_DMABURST_16 0x01 +#define VGE_DMABURST_32 0x02 +#define VGE_DMABURST_64 0x03 +#define VGE_DMABURST_128 0x04 +#define VGE_DMABURST_256 0x05 +#define VGE_DMABURST_STRFWD 0x07 + +/* DMA config register 1 */ + +#define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ +#define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ +#define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ +#define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ +#define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ +#define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ + +/* RX MAC config register */ + +#define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ +#define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ +#define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ +#define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ +#define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ + +#define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion + RX: rx all, no tag extraction */ + +#define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion + RX: rx only tagged pkts, no + extraction */ + +#define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, + RX: rx all, extract tags */ + +#define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, + RX: rx only tagged pkts, + with extraction */ + +#define VGE_RXFIFOTHR_128BYTES 0x00 +#define VGE_RXFIFOTHR_512BYTES 0x10 +#define VGE_RXFIFOTHR_1024BYTES 0x20 +#define VGE_RXFIFOTHR_STRNFWD 0x30 + +/* TX MAC config register */ + +#define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at + 13th byte + 0 == insert VLANM tag after + SNAP header (21st byte) */ +#define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ +#define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ +#define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ + +#define VGE_TXBLOCK_64PKTS 0x00 +#define VGE_TXBLOCK_32PKTS 0x04 +#define VGE_TXBLOCK_128PKTS 0x08 +#define VGE_TXBLOCK_8PKTS 0x0C + +/* EEPROM control/status register */ + +#define VGE_EECSR_EDO 0x01 /* data out pin */ +#define VGE_EECSR_EDI 0x02 /* data in pin */ +#define VGE_EECSR_ECK 0x04 /* clock pin */ +#define VGE_EECSR_ECS 0x08 /* chip select pin */ +#define VGE_EECSR_DPM 0x10 /* direct program mode enable */ +#define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ +#define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ + +/* EEPROM embedded command register */ + +#define VGE_EECMD_ERD 0x01 /* EEPROM read command */ +#define VGE_EECMD_EWR 0x02 /* EEPROM write command */ +#define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ +#define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ +#define VGE_EECMD_EDONE 0x80 /* read/write done */ + +/* Chip operation and diagnostic control register */ + +#define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ +#define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ +#define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ +#define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ +#define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ +#define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ +#define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ +#define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ + +/* Location of station address in EEPROM */ +#define VGE_EE_EADDR 0 + +/* DMA descriptor structures */ + +/* + * Each TX DMA descriptor has a control and status word, and 7 + * fragment address/length words. If a transmitted packet spans + * more than 7 fragments, it has to be coalesced. + */ + +#define VGE_TX_FRAGS 7 + +struct vge_tx_frag { + uint32_t vge_addrlo; + uint16_t vge_addrhi; + uint16_t vge_buflen; +}; + +/* + * The high bit in the buflen field of fragment #0 has special meaning. + * Normally, the chip requires the driver to issue a TX poll command + * for every packet that gets put in the TX DMA queue. Sometimes though, + * the driver might want to queue up several packets at once and just + * issue one transmit command to have all of them processed. In order + * to obtain this behavior, the special 'queue' bit must be set. + */ + +#define VGE_TXDESC_Q 0x8000 + +struct vge_tx_desc { + uint32_t vge_sts; + uint32_t vge_ctl; + struct vge_tx_frag vge_frag[VGE_TX_FRAGS]; +}; + +#define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ +#define VGE_TDSTS_COLL 0x00000010 /* collision seen */ +#define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ +#define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ +#define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ +#define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ +#define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ +#define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ +#define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ +#define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ +#define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ +#define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ +#define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ +#define VGE_TDSTS_OWN 0x80000000 /* own bit */ + +#define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ +#define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ +#define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ +#define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ +#define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ +#define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ +#define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ +#define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ +#define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ +#define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ +#define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ +#define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ +#define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ + +#define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ +#define VGE_TD_LS_SOF 0x01000000 /* start of large send */ +#define VGE_TD_LS_EOF 0x02000000 /* end of large send */ +#define VGE_TD_LS_NORM 0x03000000 /* normal frame */ + +/* Receive DMA descriptors have a single fragment pointer. */ + +struct vge_rx_desc { + volatile uint32_t vge_sts; + volatile uint32_t vge_ctl; + volatile uint32_t vge_addrlo; + volatile uint16_t vge_addrhi; + volatile uint16_t vge_buflen; +}; + +/* + * Like the TX descriptor, the high bit in the buflen field in the + * RX descriptor has special meaning. This bit controls whether or + * not interrupts are generated for this descriptor. + */ + +#define VGE_RXDESC_I 0x8000 + +#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ +#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ +#define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ +#define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ +#define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ +#define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ +#define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ +#define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ +#define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ +#define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ +#define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ +#define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ +#define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ +#define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ +#define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ +#define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ +#define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ +#define VGE_RDSTS_OWN 0x80000000 /* own bit. */ + +#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ +#define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */ +#define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */ +#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ + +#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ +#define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ +#define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ +#define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ +#define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ +#define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ +#define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ +#define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ +#define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ + +#endif /* _IF_VGEREG_H_ */ diff --git a/sys/dev/pci/if_vgevar.h b/sys/dev/pci/if_vgevar.h new file mode 100644 index 00000000000..960bb315fe9 --- /dev/null +++ b/sys/dev/pci/if_vgevar.h @@ -0,0 +1,126 @@ +/* $OpenBSD: if_vgevar.h,v 1.1 2004/12/01 01:29:00 pvalchev Exp $ */ +/* $FreeBSD: if_vgevar.h,v 1.1 2004/09/10 20:57:45 wpaul Exp $ */ +/* + * Copyright (c) 2004 + * Bill Paul <wpaul@windriver.com>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define VGE_JUMBO_MTU 9000 + +#define VGE_IFQ_MAXLEN 64 + +#define VGE_TX_DESC_CNT 256 +#define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */ +#define VGE_RING_ALIGN 256 +#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc)) +#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc)) +#define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT) +#define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT) +#define VGE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) +#define VGE_ADDR_HI(y) ((u_int64_t) (y) >> 32) +#define VGE_BUFLEN(y) ((y) & 0x7FFF) +#define VGE_OWN(x) (letoh32((x)->vge_sts) & VGE_RDSTS_OWN) +#define VGE_RXBYTES(x) ((letoh32((x)->vge_sts) & \ + VGE_RDSTS_BUFSIZ) >> 16) +#define VGE_MIN_FRAMELEN 60 + +#define MAX_NUM_MULTICAST_ADDRESSES 128 + +struct vge_softc; + +struct vge_list_data { + struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT]; + struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT]; + int vge_tx_prodidx; + int vge_rx_prodidx; + int vge_tx_considx; + int vge_tx_free; + bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT]; + bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT]; + bus_dma_tag_t vge_mtag; /* mbuf mapping tag */ + bus_dma_segment_t vge_rx_listseg; + bus_dmamap_t vge_rx_list_map; + struct vge_rx_desc *vge_rx_list; + bus_dma_segment_t vge_tx_listseg; + bus_dmamap_t vge_tx_list_map; + struct vge_tx_desc *vge_tx_list; +}; + +struct vge_softc { + struct device vge_dev; + struct arpcom arpcom; /* interface info */ + bus_space_handle_t vge_bhandle; /* bus space handle */ + bus_space_tag_t vge_btag; /* bus space tag */ + void *vge_intrhand; + bus_dma_tag_t sc_dmat; + struct mii_data sc_mii; + int vge_if_flags; + int vge_rx_consumed; + int vge_link; + int vge_camidx; + struct timeout timer_handle; + struct mbuf *vge_head; + struct mbuf *vge_tail; + + struct vge_list_data vge_ldata; +}; + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg) +#define CSR_READ_1(sc, reg) \ + bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg) + +#define CSR_SETBIT_1(sc, reg, x) \ + CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) +#define CSR_SETBIT_2(sc, reg, x) \ + CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) +#define CSR_SETBIT_4(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) + +#define CSR_CLRBIT_1(sc, reg, x) \ + CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) +#define CSR_CLRBIT_2(sc, reg, x) \ + CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) +#define CSR_CLRBIT_4(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) + +#define VGE_TIMEOUT 10000 |