diff options
Diffstat (limited to 'sys')
25 files changed, 782 insertions, 648 deletions
diff --git a/sys/arch/mips64/mips64/arcbios.c b/sys/arch/mips64/mips64/arcbios.c index 8679dbe680c..50116dd22a4 100644 --- a/sys/arch/mips64/mips64/arcbios.c +++ b/sys/arch/mips64/mips64/arcbios.c @@ -1,4 +1,4 @@ -/* $OpenBSD: arcbios.c,v 1.5 2004/08/15 12:08:24 pefo Exp $ */ +/* $OpenBSD: arcbios.c,v 1.6 2004/09/09 22:11:38 pefo Exp $ */ /*- * Copyright (c) 1996 M. Warner Losh. All rights reserved. * Copyright (c) 1996-2004 Opsycon AB. All rights reserved. @@ -270,7 +270,7 @@ bios_get_system_type() cf = (arc_config_t *)Bios_GetChild(NULL); if (cf) { for (i = 0; i < KNOWNSYSTEMS; i++) { - if (strcmp(sys_types[i].sys_name, cf->id) != 0) + if (strcmp(sys_types[i].sys_name, (char *)(long)cf->id) != 0) continue; if (sys_types[i].sys_vend && strncmp(sys_types[i].sys_vend, sid->vendor, 8) != 0) @@ -281,7 +281,7 @@ bios_get_system_type() bios_putstring("UNIDENTIFIED SYSTEM `"); if (cf) - bios_putstring(cf->id); + bios_putstring((char *)(long)cf->id); else bios_putstring("????????"); bios_putstring("' VENDOR `"); diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S index 5398bb309d0..6610569b3d5 100644 --- a/sys/arch/mips64/mips64/cache_r5k.S +++ b/sys/arch/mips64/mips64/cache_r5k.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r5k.S,v 1.4 2004/08/10 20:15:47 deraadt Exp $ */ +/* $OpenBSD: cache_r5k.S,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se) @@ -162,7 +162,7 @@ * primary cache associativity. * * Allocation: - * t4, t5 t6 used to hold I and D set size and Alias mask. + * ta4, ta5 ta6 used to hold I and D set size and Alias mask. * *---------------------------------------------------------------------------- */ @@ -174,7 +174,7 @@ LEAF(Mips5k_ConfigCache) srl t1, v0, 9 # Get I cache size. and t1, 3 li t2, 4096 - sllv t4, t2, t1 # t4 = Initial I set size. + sllv ta4, t2, t1 # ta4 = Initial I set size. and t2, v0, 0x20 srl t2, t2, 1 # Get I cache line size. @@ -184,15 +184,15 @@ LEAF(Mips5k_ConfigCache) srl t1, v0, 6 # Get D cache size. and t1, 3 li t2, 4096 # Fixed page size. - sllv t5, t2, t1 + sllv ta5, t2, t1 and t2, v0, 0x10 addu t2, t2, 16 # Get D cache line size. sw t2, CpuPrimaryDataCacheLSize li t2, CTYPE_2WAY # Assume two way cache - li t6, 0 # Secondary size 0. - li t7, 0 # Tertiary size 0. + li ta6, 0 # Secondary size 0. + li ta7, 0 # Tertiary size 0. and v1, 0xff00 # Recognize CPU's with li t1, (MIPS_R4600 << 8) # N way L1 caches only. @@ -217,7 +217,7 @@ LEAF(Mips5k_ConfigCache) Conf5K: # R5000 type, check for L2 cache and t1, v0, CF_5_SC bnez t1, ConfResult # not enabled - li t6, 0 # set size to 0. + li ta6, 0 # set size to 0. li t3, CF_5_SS and t1, t3, v0 @@ -227,15 +227,15 @@ Conf5K: # R5000 type, check for L2 cache or t2, CTYPE_HAS_XL2 # External L2 present. li t3, CF_5_SE # Set SE in conf or v0, t3 # Update config register - li t6, 512*1024 # 512k per 'click'. - sll t6, t1 + li ta6, 512*1024 # 512k per 'click'. + sll ta6, t1 mtc0 v0, COP_0_CONFIG # Enable L2 cache - la t0, KSEG0_BASE - addu t1, t0, t6 + LA t0, KSEG0_BASE + PTR_ADDU t1, t0, ta6 1: cache InvalidateSecondaryPage, 0(t0) - addu t0, 128*32 + PTR_ADDU t0, 128*32 bne t0, t1, 1b nop @@ -247,7 +247,7 @@ Conf5K: # R5000 type, check for L2 cache Conf52K: # R5200 type, check for L2 cache and t1, v0, CF_52_SC bnez t1, ConfResult # not present - li t6, 0 # set size to 0. + li ta6, 0 # set size to 0. li t3, CF_52_SS and t1, t3, v0 @@ -257,16 +257,16 @@ Conf52K: # R5200 type, check for L2 cache or t2, CTYPE_HAS_XL2 # External L2 present. li t3, CF_5_SE # Set SE in conf or v0, t3 # Update config register - li t6, 512*1024 # 512k per 'click'. + li ta6, 512*1024 # 512k per 'click'. lw t3, CpuExternalCacheOn # Check if disabled bnez t3, ConfResult # No use it. - sll t6, t1 + sll ta6, t1 and t2, ~CTYPE_HAS_XL2 li t1, ~CF_52_SE # Clear SE in conf and v0, t1 # Update config register b ConfResult - li t6, 0 # L2 cache disabled + li ta6, 0 # L2 cache disabled #---- RM7K ----------------------------- @@ -274,11 +274,11 @@ Conf7K: # RM7000, check for L2 and L3 cache li t2, CTYPE_4WAY # 4-way cache and t1, v0, CF_7_TC bnez t1, Conf7KL2 # No L3 cache if set - li t7, 0 # Set size = 0 + li ta7, 0 # Set size = 0 - lw t7, CpuTertiaryCacheSize + lw ta7, CpuTertiaryCacheSize and t2, ~CTYPE_HAS_XL3 - beqz t7, Conf7KL2 # No L3 cache present + beqz ta7, Conf7KL2 # No L3 cache present nop or t2, CTYPE_HAS_XL3 @@ -289,25 +289,25 @@ Conf7K: # RM7000, check for L2 and L3 cache and v0, ~CF_7_TE # Clear TE in conf mtc0 v0, COP_0_CONFIG # establish any new config NOP10 - li t7, 0 # L3 cache disabled + li ta7, 0 # L3 cache disabled Conf7KL2: and t1, v0, CF_7_SC # check for L2 cache bnez t1, ConfResult - li t6, 0 # No L2? + li ta6, 0 # No L2? or t2, CTYPE_HAS_IL2 # L2 is on chip lw t3, CpuOnboardCacheOn # Check if disabled bnez t3, ConfResult # No, use it - li t6, 256*1024 # size = 256k + li ta6, 256*1024 # size = 256k /* Sync on chip L2 */ - li a0, 0x80000000 - li a1, 0x80040000 + LA a0, KSEG0_BASE + LA a1, KSEG0_BASE+0x00040000 10: cache IndexWBInvalidate_S, 0(a0) - addu a0, 32 + PTR_ADDU a0, 32 bne a0, a1, 10b nop @@ -317,11 +317,11 @@ Conf7KL2: mtc0 v0, COP_0_CONFIG # establish any new config NOP10 b ConfResult - li t6, 0 # L2 cache disabled + li ta6, 0 # L2 cache disabled /* - * Get here with t2 = Cache type, t4 = L1 I size, t5 = L1 D size. - * t6 = secondary size, t7 = tertiary size. + * Get here with t2 = Cache type, ta4 = L1 I size, ta5 = L1 D size. + * ta6 = secondary size, ta7 = tertiary size. */ ConfResult: sw v0, CpuConfigRegister @@ -332,21 +332,21 @@ ConfResult: sw t2, CpuNWayCache srl t2, 1 # get div shift for set size. - sw t6, CpuSecondaryCacheSize - sw t7, CpuTertiaryCacheSize + sw ta6, CpuSecondaryCacheSize + sw ta7, CpuTertiaryCacheSize - addu t1, t4, -1 # Use icache for alias mask + addu t1, ta4, -1 # Use icache for alias mask srl t1, t2 # Some cpus have different and t1, ~(NBPG - 1) # i and d cache sizes... sw t1, CpuCacheAliasMask - sw t4, CpuPrimaryInstCacheSize # store cache size. - srl t4, t2 # calculate set size. - sw t4, CpuPrimaryInstSetSize + sw ta4, CpuPrimaryInstCacheSize # store cache size. + srl ta4, t2 # calculate set size. + sw ta4, CpuPrimaryInstSetSize - sw t5, CpuPrimaryDataCacheSize # store cache size. - srl t5, t2 # calculate set size. - sw t5, CpuPrimaryDataSetSize + sw ta5, CpuPrimaryDataCacheSize # store cache size. + srl ta5, t2 # calculate set size. + sw ta5, CpuPrimaryDataSetSize and v0, 0xfffffff8 or v0, 0x00000003 # set cachable writeback kseg0 @@ -424,11 +424,11 @@ LEAF(Mips5k_SyncCache) 3: LA t3, KSEG0_BASE - lw t4, CpuSecondaryCacheSize + lw ta4, CpuSecondaryCacheSize 10: cache IndexWBInvalidate_S, 0(t3) - PTR_SUBU t4, 32 # Fixed cache line size. - bgtz t4, 10b + PTR_SUBU ta4, 32 # Fixed cache line size. + bgtz ta4, 10b PTR_ADDU t3, 32 /* Do off chip L2 if present */ @@ -440,11 +440,11 @@ LEAF(Mips5k_SyncCache) mtc0 zero, COP_0_TAG_LO LA t3, KSEG0_BASE - lw t4, CpuSecondaryCacheSize + lw ta4, CpuSecondaryCacheSize 21: cache InvalidateSecondaryPage, 0(t3) - PTR_SUBU t4, 4096 # Fixed cache page size. - bgtz t4, 21b + PTR_SUBU ta4, 4096 # Fixed cache page size. + bgtz ta4, 21b PTR_ADDU t3, 4096 /* Do off chip L3 if present */ @@ -456,11 +456,11 @@ LEAF(Mips5k_SyncCache) mtc0 zero, COP_0_TAG_LO LA t3, KSEG0_BASE - lw t4, CpuTertiaryCacheSize + lw ta4, CpuTertiaryCacheSize 31: cache InvalidatePage_T, 0(t3) - PTR_SUBU t4, 4096 # Fixed cache page size. - bgtz t4, 31b + PTR_SUBU ta4, 4096 # Fixed cache page size. + bgtz ta4, 31b PTR_ADDU t3, 4096 99: @@ -898,24 +898,31 @@ END(Mips5k_HitInvalidateSCache) * *---------------------------------------------------------------------------- */ -NON_LEAF(Mips5k_IOSyncDCache, FRAMESZ(CF_SZ), ra) +NON_LEAF(Mips5k_IOSyncDCache, FRAMESZ(CF_SZ+2*REGSZ), ra) - PTR_SUBU sp, FRAMESZ(CF_SZ) - PTR_S ra, CF_RA_OFFS(sp) - REG_S a0, FRAMESZ(CF_SZ)(sp) # save args + PTR_SUBU sp, FRAMESZ(CF_SZ+2*REGSZ) + PTR_S ra, CF_RA_OFFS+2*REGSZ(sp) + REG_S a0, CF_ARGSZ(sp) # save args beqz a2, SyncRD # Sync PREREAD - REG_S a1, FRAMESZ(CF_SZ)+REGSZ(sp) + REG_S a1, CF_ARGSZ+REGSZ(sp) addiu a2, 1 bnez a2, SyncRDWB # Sync PREWRITE+PREREAD nop lw t0, CpuCacheType # Sync PREWRITE and t0, CTYPE_HAS_IL2 # Have internal L2? - beqzl t0, Mips5k_HitSyncDCache # No flush L1. - PTR_ADDU sp, FRAMESZ(CF_SZ) + bnez t0, SyncSC # Yes + nop + jal Mips5k_HitSyncDCache # No flush L1. + nop + b SyncDone + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) - b Mips5k_HitSyncSCache # Do internal L2 cache +SyncSC: + jal Mips5k_HitSyncSCache # Do internal L2 cache nop # L1 done in parallel + b SyncDone + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) SyncRD: and t0, a0, 31 # check if invalidate possible @@ -936,14 +943,14 @@ SyncRD: nop b SyncRDXL2 - PTR_L ra, CF_RA_OFFS(sp) # External L2 if present + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) # External L2 if present SyncRDL2: jal Mips5k_HitInvalidateSCache # Internal L2 cache nop # L1 done in parallel b SyncRDL3 - PTR_L ra, CF_RA_OFFS(sp) # L3 invalidate if present + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) # L3 invalidate if present /* * Sync for unaligned read or write-read. @@ -958,21 +965,21 @@ SyncRDWB: nop b SyncRDXL2 - PTR_L ra, CF_RA_OFFS(sp) # External L2 if present + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) # External L2 if present SyncRDWBL2: jal Mips5k_HitSyncSCache # Internal L2 cache nop # L1 done in parallel b SyncRDL3 - PTR_L ra, CF_RA_OFFS(sp) # L3 invalidate if present + PTR_L ra, CF_RA_OFFS+2*REGSZ(sp) # L3 invalidate if present SyncRDXL2: lw t0, CpuCacheType and t0, CTYPE_HAS_XL2 # Have external L2? beqz t0, SyncRDL3 # Nope. - REG_L a0, FRAMESZ(CF_SZ)(sp) - REG_L a1, FRAMESZ(CF_SZ)+REGSZ(sp) + REG_L a0, CF_ARGSZ(sp) + REG_L a1, CF_ARGSZ+REGSZ(sp) and a2, a0, 4095 # align on page size PTR_SUBU a0, a2 PTR_ADDU a1, a2 @@ -988,8 +995,8 @@ SyncRDL3: lw t0, CpuCacheType and t0, CTYPE_HAS_XL3 # Have L3? beqz t0, SyncDone # Nope. - REG_L a0, FRAMESZ(CF_SZ)(sp) - REG_L a1, FRAMESZ(CF_SZ)+REGSZ(sp) + REG_L a0, CF_ARGSZ(sp) + REG_L a1, CF_ARGSZ+REGSZ(sp) and a2, a0, 4095 # align on page size PTR_SUBU a0, a2 PTR_ADDU a1, a2 @@ -1003,5 +1010,5 @@ SyncRDL3: SyncDone: j ra - PTR_ADDU sp, FRAMESZ(CF_SZ) + PTR_ADDU sp, FRAMESZ(CF_SZ+2*REGSZ) END(Mips5k_IOSyncDCache) diff --git a/sys/arch/mips64/mips64/context.S b/sys/arch/mips64/mips64/context.S index b963db46861..7c1b835f9dd 100644 --- a/sys/arch/mips64/mips64/context.S +++ b/sys/arch/mips64/mips64/context.S @@ -1,4 +1,4 @@ -/* $OpenBSD: context.S,v 1.3 2004/08/10 20:15:47 deraadt Exp $ */ +/* $OpenBSD: context.S,v 1.4 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -59,12 +59,12 @@ LEAF(savectx) REG_S s7, U_PCB_CONTEXT+7*REGSZ(a0) REG_S sp, U_PCB_CONTEXT+8*REGSZ(a0) REG_S s8, U_PCB_CONTEXT+9*REGSZ(a0) - PTR_S ra, U_PCB_CONTEXT+10*REGSZ(a0) + REG_S ra, U_PCB_CONTEXT+10*REGSZ(a0) REG_S v0, U_PCB_CONTEXT+11*REGSZ(a0) cfc0 t1, COP_0_ICR lw t0, cpl - sw t1, U_PCB_CONTEXT+12*REGSZ(a0) # save status register - sw t0, U_PCB_CONTEXT+13*REGSZ(a0) + REG_S t1, U_PCB_CONTEXT+12*REGSZ(a0) # save status register + REG_S t0, U_PCB_CONTEXT+13*REGSZ(a0) j ra move v0, zero END(savectx) @@ -225,9 +225,9 @@ END(switch_exit) */ NON_LEAF(cpu_switch, FRAMESZ(CF_SZ), ra) PTR_L t3, curprocpaddr - PTR_S sp, U_PCB_CONTEXT+8*REGSZ(t3) # save old sp + REG_S sp, U_PCB_CONTEXT+8*REGSZ(t3) # save old sp PTR_SUBU sp, sp, FRAMESZ(CF_SZ) - PTR_S ra, CF_RA_OFFS(sp) + REG_S ra, CF_RA_OFFS(sp) .mask 0x80000000, (CF_RA_OFFS - FRAMESZ(CF_SZ)) lw t0, cpl sw t0, U_PCB_CONTEXT+13*REGSZ(t3) @@ -241,7 +241,7 @@ NON_LEAF(cpu_switch, FRAMESZ(CF_SZ), ra) REG_S s6, U_PCB_CONTEXT+6*REGSZ(t3) REG_S s7, U_PCB_CONTEXT+7*REGSZ(t3) REG_S s8, U_PCB_CONTEXT+9*REGSZ(t3) - PTR_S ra, U_PCB_CONTEXT+10*REGSZ(t3) + REG_S ra, U_PCB_CONTEXT+10*REGSZ(t3) mfc0 t0, COP_0_STATUS_REG cfc0 t1, COP_0_ICR REG_S t0, U_PCB_CONTEXT+11*REGSZ(t3) @@ -336,14 +336,14 @@ sw1: ctx1: mtc0 zero, COP_0_TLB_INDEX dmtc0 v0, COP_0_TLB_HI - lw t4, 0(t1) - lw t5, 4(t1) - dsll t4, t4, 34 - dsrl t4, t4, 34 - dsll t5, t5, 34 - dsrl t5, t5, 34 - dmtc0 t4, COP_0_TLB_LO0 - dmtc0 t5, COP_0_TLB_LO1 + lw ta4, 0(t1) + lw ta5, 4(t1) + dsll ta4, ta4, 34 + dsrl ta4, ta4, 34 + dsll ta5, ta5, 34 + dsrl ta5, ta5, 34 + dmtc0 ta4, COP_0_TLB_LO0 + dmtc0 ta5, COP_0_TLB_LO1 nop PTR_ADDU v0, 2*NBPG nop @@ -352,14 +352,14 @@ ctx1: #if (UPAGES != 2) dmtc0 v0, COP_0_TLB_HI # init high entry (tlbid) - lw t4, 8(t1) - lw t5, 12(t1) - dsll t4, t4, 34 - dsrl t4, t4, 34 + lw ta4, 8(t1) + lw ta5, 12(t1) + dsll ta4, ta4, 34 + dsrl ta4, ta4, 34 tlbp nop - dsll t5, t5, 34 - dsrl t5, t5, 34 + dsll ta5, ta5, 34 + dsrl ta5, ta5, 34 mfc0 t0, COP_0_TLB_INDEX nop bltz t0, ctx2 # not in tlb @@ -380,8 +380,8 @@ ctx1: ctx2: mtc0 t2, COP_0_TLB_INDEX dmtc0 v0, COP_0_TLB_HI - dmtc0 t4, COP_0_TLB_LO0 - dmtc0 t5, COP_0_TLB_LO1 + dmtc0 ta4, COP_0_TLB_LO0 + dmtc0 ta5, COP_0_TLB_LO1 nop nop nop @@ -398,7 +398,7 @@ ctx3: /* * Restore registers and return. */ - lw a0, U_PCB_CONTEXT+13*REGSZ(t3) + REG_L a0, U_PCB_CONTEXT+13*REGSZ(t3) REG_L s0, U_PCB_CONTEXT+0*REGSZ(t3) REG_L s1, U_PCB_CONTEXT+1*REGSZ(t3) REG_L s2, U_PCB_CONTEXT+2*REGSZ(t3) @@ -414,9 +414,9 @@ ctx3: jal hw_setintrmask nop #endif - PTR_L ra, U_PCB_CONTEXT+10*REGSZ(t3) - lw v0, U_PCB_CONTEXT+11*REGSZ(t3) - lw v1, U_PCB_CONTEXT+12*REGSZ(t3) + REG_L ra, U_PCB_CONTEXT+10*REGSZ(t3) + REG_L v0, U_PCB_CONTEXT+11*REGSZ(t3) + REG_L v1, U_PCB_CONTEXT+12*REGSZ(t3) #ifndef IMASK_EXTERNAL ctc0 v1, COP_0_ICR # XXX RM7000 #endif diff --git a/sys/arch/mips64/mips64/cpu.c b/sys/arch/mips64/mips64/cpu.c index 6434d3990e1..038db59eba2 100644 --- a/sys/arch/mips64/mips64/cpu.c +++ b/sys/arch/mips64/mips64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.6 2004/08/11 15:13:58 deraadt Exp $ */ +/* $OpenBSD: cpu.c,v 1.7 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se) @@ -195,7 +195,7 @@ cpuattach(struct device *parent, struct device *dev, void *aux) printf("cpu%d: Alias mask 0x%x\n", cpuno, CpuCacheAliasMask); printf("cpu%d: Config Register %x\n", cpuno, CpuConfigRegister); printf("cpu%d: Cache type %x\n", cpuno, CpuCacheType); - if (fpu_id.cpu[cpuno].cp_imp == MIPS_RM7000) { + if (sys_config.cpu[cpuno].fptype == MIPS_RM7000) { u_int tmp = CpuConfigRegister; printf("cpu%d: ", cpuno); diff --git a/sys/arch/mips64/mips64/db_machdep.c b/sys/arch/mips64/mips64/db_machdep.c index ec0225315aa..10c6e3368f4 100644 --- a/sys/arch/mips64/mips64/db_machdep.c +++ b/sys/arch/mips64/mips64/db_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: db_machdep.c,v 1.4 2004/08/10 20:28:13 deraadt Exp $ */ +/* $OpenBSD: db_machdep.c,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se) @@ -238,7 +238,7 @@ loop: stksize = 0; /* check for bad SP: could foul up next frame */ - if (sp & 3 || sp < 0xffffffff80000000) { + if (sp & 3 || sp < KSEG0_BASE) { (*pr)("SP %p: not in kernel\n", sp); ra = 0; subr = 0; @@ -265,8 +265,8 @@ loop: /* check for bad PC */ - if (pc & 3 || pc < 0xffffffff80000000 || pc >= (unsigned)edata) { - (*pr)("PC 0x%x: not in kernel\n", pc); + if (pc & 3 || pc < KSEG0_BASE || pc >= (unsigned)edata) { + (*pr)("PC 0x%p: not in kernel\n", pc); ra = 0; goto done; } diff --git a/sys/arch/mips64/mips64/exception.S b/sys/arch/mips64/mips64/exception.S index e07663234bd..ac209ea70fe 100644 --- a/sys/arch/mips64/mips64/exception.S +++ b/sys/arch/mips64/mips64/exception.S @@ -1,4 +1,4 @@ -/* $OpenBSD: exception.S,v 1.3 2004/08/10 20:15:47 deraadt Exp $ */ +/* $OpenBSD: exception.S,v 1.4 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -164,7 +164,7 @@ exception: LA k0, u_exception_table PTR_ADDU k0, k0, k1 -#if (_MIPS_SZPTR == 64) +#ifdef __LP64__ PTR_ADDU k0, k0, k1 # yes, twice... #endif PTR_L k0, 0(k0) @@ -174,7 +174,7 @@ exception: k_exception: LA k0, k_exception_table PTR_ADDU k0, k0, k1 -#if (_MIPS_SZPTR == 64) +#ifdef __LP64__ PTR_ADDU k0, k0, k1 # yes, twice... #endif PTR_L k0, 0(k0) diff --git a/sys/arch/mips64/mips64/fp.S b/sys/arch/mips64/mips64/fp.S index 6b76ce020e2..7ffbe42b5a3 100644 --- a/sys/arch/mips64/mips64/fp.S +++ b/sys/arch/mips64/mips64/fp.S @@ -1,4 +1,4 @@ -/* $OpenBSD: fp.S,v 1.2 2004/08/15 18:35:58 pefo Exp $ */ +/* $OpenBSD: fp.S,v 1.3 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)fp.s 8.1 (Berkeley) 6/10/93 - * $Id: fp.S,v 1.2 2004/08/15 18:35:58 pefo Exp $ + * $Id: fp.S,v 1.3 2004/09/09 22:11:38 pefo Exp $ */ /* @@ -638,7 +638,7 @@ func_fmt_tbl: */ sub_s: jal get_ft_fs_s - xor t4, t4, 1 # negate FT sign bit + xor ta4, ta4, 1 # negate FT sign bit b add_sub_s /* * Single precision add. @@ -647,38 +647,38 @@ add_s: jal get_ft_fs_s add_sub_s: bne t1, SEXP_INF, 1f # is FS an infinity? - bne t5, SEXP_INF, result_fs_s # if FT is not inf, result=FS + bne ta5, SEXP_INF, result_fs_s # if FT is not inf, result=FS bne t2, zero, result_fs_s # if FS is NAN, result is FS - bne t6, zero, result_ft_s # if FT is NAN, result is FT - bne t0, t4, invalid_s # both infinities same sign? + bne ta6, zero, result_ft_s # if FT is NAN, result is FT + bne t0, ta4, invalid_s # both infinities same sign? b result_fs_s # result is in FS 1: - beq t5, SEXP_INF, result_ft_s # if FT is inf, result=FT + beq ta5, SEXP_INF, result_ft_s # if FT is inf, result=FT bne t1, zero, 4f # is FS a denormalized num? beq t2, zero, 3f # is FS zero? - bne t5, zero, 2f # is FT a denormalized num? - beq t6, zero, result_fs_s # FT is zero, result=FS + bne ta5, zero, 2f # is FT a denormalized num? + beq ta6, zero, result_fs_s # FT is zero, result=FS jal renorm_fs_s jal renorm_ft_s b 5f 2: jal renorm_fs_s - subu t5, t5, SEXP_BIAS # unbias FT exponent - or t6, t6, SIMPL_ONE # set implied one bit + subu ta5, ta5, SEXP_BIAS # unbias FT exponent + or ta6, ta6, SIMPL_ONE # set implied one bit b 5f 3: - bne t5, zero, result_ft_s # if FT != 0, result=FT - bne t6, zero, result_ft_s + bne ta5, zero, result_ft_s # if FT != 0, result=FT + bne ta6, zero, result_ft_s and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, t4 # compute result sign + or t0, t0, ta4 # compute result sign b result_fs_s 1: - and t0, t0, t4 # compute result sign + and t0, t0, ta4 # compute result sign b result_fs_s 4: - bne t5, zero, 2f # is FT a denormalized num? - beq t6, zero, result_fs_s # FT is zero, result=FS + bne ta5, zero, 2f # is FT a denormalized num? + beq ta6, zero, result_fs_s # FT is zero, result=FS subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit jal renorm_ft_s @@ -686,15 +686,15 @@ add_sub_s: 2: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit - subu t5, t5, SEXP_BIAS # unbias FT exponent - or t6, t6, SIMPL_ONE # set implied one bit + subu ta5, ta5, SEXP_BIAS # unbias FT exponent + or ta6, ta6, SIMPL_ONE # set implied one bit /* * Perform the addition. */ 5: move t8, zero # no shifted bits (sticky reg) - beq t1, t5, 4f # no shift needed - subu v0, t1, t5 # v0 = difference of exponents + beq t1, ta5, 4f # no shift needed + subu v0, t1, ta5 # v0 = difference of exponents move v1, v0 # v1 = abs(difference) bge v0, zero, 1f negu v1 @@ -702,50 +702,50 @@ add_sub_s: ble v1, SFRAC_BITS+2, 2f # is difference too great? li t8, STICKYBIT # set the sticky bit bge v0, zero, 1f # check which exp is larger - move t1, t5 # result exp is FTs + move t1, ta5 # result exp is FTs move t2, zero # FSs fraction shifted is zero b 4f 1: - move t6, zero # FTs fraction shifted is zero + move ta6, zero # FTs fraction shifted is zero b 4f 2: li t9, 32 # compute 32 - abs(exp diff) subu t9, t9, v1 bgt v0, zero, 3f # if FS > FT, shift FTs frac - move t1, t5 # FT > FS, result exp is FTs + move t1, ta5 # FT > FS, result exp is FTs sll t8, t2, t9 # save bits shifted out srl t2, t2, v1 # shift FSs fraction b 4f 3: - sll t8, t6, t9 # save bits shifted out - srl t6, t6, v1 # shift FTs fraction + sll t8, ta6, t9 # save bits shifted out + srl ta6, ta6, v1 # shift FTs fraction 4: - bne t0, t4, 1f # if signs differ, subtract - addu t2, t2, t6 # add fractions + bne t0, ta4, 1f # if signs differ, subtract + addu t2, t2, ta6 # add fractions b norm_s 1: - blt t2, t6, 3f # subtract larger from smaller - bne t2, t6, 2f # if same, result=0 + blt t2, ta6, 3f # subtract larger from smaller + bne t2, ta6, 2f # if same, result=0 move t1, zero # result=0 move t2, zero and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, t4 # compute result sign + or t0, t0, ta4 # compute result sign b result_fs_s 1: - and t0, t0, t4 # compute result sign + and t0, t0, ta4 # compute result sign b result_fs_s 2: - sltu t9, zero, t8 # compute t2:zero - t6:t8 + sltu t9, zero, t8 # compute t2:zero - ta6:t8 subu t8, zero, t8 - subu t2, t2, t6 # subtract fractions + subu t2, t2, ta6 # subtract fractions subu t2, t2, t9 # subtract barrow b norm_s 3: - move t0, t4 # sign of result = FTs - sltu t9, zero, t8 # compute t6:zero - t2:t8 + move t0, ta4 # sign of result = FTs + sltu t9, zero, t8 # compute ta6:zero - t2:t8 subu t8, zero, t8 - subu t2, t6, t2 # subtract fractions + subu t2, ta6, t2 # subtract fractions subu t2, t2, t9 # subtract barrow b norm_s @@ -754,7 +754,7 @@ add_sub_s: */ sub_d: jal get_ft_fs_d - xor t4, t4, 1 # negate sign bit + xor ta4, ta4, 1 # negate sign bit b add_sub_d /* * Double precision add. @@ -763,46 +763,46 @@ add_d: jal get_ft_fs_d add_sub_d: bne t1, DEXP_INF, 1f # is FS an infinity? - bne t5, DEXP_INF, result_fs_d # if FT is not inf, result=FS + bne ta5, DEXP_INF, result_fs_d # if FT is not inf, result=FS bne t2, zero, result_fs_d # if FS is NAN, result is FS bne t3, zero, result_fs_d - bne t6, zero, result_ft_d # if FT is NAN, result is FT - bne t7, zero, result_ft_d - bne t0, t4, invalid_d # both infinities same sign? + bne ta6, zero, result_ft_d # if FT is NAN, result is FT + bne ta7, zero, result_ft_d + bne t0, ta4, invalid_d # both infinities same sign? b result_fs_d # result is in FS 1: - beq t5, DEXP_INF, result_ft_d # if FT is inf, result=FT + beq ta5, DEXP_INF, result_ft_d # if FT is inf, result=FT bne t1, zero, 4f # is FS a denormalized num? bne t2, zero, 1f # is FS zero? beq t3, zero, 3f 1: - bne t5, zero, 2f # is FT a denormalized num? - bne t6, zero, 1f - beq t7, zero, result_fs_d # FT is zero, result=FS + bne ta5, zero, 2f # is FT a denormalized num? + bne ta6, zero, 1f + beq ta7, zero, result_fs_d # FT is zero, result=FS 1: jal renorm_fs_d jal renorm_ft_d b 5f 2: jal renorm_fs_d - subu t5, t5, DEXP_BIAS # unbias FT exponent - or t6, t6, DIMPL_ONE # set implied one bit + subu ta5, ta5, DEXP_BIAS # unbias FT exponent + or ta6, ta6, DIMPL_ONE # set implied one bit b 5f 3: - bne t5, zero, result_ft_d # if FT != 0, result=FT - bne t6, zero, result_ft_d - bne t7, zero, result_ft_d + bne ta5, zero, result_ft_d # if FT != 0, result=FT + bne ta6, zero, result_ft_d + bne ta7, zero, result_ft_d and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, t4 # compute result sign + or t0, t0, ta4 # compute result sign b result_fs_d 1: - and t0, t0, t4 # compute result sign + and t0, t0, ta4 # compute result sign b result_fs_d 4: - bne t5, zero, 2f # is FT a denormalized num? - bne t6, zero, 1f - beq t7, zero, result_fs_d # FT is zero, result=FS + bne ta5, zero, 2f # is FT a denormalized num? + bne ta6, zero, 1f + beq ta7, zero, result_fs_d # FT is zero, result=FS 1: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit @@ -811,15 +811,15 @@ add_sub_d: 2: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit - subu t5, t5, DEXP_BIAS # unbias FT exponent - or t6, t6, DIMPL_ONE # set implied one bit + subu ta5, ta5, DEXP_BIAS # unbias FT exponent + or ta6, ta6, DIMPL_ONE # set implied one bit /* * Perform the addition. */ 5: move t8, zero # no shifted bits (sticky reg) - beq t1, t5, 4f # no shift needed - subu v0, t1, t5 # v0 = difference of exponents + beq t1, ta5, 4f # no shift needed + subu v0, t1, ta5 # v0 = difference of exponents move v1, v0 # v1 = abs(difference) bge v0, zero, 1f negu v1 @@ -827,18 +827,18 @@ add_sub_d: ble v1, DFRAC_BITS+2, 2f # is difference too great? li t8, STICKYBIT # set the sticky bit bge v0, zero, 1f # check which exp is larger - move t1, t5 # result exp is FTs + move t1, ta5 # result exp is FTs move t2, zero # FSs fraction shifted is zero move t3, zero b 4f 1: - move t6, zero # FTs fraction shifted is zero - move t7, zero + move ta6, zero # FTs fraction shifted is zero + move ta7, zero b 4f 2: li t9, 32 bge v0, zero, 3f # if FS > FT, shift FTs frac - move t1, t5 # FT > FS, result exp is FTs + move t1, ta5 # FT > FS, result exp is FTs blt v1, t9, 1f # shift right by < 32? subu v1, v1, t9 subu t9, t9, v1 @@ -860,62 +860,62 @@ add_sub_d: blt v1, t9, 1f # shift right by < 32? subu v1, v1, t9 subu t9, t9, v1 - sll t8, t6, t9 # save bits shifted out - srl t7, t6, v1 # shift FTs fraction - move t6, zero + sll t8, ta6, t9 # save bits shifted out + srl ta7, ta6, v1 # shift FTs fraction + move ta6, zero b 4f 1: subu t9, t9, v1 - sll t8, t7, t9 # save bits shifted out - srl t7, t7, v1 # shift FTs fraction - sll t9, t6, t9 # save bits shifted out of t2 - or t7, t7, t9 # and put into t3 - srl t6, t6, v1 + sll t8, ta7, t9 # save bits shifted out + srl ta7, ta7, v1 # shift FTs fraction + sll t9, ta6, t9 # save bits shifted out of t2 + or ta7, ta7, t9 # and put into t3 + srl ta6, ta6, v1 4: - bne t0, t4, 1f # if signs differ, subtract - addu t3, t3, t7 # add fractions - sltu t9, t3, t7 # compute carry - addu t2, t2, t6 # add fractions + bne t0, ta4, 1f # if signs differ, subtract + addu t3, t3, ta7 # add fractions + sltu t9, t3, ta7 # compute carry + addu t2, t2, ta6 # add fractions addu t2, t2, t9 # add carry b norm_d 1: - blt t2, t6, 3f # subtract larger from smaller - bne t2, t6, 2f - bltu t3, t7, 3f - bne t3, t7, 2f # if same, result=0 + blt t2, ta6, 3f # subtract larger from smaller + bne t2, ta6, 2f + bltu t3, ta7, 3f + bne t3, ta7, 2f # if same, result=0 move t1, zero # result=0 move t2, zero move t3, zero and v0, a1, FPC_ROUNDING_BITS # get rounding mode bne v0, FPC_ROUND_RM, 1f # round to -infinity? - or t0, t0, t4 # compute result sign + or t0, t0, ta4 # compute result sign b result_fs_d 1: - and t0, t0, t4 # compute result sign + and t0, t0, ta4 # compute result sign b result_fs_d 2: - beq t8, zero, 1f # compute t2:t3:zero - t6:t7:t8 + beq t8, zero, 1f # compute t2:t3:zero - ta6:ta7:t8 subu t8, zero, t8 sltu v0, t3, 1 # compute barrow out subu t3, t3, 1 # subtract barrow subu t2, t2, v0 1: - sltu v0, t3, t7 - subu t3, t3, t7 # subtract fractions - subu t2, t2, t6 # subtract fractions + sltu v0, t3, ta7 + subu t3, t3, ta7 # subtract fractions + subu t2, t2, ta6 # subtract fractions subu t2, t2, v0 # subtract barrow b norm_d 3: - move t0, t4 # sign of result = FTs - beq t8, zero, 1f # compute t6:t7:zero - t2:t3:t8 + move t0, ta4 # sign of result = FTs + beq t8, zero, 1f # compute ta6:ta7:zero - t2:t3:t8 subu t8, zero, t8 - sltu v0, t7, 1 # compute barrow out - subu t7, t7, 1 # subtract barrow - subu t6, t6, v0 + sltu v0, ta7, 1 # compute barrow out + subu ta7, ta7, 1 # subtract barrow + subu ta6, ta6, v0 1: - sltu v0, t7, t3 - subu t3, t7, t3 # subtract fractions - subu t2, t6, t2 # subtract fractions + sltu v0, ta7, t3 + subu t3, ta7, t3 # subtract fractions + subu t2, ta6, t2 # subtract fractions subu t2, t2, v0 # subtract barrow b norm_d @@ -924,22 +924,22 @@ add_sub_d: */ mul_s: jal get_ft_fs_s - xor t0, t0, t4 # compute sign of result - move t4, t0 + xor t0, t0, ta4 # compute sign of result + move ta4, t0 bne t1, SEXP_INF, 2f # is FS an infinity? bne t2, zero, result_fs_s # if FS is a NAN, result=FS - bne t5, SEXP_INF, 1f # FS is inf, is FT an infinity? - bne t6, zero, result_ft_s # if FT is a NAN, result=FT + bne ta5, SEXP_INF, 1f # FS is inf, is FT an infinity? + bne ta6, zero, result_ft_s # if FT is a NAN, result=FT b result_fs_s # result is infinity 1: - bne t5, zero, result_fs_s # inf * zero? if no, result=FS - bne t6, zero, result_fs_s + bne ta5, zero, result_fs_s # inf * zero? if no, result=FS + bne ta6, zero, result_fs_s b invalid_s # infinity * zero is invalid 2: - bne t5, SEXP_INF, 1f # FS != inf, is FT an infinity? + bne ta5, SEXP_INF, 1f # FS != inf, is FT an infinity? bne t1, zero, result_ft_s # zero * inf? if no, result=FT bne t2, zero, result_ft_s - bne t6, zero, result_ft_s # if FT is a NAN, result=FT + bne ta6, zero, result_ft_s # if FT is a NAN, result=FT b invalid_s # zero * infinity is invalid 1: bne t1, zero, 1f # is FS zero? @@ -950,17 +950,17 @@ mul_s: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit 2: - bne t5, zero, 1f # is FT zero? - beq t6, zero, result_ft_s # result is zero + bne ta5, zero, 1f # is FT zero? + beq ta6, zero, result_ft_s # result is zero jal renorm_ft_s b 2f 1: - subu t5, t5, SEXP_BIAS # unbias FT exponent - or t6, t6, SIMPL_ONE # set implied one bit + subu ta5, ta5, SEXP_BIAS # unbias FT exponent + or ta6, ta6, SIMPL_ONE # set implied one bit 2: - addu t1, t1, t5 # compute result exponent + addu t1, t1, ta5 # compute result exponent addu t1, t1, 9 # account for binary point - multu t2, t6 # multiply fractions + multu t2, ta6 # multiply fractions mflo t8 mfhi t2 b norm_s @@ -970,27 +970,27 @@ mul_s: */ mul_d: jal get_ft_fs_d - xor t0, t0, t4 # compute sign of result - move t4, t0 + xor t0, t0, ta4 # compute sign of result + move ta4, t0 bne t1, DEXP_INF, 2f # is FS an infinity? bne t2, zero, result_fs_d # if FS is a NAN, result=FS bne t3, zero, result_fs_d - bne t5, DEXP_INF, 1f # FS is inf, is FT an infinity? - bne t6, zero, result_ft_d # if FT is a NAN, result=FT - bne t7, zero, result_ft_d + bne ta5, DEXP_INF, 1f # FS is inf, is FT an infinity? + bne ta6, zero, result_ft_d # if FT is a NAN, result=FT + bne ta7, zero, result_ft_d b result_fs_d # result is infinity 1: - bne t5, zero, result_fs_d # inf * zero? if no, result=FS - bne t6, zero, result_fs_d - bne t7, zero, result_fs_d + bne ta5, zero, result_fs_d # inf * zero? if no, result=FS + bne ta6, zero, result_fs_d + bne ta7, zero, result_fs_d b invalid_d # infinity * zero is invalid 2: - bne t5, DEXP_INF, 1f # FS != inf, is FT an infinity? + bne ta5, DEXP_INF, 1f # FS != inf, is FT an infinity? bne t1, zero, result_ft_d # zero * inf? if no, result=FT bne t2, zero, result_ft_d # if FS is a NAN, result=FS bne t3, zero, result_ft_d - bne t6, zero, result_ft_d # if FT is a NAN, result=FT - bne t7, zero, result_ft_d + bne ta6, zero, result_ft_d # if FT is a NAN, result=FT + bne ta7, zero, result_ft_d b invalid_d # zero * infinity is invalid 1: bne t1, zero, 2f # is FS zero? @@ -1003,37 +1003,37 @@ mul_d: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit 3: - bne t5, zero, 2f # is FT zero? - bne t6, zero, 1f - beq t7, zero, result_ft_d # result is zero + bne ta5, zero, 2f # is FT zero? + bne ta6, zero, 1f + beq ta7, zero, result_ft_d # result is zero 1: jal renorm_ft_d b 3f 2: - subu t5, t5, DEXP_BIAS # unbias FT exponent - or t6, t6, DIMPL_ONE # set implied one bit + subu ta5, ta5, DEXP_BIAS # unbias FT exponent + or ta6, ta6, DIMPL_ONE # set implied one bit 3: - addu t1, t1, t5 # compute result exponent + addu t1, t1, ta5 # compute result exponent addu t1, t1, 12 # ??? - multu t3, t7 # multiply fractions (low * low) - move t4, t2 # free up t2,t3 for result - move t5, t3 + multu t3, ta7 # multiply fractions (low * low) + move ta4, t2 # free up t2,t3 for result + move ta5, t3 mflo a3 # save low order bits mfhi t8 not v0, t8 - multu t4, t7 # multiply FS(high) * FT(low) + multu ta4, ta7 # multiply FS(high) * FT(low) mflo v1 mfhi t3 # init low result sltu v0, v0, v1 # compute carry addu t8, v1 - multu t5, t6 # multiply FS(low) * FT(high) + multu ta5, ta6 # multiply FS(low) * FT(high) addu t3, t3, v0 # add carry not v0, t8 mflo v1 mfhi t2 sltu v0, v0, v1 addu t8, v1 - multu t4, t6 # multiply FS(high) * FT(high) + multu ta4, ta6 # multiply FS(high) * FT(high) addu t3, v0 not v1, t3 sltu v1, v1, t2 @@ -1054,24 +1054,24 @@ mul_d: */ div_s: jal get_ft_fs_s - xor t0, t0, t4 # compute sign of result - move t4, t0 + xor t0, t0, ta4 # compute sign of result + move ta4, t0 bne t1, SEXP_INF, 1f # is FS an infinity? bne t2, zero, result_fs_s # if FS is NAN, result is FS - bne t5, SEXP_INF, result_fs_s # is FT an infinity? - bne t6, zero, result_ft_s # if FT is NAN, result is FT + bne ta5, SEXP_INF, result_fs_s # is FT an infinity? + bne ta6, zero, result_ft_s # if FT is NAN, result is FT b invalid_s # infinity/infinity is invalid 1: - bne t5, SEXP_INF, 1f # is FT an infinity? - bne t6, zero, result_ft_s # if FT is NAN, result is FT + bne ta5, SEXP_INF, 1f # is FT an infinity? + bne ta6, zero, result_ft_s # if FT is NAN, result is FT move t1, zero # x / infinity is zero move t2, zero b result_fs_s 1: bne t1, zero, 2f # is FS zero? bne t2, zero, 1f - bne t5, zero, result_fs_s # FS=zero, is FT zero? - beq t6, zero, invalid_s # 0 / 0 + bne ta5, zero, result_fs_s # FS=zero, is FT zero? + beq ta6, zero, invalid_s # 0 / 0 b result_fs_s # result = zero 1: jal renorm_fs_s @@ -1080,8 +1080,8 @@ div_s: subu t1, t1, SEXP_BIAS # unbias FS exponent or t2, t2, SIMPL_ONE # set implied one bit 3: - bne t5, zero, 2f # is FT zero? - bne t6, zero, 1f + bne ta5, zero, 2f # is FT zero? + bne ta6, zero, 1f or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap @@ -1093,18 +1093,18 @@ div_s: jal renorm_ft_s b 3f 2: - subu t5, t5, SEXP_BIAS # unbias FT exponent - or t6, t6, SIMPL_ONE # set implied one bit + subu ta5, ta5, SEXP_BIAS # unbias FT exponent + or ta6, ta6, SIMPL_ONE # set implied one bit 3: - subu t1, t1, t5 # compute exponent + subu t1, t1, ta5 # compute exponent subu t1, t1, 3 # compensate for result position li v0, SFRAC_BITS+3 # number of bits to divide move t8, t2 # init dividend move t2, zero # init result 1: - bltu t8, t6, 3f # is dividend >= divisor? + bltu t8, ta6, 3f # is dividend >= divisor? 2: - subu t8, t8, t6 # subtract divisor from dividend + subu t8, t8, ta6 # subtract divisor from dividend or t2, t2, 1 # remember that we did bne t8, zero, 3f # if not done, continue sll t2, t2, v0 # shift result to final position @@ -1121,19 +1121,19 @@ div_s: */ div_d: jal get_ft_fs_d - xor t0, t0, t4 # compute sign of result - move t4, t0 + xor t0, t0, ta4 # compute sign of result + move ta4, t0 bne t1, DEXP_INF, 1f # is FS an infinity? bne t2, zero, result_fs_d # if FS is NAN, result is FS bne t3, zero, result_fs_d - bne t5, DEXP_INF, result_fs_d # is FT an infinity? - bne t6, zero, result_ft_d # if FT is NAN, result is FT - bne t7, zero, result_ft_d + bne ta5, DEXP_INF, result_fs_d # is FT an infinity? + bne ta6, zero, result_ft_d # if FT is NAN, result is FT + bne ta7, zero, result_ft_d b invalid_d # infinity/infinity is invalid 1: - bne t5, DEXP_INF, 1f # is FT an infinity? - bne t6, zero, result_ft_d # if FT is NAN, result is FT - bne t7, zero, result_ft_d + bne ta5, DEXP_INF, 1f # is FT an infinity? + bne ta6, zero, result_ft_d # if FT is NAN, result is FT + bne ta7, zero, result_ft_d move t1, zero # x / infinity is zero move t2, zero move t3, zero @@ -1142,9 +1142,9 @@ div_d: bne t1, zero, 2f # is FS zero? bne t2, zero, 1f bne t3, zero, 1f - bne t5, zero, result_fs_d # FS=zero, is FT zero? - bne t6, zero, result_fs_d - beq t7, zero, invalid_d # 0 / 0 + bne ta5, zero, result_fs_d # FS=zero, is FT zero? + bne ta6, zero, result_fs_d + beq ta7, zero, invalid_d # 0 / 0 b result_fs_d # result = zero 1: jal renorm_fs_d @@ -1153,9 +1153,9 @@ div_d: subu t1, t1, DEXP_BIAS # unbias FS exponent or t2, t2, DIMPL_ONE # set implied one bit 3: - bne t5, zero, 2f # is FT zero? - bne t6, zero, 1f - bne t7, zero, 1f + bne ta5, zero, 2f # is FT zero? + bne ta6, zero, 1f + bne ta7, zero, 1f or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 and v0, a1, FPC_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap @@ -1168,10 +1168,10 @@ div_d: jal renorm_ft_d b 3f 2: - subu t5, t5, DEXP_BIAS # unbias FT exponent - or t6, t6, DIMPL_ONE # set implied one bit + subu ta5, ta5, DEXP_BIAS # unbias FT exponent + or ta6, ta6, DIMPL_ONE # set implied one bit 3: - subu t1, t1, t5 # compute exponent + subu t1, t1, ta5 # compute exponent subu t1, t1, 3 # compensate for result position li v0, DFRAC_BITS+3 # number of bits to divide move t8, t2 # init dividend @@ -1179,13 +1179,13 @@ div_d: move t2, zero # init result move t3, zero 1: - bltu t8, t6, 3f # is dividend >= divisor? - bne t8, t6, 2f - bltu t9, t7, 3f + bltu t8, ta6, 3f # is dividend >= divisor? + bne t8, ta6, 2f + bltu t9, ta7, 3f 2: - sltu v1, t9, t7 # subtract divisor from dividend - subu t9, t9, t7 - subu t8, t8, t6 + sltu v1, t9, ta7 # subtract divisor from dividend + subu t9, t9, ta7 + subu t8, t8, ta6 subu t8, t8, v1 or t3, t3, 1 # remember that we did bne t8, zero, 3f # if not done, continue @@ -1580,23 +1580,23 @@ cmp_s: bne t1, SEXP_INF, 1f # is FS an infinity? bne t2, zero, unordered # FS is a NAN 1: - bne t5, SEXP_INF, 2f # is FT an infinity? - bne t6, zero, unordered # FT is a NAN + bne ta5, SEXP_INF, 2f # is FT an infinity? + bne ta6, zero, unordered # FT is a NAN 2: sll t1, t1, 23 # reassemble exp & frac or t1, t1, t2 - sll t5, t5, 23 # reassemble exp & frac - or t5, t5, t6 + sll ta5, ta5, 23 # reassemble exp & frac + or ta5, ta5, ta6 beq t0, zero, 1f # is FS positive? negu t1 1: - beq t4, zero, 1f # is FT positive? - negu t5 + beq ta4, zero, 1f # is FT positive? + negu ta5 1: li v0, COND_LESS - blt t1, t5, test_cond # is FS < FT? + blt t1, ta5, test_cond # is FS < FT? li v0, COND_EQUAL - beq t1, t5, test_cond # is FS == FT? + beq t1, ta5, test_cond # is FS == FT? move v0, zero # FS > FT b test_cond @@ -1609,14 +1609,14 @@ cmp_d: bne t2, zero, unordered bne t3, zero, unordered # FS is a NAN 1: - bne t5, DEXP_INF, 2f # is FT an infinity? - bne t6, zero, unordered - bne t7, zero, unordered # FT is a NAN + bne ta5, DEXP_INF, 2f # is FT an infinity? + bne ta6, zero, unordered + bne ta7, zero, unordered # FT is a NAN 2: sll t1, t1, 20 # reassemble exp & frac or t1, t1, t2 - sll t5, t5, 20 # reassemble exp & frac - or t5, t5, t6 + sll ta5, ta5, 20 # reassemble exp & frac + or ta5, ta5, ta6 beq t0, zero, 1f # is FS positive? not t3 # negate t1,t3 not t1 @@ -1624,21 +1624,21 @@ cmp_d: seq v0, t3, zero # compute carry addu t1, t1, v0 1: - beq t4, zero, 1f # is FT positive? - not t7 # negate t5,t7 - not t5 - addu t7, t7, 1 - seq v0, t7, zero # compute carry - addu t5, t5, v0 + beq ta4, zero, 1f # is FT positive? + not ta7 # negate ta5,ta7 + not ta5 + addu ta7, ta7, 1 + seq v0, ta7, zero # compute carry + addu ta5, ta5, v0 1: li v0, COND_LESS - blt t1, t5, test_cond # is FS(MSW) < FT(MSW)? + blt t1, ta5, test_cond # is FS(MSW) < FT(MSW)? move v0, zero - bne t1, t5, test_cond # is FS(MSW) > FT(MSW)? + bne t1, ta5, test_cond # is FS(MSW) > FT(MSW)? li v0, COND_LESS - bltu t3, t7, test_cond # is FS(LSW) < FT(LSW)? + bltu t3, ta7, test_cond # is FS(LSW) < FT(LSW)? li v0, COND_EQUAL - beq t3, t7, test_cond # is FS(LSW) == FT(LSW)? + beq t3, ta7, test_cond # is FS(LSW) == FT(LSW)? move v0, zero # FS > FT test_cond: and v0, v0, a0 # condition match instruction? @@ -1729,8 +1729,8 @@ norm_s: or t8, t8, v0 srl t2, t2, t9 norm_noshift_s: - move t5, t1 # save unrounded exponent - move t6, t2 # save unrounded fraction + move ta5, t1 # save unrounded exponent + move ta6, t2 # save unrounded fraction and v0, a1, FPC_ROUNDING_BITS # get rounding mode beq v0, FPC_ROUND_RN, 3f # round to nearest beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) @@ -1830,8 +1830,8 @@ underflow_s: * signal inexact result (if it is) and trap (if enabled). */ 1: - move t1, t5 # get unrounded exponent - move t2, t6 # get unrounded fraction + move t1, ta5 # get unrounded exponent + move t2, ta6 # get unrounded fraction li t9, SEXP_MIN # compute shift amount subu t9, t9, t1 # shift t2,t8 right by t9 blt t9, SFRAC_BITS+2, 3f # shift all the bits out? @@ -1974,9 +1974,9 @@ norm_d: or t3, t3, v0 srl t2, t2, t9 norm_noshift_d: - move t5, t1 # save unrounded exponent - move t6, t2 # save unrounded fraction (MS) - move t7, t3 # save unrounded fraction (LS) + move ta5, t1 # save unrounded exponent + move ta6, t2 # save unrounded fraction (MS) + move ta7, t3 # save unrounded fraction (LS) and v0, a1, FPC_ROUNDING_BITS # get rounding mode beq v0, FPC_ROUND_RN, 3f # round to nearest beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) @@ -2082,9 +2082,9 @@ underflow_d: * signal inexact result (if it is) and trap (if enabled). */ 1: - move t1, t5 # get unrounded exponent - move t2, t6 # get unrounded fraction (MS) - move t3, t7 # get unrounded fraction (LS) + move t1, ta5 # get unrounded exponent + move t2, ta6 # get unrounded fraction (MS) + move t3, ta7 # get unrounded fraction (LS) li t9, DEXP_MIN # compute shift amount subu t9, t9, t1 # shift t2,t8 right by t9 blt t9, DFRAC_BITS+2, 3f # shift all the bits out? @@ -2233,9 +2233,9 @@ ill: b done_err result_ft_s: - move t0, t4 # result is FT - move t1, t5 - move t2, t6 + move t0, ta4 # result is FT + move t1, ta5 + move t2, ta6 result_fs_s: # result is FS jal set_fd_s # save result (in t0,t1,t2) b done @@ -2245,10 +2245,10 @@ result_fs_w: b done result_ft_d: - move t0, t4 # result is FT - move t1, t5 - move t2, t6 - move t3, t7 + move t0, ta4 # result is FT + move t1, ta5 + move t2, ta6 + move t3, ta7 result_fs_d: # result is FS jal set_fd_d # save result (in t0,t1,t2,t3) @@ -2364,9 +2364,9 @@ END(get_fs_int) * t0 contains the FS sign * t1 contains the FS (biased) exponent * t2 contains the FS fraction - * t4 contains the FT sign - * t5 contains the FT (biased) exponent - * t6 contains the FT fraction + * ta4 contains the FT sign + * ta5 contains the FT (biased) exponent + * ta6 contains the FT fraction * *---------------------------------------------------------------------------- */ @@ -2397,59 +2397,59 @@ get_ft_s_tbl: .text get_ft_s_f0: - mfc1 t4, $f0 + mfc1 ta4, $f0 b get_ft_s_done get_ft_s_f2: - mfc1 t4, $f2 + mfc1 ta4, $f2 b get_ft_s_done get_ft_s_f4: - mfc1 t4, $f4 + mfc1 ta4, $f4 b get_ft_s_done get_ft_s_f6: - mfc1 t4, $f6 + mfc1 ta4, $f6 b get_ft_s_done get_ft_s_f8: - mfc1 t4, $f8 + mfc1 ta4, $f8 b get_ft_s_done get_ft_s_f10: - mfc1 t4, $f10 + mfc1 ta4, $f10 b get_ft_s_done get_ft_s_f12: - mfc1 t4, $f12 + mfc1 ta4, $f12 b get_ft_s_done get_ft_s_f14: - mfc1 t4, $f14 + mfc1 ta4, $f14 b get_ft_s_done get_ft_s_f16: - mfc1 t4, $f16 + mfc1 ta4, $f16 b get_ft_s_done get_ft_s_f18: - mfc1 t4, $f18 + mfc1 ta4, $f18 b get_ft_s_done get_ft_s_f20: - mfc1 t4, $f20 + mfc1 ta4, $f20 b get_ft_s_done get_ft_s_f22: - mfc1 t4, $f22 + mfc1 ta4, $f22 b get_ft_s_done get_ft_s_f24: - mfc1 t4, $f24 + mfc1 ta4, $f24 b get_ft_s_done get_ft_s_f26: - mfc1 t4, $f26 + mfc1 ta4, $f26 b get_ft_s_done get_ft_s_f28: - mfc1 t4, $f28 + mfc1 ta4, $f28 b get_ft_s_done get_ft_s_f30: - mfc1 t4, $f30 + mfc1 ta4, $f30 get_ft_s_done: - srl t5, t4, 23 # get exponent - and t5, t5, 0xFF - and t6, t4, 0x7FFFFF # get fraction - srl t4, t4, 31 # get sign - bne t5, SEXP_INF, 1f # is it a signaling NAN? - and v0, t6, SSIGNAL_NAN + srl ta5, ta4, 23 # get exponent + and ta5, ta5, 0xFF + and ta6, ta4, 0x7FFFFF # get fraction + srl ta4, ta4, 31 # get sign + bne ta5, SEXP_INF, 1f # is it a signaling NAN? + and v0, ta6, SSIGNAL_NAN bne v0, zero, invalid_s 1: /* fall through to get FS */ @@ -2565,10 +2565,10 @@ END(get_ft_fs_s) * t1 contains the FS (biased) exponent * t2 contains the FS fraction * t3 contains the FS remaining fraction - * t4 contains the FT sign - * t5 contains the FT (biased) exponent - * t6 contains the FT fraction - * t7 contains the FT remaining fraction + * ta4 contains the FT sign + * ta5 contains the FT (biased) exponent + * ta6 contains the FT fraction + * ta7 contains the FT remaining fraction * *---------------------------------------------------------------------------- */ @@ -2599,75 +2599,75 @@ get_ft_d_tbl: .text get_ft_d_f0: - mfc1 t7, $f0 - mfc1 t4, $f1 + mfc1 ta7, $f0 + mfc1 ta4, $f1 b get_ft_d_done get_ft_d_f2: - mfc1 t7, $f2 - mfc1 t4, $f3 + mfc1 ta7, $f2 + mfc1 ta4, $f3 b get_ft_d_done get_ft_d_f4: - mfc1 t7, $f4 - mfc1 t4, $f5 + mfc1 ta7, $f4 + mfc1 ta4, $f5 b get_ft_d_done get_ft_d_f6: - mfc1 t7, $f6 - mfc1 t4, $f7 + mfc1 ta7, $f6 + mfc1 ta4, $f7 b get_ft_d_done get_ft_d_f8: - mfc1 t7, $f8 - mfc1 t4, $f9 + mfc1 ta7, $f8 + mfc1 ta4, $f9 b get_ft_d_done get_ft_d_f10: - mfc1 t7, $f10 - mfc1 t4, $f11 + mfc1 ta7, $f10 + mfc1 ta4, $f11 b get_ft_d_done get_ft_d_f12: - mfc1 t7, $f12 - mfc1 t4, $f13 + mfc1 ta7, $f12 + mfc1 ta4, $f13 b get_ft_d_done get_ft_d_f14: - mfc1 t7, $f14 - mfc1 t4, $f15 + mfc1 ta7, $f14 + mfc1 ta4, $f15 b get_ft_d_done get_ft_d_f16: - mfc1 t7, $f16 - mfc1 t4, $f17 + mfc1 ta7, $f16 + mfc1 ta4, $f17 b get_ft_d_done get_ft_d_f18: - mfc1 t7, $f18 - mfc1 t4, $f19 + mfc1 ta7, $f18 + mfc1 ta4, $f19 b get_ft_d_done get_ft_d_f20: - mfc1 t7, $f20 - mfc1 t4, $f21 + mfc1 ta7, $f20 + mfc1 ta4, $f21 b get_ft_d_done get_ft_d_f22: - mfc1 t7, $f22 - mfc1 t4, $f23 + mfc1 ta7, $f22 + mfc1 ta4, $f23 b get_ft_d_done get_ft_d_f24: - mfc1 t7, $f24 - mfc1 t4, $f25 + mfc1 ta7, $f24 + mfc1 ta4, $f25 b get_ft_d_done get_ft_d_f26: - mfc1 t7, $f26 - mfc1 t4, $f27 + mfc1 ta7, $f26 + mfc1 ta4, $f27 b get_ft_d_done get_ft_d_f28: - mfc1 t7, $f28 - mfc1 t4, $f29 + mfc1 ta7, $f28 + mfc1 ta4, $f29 b get_ft_d_done get_ft_d_f30: - mfc1 t7, $f30 - mfc1 t4, $f31 + mfc1 ta7, $f30 + mfc1 ta4, $f31 get_ft_d_done: - srl t5, t4, 20 # get exponent - and t5, t5, 0x7FF - and t6, t4, 0xFFFFF # get fraction - srl t4, t4, 31 # get sign - bne t5, DEXP_INF, 1f # is it a signaling NAN? - and v0, t6, DSIGNAL_NAN + srl ta5, ta4, 20 # get exponent + and ta5, ta5, 0x7FF + and ta6, ta4, 0xFFFFF # get fraction + srl ta4, ta4, 31 # get sign + bne ta5, DEXP_INF, 1f # is it a signaling NAN? + and v0, ta6, DSIGNAL_NAN bne v0, zero, invalid_d 1: /* fall through to get FS */ @@ -2799,9 +2799,9 @@ END(get_ft_fs_d) * t0 contains the sign * t1 contains the (biased) exponent * t2 contains the fraction - * t4 contains the sign - * t5 contains the (biased) exponent - * t6 contains the fraction + * ta4 contains the sign + * ta5 contains the (biased) exponent + * ta6 contains the fraction * *---------------------------------------------------------------------------- */ @@ -2910,57 +2910,57 @@ cmp_ft_s_tbl: .text cmp_ft_s_f0: - mfc1 t4, $f0 + mfc1 ta4, $f0 b cmp_ft_s_done cmp_ft_s_f2: - mfc1 t4, $f2 + mfc1 ta4, $f2 b cmp_ft_s_done cmp_ft_s_f4: - mfc1 t4, $f4 + mfc1 ta4, $f4 b cmp_ft_s_done cmp_ft_s_f6: - mfc1 t4, $f6 + mfc1 ta4, $f6 b cmp_ft_s_done cmp_ft_s_f8: - mfc1 t4, $f8 + mfc1 ta4, $f8 b cmp_ft_s_done cmp_ft_s_f10: - mfc1 t4, $f10 + mfc1 ta4, $f10 b cmp_ft_s_done cmp_ft_s_f12: - mfc1 t4, $f12 + mfc1 ta4, $f12 b cmp_ft_s_done cmp_ft_s_f14: - mfc1 t4, $f14 + mfc1 ta4, $f14 b cmp_ft_s_done cmp_ft_s_f16: - mfc1 t4, $f16 + mfc1 ta4, $f16 b cmp_ft_s_done cmp_ft_s_f18: - mfc1 t4, $f18 + mfc1 ta4, $f18 b cmp_ft_s_done cmp_ft_s_f20: - mfc1 t4, $f20 + mfc1 ta4, $f20 b cmp_ft_s_done cmp_ft_s_f22: - mfc1 t4, $f22 + mfc1 ta4, $f22 b cmp_ft_s_done cmp_ft_s_f24: - mfc1 t4, $f24 + mfc1 ta4, $f24 b cmp_ft_s_done cmp_ft_s_f26: - mfc1 t4, $f26 + mfc1 ta4, $f26 b cmp_ft_s_done cmp_ft_s_f28: - mfc1 t4, $f28 + mfc1 ta4, $f28 b cmp_ft_s_done cmp_ft_s_f30: - mfc1 t4, $f30 + mfc1 ta4, $f30 cmp_ft_s_done: - srl t5, t4, 23 # get exponent - and t5, t5, 0xFF - and t6, t4, 0x7FFFFF # get fraction - srl t4, t4, 31 # get sign + srl ta5, ta4, 23 # get exponent + and ta5, ta5, 0xFF + and ta6, ta4, 0x7FFFFF # get fraction + srl ta4, ta4, 31 # get sign j ra END(get_cmp_s) @@ -2976,10 +2976,10 @@ END(get_cmp_s) * t1 contains the (biased) exponent * t2 contains the fraction * t3 contains the remaining fraction - * t4 contains the sign - * t5 contains the (biased) exponent - * t6 contains the fraction - * t7 contains the remaining fraction + * ta4 contains the sign + * ta5 contains the (biased) exponent + * ta6 contains the fraction + * ta7 contains the remaining fraction * *---------------------------------------------------------------------------- */ @@ -3104,73 +3104,73 @@ cmp_ft_d_tbl: .text cmp_ft_d_f0: - mfc1 t7, $f0 - mfc1 t4, $f1 + mfc1 ta7, $f0 + mfc1 ta4, $f1 b cmp_ft_d_done cmp_ft_d_f2: - mfc1 t7, $f2 - mfc1 t4, $f3 + mfc1 ta7, $f2 + mfc1 ta4, $f3 b cmp_ft_d_done cmp_ft_d_f4: - mfc1 t7, $f4 - mfc1 t4, $f5 + mfc1 ta7, $f4 + mfc1 ta4, $f5 b cmp_ft_d_done cmp_ft_d_f6: - mfc1 t7, $f6 - mfc1 t4, $f7 + mfc1 ta7, $f6 + mfc1 ta4, $f7 b cmp_ft_d_done cmp_ft_d_f8: - mfc1 t7, $f8 - mfc1 t4, $f9 + mfc1 ta7, $f8 + mfc1 ta4, $f9 b cmp_ft_d_done cmp_ft_d_f10: - mfc1 t7, $f10 - mfc1 t4, $f11 + mfc1 ta7, $f10 + mfc1 ta4, $f11 b cmp_ft_d_done cmp_ft_d_f12: - mfc1 t7, $f12 - mfc1 t4, $f13 + mfc1 ta7, $f12 + mfc1 ta4, $f13 b cmp_ft_d_done cmp_ft_d_f14: - mfc1 t7, $f14 - mfc1 t4, $f15 + mfc1 ta7, $f14 + mfc1 ta4, $f15 b cmp_ft_d_done cmp_ft_d_f16: - mfc1 t7, $f16 - mfc1 t4, $f17 + mfc1 ta7, $f16 + mfc1 ta4, $f17 b cmp_ft_d_done cmp_ft_d_f18: - mfc1 t7, $f18 - mfc1 t4, $f19 + mfc1 ta7, $f18 + mfc1 ta4, $f19 b cmp_ft_d_done cmp_ft_d_f20: - mfc1 t7, $f20 - mfc1 t4, $f21 + mfc1 ta7, $f20 + mfc1 ta4, $f21 b cmp_ft_d_done cmp_ft_d_f22: - mfc1 t7, $f22 - mfc1 t4, $f23 + mfc1 ta7, $f22 + mfc1 ta4, $f23 b cmp_ft_d_done cmp_ft_d_f24: - mfc1 t7, $f24 - mfc1 t4, $f25 + mfc1 ta7, $f24 + mfc1 ta4, $f25 b cmp_ft_d_done cmp_ft_d_f26: - mfc1 t7, $f26 - mfc1 t4, $f27 + mfc1 ta7, $f26 + mfc1 ta4, $f27 b cmp_ft_d_done cmp_ft_d_f28: - mfc1 t7, $f28 - mfc1 t4, $f29 + mfc1 ta7, $f28 + mfc1 ta4, $f29 b cmp_ft_d_done cmp_ft_d_f30: - mfc1 t7, $f30 - mfc1 t4, $f31 + mfc1 ta7, $f30 + mfc1 ta4, $f31 cmp_ft_d_done: - srl t5, t4, 20 # get exponent - and t5, t5, 0x7FF - and t6, t4, 0xFFFFF # get fraction - srl t4, t4, 31 # get sign + srl ta5, ta4, 20 # get exponent + and ta5, ta5, 0x7FF + and ta6, ta4, 0xFFFFF # get fraction + srl ta4, ta4, 31 # get sign j ra END(get_cmp_d) @@ -3506,16 +3506,16 @@ END(renorm_fs_d) * renorm_ft_s -- * * Results: - * t5 unbiased exponent - * t6 normalized fraction + * ta5 unbiased exponent + * ta6 normalized fraction * *---------------------------------------------------------------------------- */ LEAF(renorm_ft_s) /* - * Find out how many leading zero bits are in t6 and put in t9. + * Find out how many leading zero bits are in ta6 and put in t9. */ - move v0, t6 + move v0, ta6 move t9, zero srl v1, v0, 16 bne v1, zero, 1f @@ -3541,13 +3541,13 @@ LEAF(renorm_ft_s) bne v1, zero, 1f addu t9, 1 /* - * Now shift t6 the correct number of bits. + * Now shift ta6 the correct number of bits. */ 1: subu t9, t9, SLEAD_ZEROS # dont count normal leading zeros - li t5, SEXP_MIN - subu t5, t5, t9 # adjust exponent - sll t6, t6, t9 + li ta5, SEXP_MIN + subu ta5, ta5, t9 # adjust exponent + sll ta6, ta6, t9 j ra END(renorm_ft_s) @@ -3555,19 +3555,19 @@ END(renorm_ft_s) * renorm_ft_d -- * * Results: - * t5 unbiased exponent - * t6,t7 normalized fraction + * ta5 unbiased exponent + * ta6,ta7 normalized fraction * *---------------------------------------------------------------------------- */ LEAF(renorm_ft_d) /* - * Find out how many leading zero bits are in t6,t7 and put in t9. + * Find out how many leading zero bits are in ta6,ta7 and put in t9. */ - move v0, t6 + move v0, ta6 move t9, zero - bne t6, zero, 1f - move v0, t7 + bne ta6, zero, 1f + move v0, ta7 addu t9, 32 1: srl v1, v0, 16 @@ -3594,23 +3594,23 @@ LEAF(renorm_ft_d) bne v1, zero, 1f addu t9, 1 /* - * Now shift t6,t7 the correct number of bits. + * Now shift ta6,ta7 the correct number of bits. */ 1: subu t9, t9, DLEAD_ZEROS # dont count normal leading zeros - li t5, DEXP_MIN - subu t5, t5, t9 # adjust exponent + li ta5, DEXP_MIN + subu ta5, ta5, t9 # adjust exponent li v0, 32 blt t9, v0, 1f subu t9, t9, v0 # shift fraction left >= 32 bits - sll t6, t7, t9 - move t7, zero + sll ta6, ta7, t9 + move ta7, zero j ra 1: subu v0, v0, t9 # shift fraction left < 32 bits - sll t6, t6, t9 - srl v1, t7, v0 - or t6, t6, v1 - sll t7, t7, t9 + sll ta6, ta6, t9 + srl v1, ta7, v0 + or ta6, ta6, v1 + sll ta7, ta7, t9 j ra END(renorm_ft_d) diff --git a/sys/arch/mips64/mips64/lcore_access.S b/sys/arch/mips64/mips64/lcore_access.S index d1c5662d76a..9d337aa67cf 100644 --- a/sys/arch/mips64/mips64/lcore_access.S +++ b/sys/arch/mips64/mips64/lcore_access.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_access.S,v 1.4 2004/08/10 20:15:47 deraadt Exp $ */ +/* $OpenBSD: lcore_access.S,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -60,8 +60,8 @@ onfault_table: PTR_VAL 0 # invalid index number PTR_VAL baderr - PTR_VAL copyerr - PTR_VAL copyerr + PTR_VAL _copyerr + PTR_VAL _copyerr #if defined(DDB) || defined(DEBUG) PTR_VAL kt_ddberr #else @@ -155,8 +155,10 @@ LEAF(copystr) move v0, zero END(copystr) +#ifndef __LP64__ /* * Read 64 bits from bus in non LP64 mode. + * XXX ints should be disabled! */ LEAF(lp32_read8) #if defined(__MIPSEB__) @@ -172,6 +174,7 @@ END(lp32_read8) /* * Write 64 bits to bus in non LP64 mode. + * XXX ints should be disabled! */ LEAF(lp32_write8) #if defined(__MIPSEB__) @@ -188,6 +191,7 @@ LEAF(lp32_write8) jr ra sd a2, 0(a0) END(lp32_write8) +#endif /* * fillw(pat, addr, count) @@ -345,7 +349,7 @@ NON_LEAF(copyinstr, FRAMESZ(CF_SZ), ra) PTR_SUBU sp, sp, FRAMESZ(CF_SZ) .mask 0x80000000, (CF_RA_OFFS - FRAMESZ(CF_SZ)) PTR_S ra, CF_RA_OFFS(sp) - blt a0, zero, copyerr # make sure address is in user space + blt a0, zero, _copyerr # make sure address is in user space li v0, KT_COPYERR PTR_L t3, curprocpaddr jal copystr @@ -373,7 +377,7 @@ NON_LEAF(copyoutstr, FRAMESZ(CF_SZ), ra) PTR_SUBU sp, sp, FRAMESZ(CF_SZ) .mask 0x80000000, (CF_RA_OFFS - FRAMESZ(CF_SZ)) PTR_S ra, CF_RA_OFFS(sp) - blt a1, zero, copyerr # make sure address is in user space + blt a1, zero, _copyerr # make sure address is in user space li v0, KT_COPYERR PTR_L t3, curprocpaddr jal copystr @@ -398,7 +402,7 @@ NON_LEAF(copyin, FRAMESZ(CF_SZ), ra) PTR_SUBU sp, sp, FRAMESZ(CF_SZ) .mask 0x80000000, (CF_RA_OFFS - FRAMESZ(CF_SZ)) PTR_S ra, CF_RA_OFFS(sp) - blt a0, zero, copyerr # make sure address is in user space + blt a0, zero, _copyerr # make sure address is in user space li v0, KT_COPYERR PTR_L t3, curprocpaddr jal bcopy @@ -423,7 +427,7 @@ NON_LEAF(copyout, FRAMESZ(CF_SZ), ra) PTR_SUBU sp, sp, FRAMESZ(CF_SZ) .mask 0x80000000, (CF_RA_OFFS - FRAMESZ(CF_SZ)) PTR_S ra, CF_RA_OFFS(sp) - blt a1, zero, copyerr # make sure address is in user space + blt a1, zero, _copyerr # make sure address is in user space li v0, KT_COPYERR PTR_L t3, curprocpaddr jal bcopy @@ -437,14 +441,13 @@ NON_LEAF(copyout, FRAMESZ(CF_SZ), ra) move v0, zero END(copyout) -LEAF(copyerr) +_copyerr: PTR_L ra, CF_RA_OFFS(sp) PTR_L t3, curprocpaddr sw zero, U_PCB_ONFAULT(t3) PTR_ADDU sp, sp, FRAMESZ(CF_SZ) j ra li v0, EFAULT # return error -END(copyerr) /* * kcopy is a wrapper around bcopy that catches bad memory references. diff --git a/sys/arch/mips64/mips64/lcore_float.S b/sys/arch/mips64/mips64/lcore_float.S index d9c4c042e5b..65b68ddfef2 100644 --- a/sys/arch/mips64/mips64/lcore_float.S +++ b/sys/arch/mips64/mips64/lcore_float.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_float.S,v 1.4 2004/08/15 18:35:58 pefo Exp $ */ +/* $OpenBSD: lcore_float.S,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -78,10 +78,10 @@ LEAF(MipsSwitchFPState) cfc1 t0, FPC_CSR # stall til FP done cfc1 t0, FPC_CSR # now get status li t3, ~SR_COP_1_BIT - lw t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register - sw t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status + REG_L t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register + REG_S t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status and t2, t2, t3 # clear COP_1 enable bit - sw t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register + REG_S t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register /* * Save the floating point registers. */ @@ -122,7 +122,7 @@ LEAF(MipsSwitchFPState) /* * Restore the floating point registers. */ - lw t0, U_PCB_FPREGS+(32 * REGSZ)(a1) # get status register + REG_L t0, U_PCB_FPREGS+(32 * REGSZ)(a1) # get status register ldc1 $f0, U_PCB_FPREGS+(0 * REGSZ)(a1) ldc1 $f1, U_PCB_FPREGS+(1 * REGSZ)(a1) ldc1 $f2, U_PCB_FPREGS+(2 * REGSZ)(a1) @@ -182,10 +182,10 @@ LEAF(MipsSwitchFPState16) cfc1 t0, FPC_CSR # stall til FP done cfc1 t0, FPC_CSR # now get status li t3, ~SR_COP_1_BIT - lw t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register - sw t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status + REG_L t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register + REG_S t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status and t2, t2, t3 # clear COP_1 enable bit - sw t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register + REG_S t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register /* * Save the floating point registers. */ @@ -226,7 +226,7 @@ LEAF(MipsSwitchFPState16) /* * Restore the floating point registers. */ - lw t0, U_PCB_FPREGS+(32 * REGSZ)(a1) # get status register + REG_L t0, U_PCB_FPREGS+(32 * REGSZ)(a1) # get status register lwc1 $f0, U_PCB_FPREGS+(0 * REGSZ)(a1) lwc1 $f1, U_PCB_FPREGS+(1 * REGSZ)(a1) lwc1 $f2, U_PCB_FPREGS+(2 * REGSZ)(a1) @@ -288,7 +288,7 @@ END(MipsSwitchFPState16) *---------------------------------------------------------------------------- */ LEAF(MipsSaveCurFPState) - lw a0, P_ADDR(a0) # get pointer to pcb for proc + PTR_L a0, P_ADDR(a0) # get pointer to pcb for proc mfc0 t1, COP_0_STATUS_REG # Disable interrupts and li t0, SR_COP_1_BIT|SR_FR_32 # enable the coprocessor mtc0 t0, COP_0_STATUS_REG @@ -298,13 +298,13 @@ LEAF(MipsSaveCurFPState) * First read out the status register to make sure that all FP operations * have completed. */ - lw t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register + REG_L t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register li t3, ~SR_COP_1_BIT and t2, t2, t3 # clear COP_1 enable bit cfc1 t0, FPC_CSR # stall til FP done cfc1 t0, FPC_CSR # now get status - sw t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register - sw t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status + REG_S t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register + REG_S t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status /* * Save the floating point registers. */ @@ -348,7 +348,7 @@ LEAF(MipsSaveCurFPState) END(MipsSaveCurFPState) LEAF(MipsSaveCurFPState16) - lw a0, P_ADDR(a0) # get pointer to pcb for proc + PTR_L a0, P_ADDR(a0) # get pointer to pcb for proc mfc0 t1, COP_0_STATUS_REG # Disable interrupts and li t0, SR_COP_1_BIT # enable the coprocessor mtc0 t0, COP_0_STATUS_REG @@ -358,13 +358,13 @@ LEAF(MipsSaveCurFPState16) * First read out the status register to make sure that all FP operations * have completed. */ - lw t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register + REG_L t2, U_PCB_REGS+(PS * REGSZ)(a0) # get CPU status register li t3, ~SR_COP_1_BIT and t2, t2, t3 # clear COP_1 enable bit cfc1 t0, FPC_CSR # stall til FP done cfc1 t0, FPC_CSR # now get status - sw t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register - sw t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status + REG_S t2, U_PCB_REGS+(PS * REGSZ)(a0) # save new status register + REG_S t0, U_PCB_FPREGS+(32 * REGSZ)(a0) # save FP status /* * Save the floating point registers. */ diff --git a/sys/arch/mips64/mips64/mem.c b/sys/arch/mips64/mips64/mem.c index 0fd86f4ad91..cf18f53cfd0 100644 --- a/sys/arch/mips64/mips64/mem.c +++ b/sys/arch/mips64/mips64/mem.c @@ -1,4 +1,4 @@ -/* $OpenBSD: mem.c,v 1.4 2004/08/11 15:13:58 deraadt Exp $ */ +/* $OpenBSD: mem.c,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* $NetBSD: mem.c,v 1.6 1995/04/10 11:55:03 mycroft Exp $ */ /* @@ -134,7 +134,7 @@ mmrw(dev_t dev, struct uio *uio, int flags) c = iov->iov_len; if (v + c > ctob(physmem)) return (EFAULT); - v += KSEG0_BASE; + v = (vaddr_t)PHYS_TO_KSEG0(v); error = uiomove((caddr_t)v, c, uio); continue; diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c index 5031afd40f1..570bf5fd668 100644 --- a/sys/arch/mips64/mips64/pmap.c +++ b/sys/arch/mips64/mips64/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.6 2004/08/15 18:35:12 pefo Exp $ */ +/* $OpenBSD: pmap.c,v 1.7 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -1362,12 +1362,12 @@ pmap_copy_page(struct vm_page *srcpg, struct vm_page *dstpg) pv = pa_to_pvh(src); if (pv->pv_flags & PV_CACHED && - (sf = ((pv->pv_va ^ (int)s) & CpuCacheAliasMask) != 0)) { + (sf = ((pv->pv_va ^ (long)s) & CpuCacheAliasMask) != 0)) { Mips_SyncDCachePage(pv->pv_va); } pv = pa_to_pvh(dst); if (pv->pv_flags & PV_CACHED && - (df = ((pv->pv_va ^ (int)d) & CpuCacheAliasMask) != 0)) { + (df = ((pv->pv_va ^ (long)d) & CpuCacheAliasMask) != 0)) { Mips_SyncDCachePage(pv->pv_va); } diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S index 2ce86b1545e..32e68f4d319 100644 --- a/sys/arch/mips64/mips64/tlbhandler.S +++ b/sys/arch/mips64/mips64/tlbhandler.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlbhandler.S,v 1.3 2004/08/10 20:15:47 deraadt Exp $ */ +/* $OpenBSD: tlbhandler.S,v 1.4 2004/09/09 22:11:38 pefo Exp $ */ /* * Copyright (c) 1995-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -131,6 +131,9 @@ tlb_load: nop eret # RM7000 need 4 for JTLB usage. + .globl e_tlb_miss +e_tlb_miss: + /*---------------------------------------------------------------- xtlb_miss * Low level XTLB exception handler. * XXX! This handler should be changed to handle larger segtabs. @@ -162,8 +165,8 @@ _k_miss: j k_tlb_miss # kernel tlbmiss. dmfc0 k0, COP_0_BAD_VADDR # must reload. - .globl e_tlb_miss -e_tlb_miss: + .globl e_xtlb_miss +e_xtlb_miss: .set at /***************************** End of code copied to exception vector */ @@ -322,19 +325,25 @@ sys_stk_chk: nop LA a0, start-FRAMESZ(CF_SZ)-4*REGSZ # set sp to a valid place - PTR_S sp, CF_ARGSZ+2*REGSZ(a0) - move sp, a0 - LA a0, 1f +#ifdef __mips_n64 + mfc0 a4, COP_0_STATUS_REG + mfc0 a5, COP_0_CAUSE_REG + move a6, sp +#else mfc0 a2, COP_0_STATUS_REG mfc0 a3, COP_0_CAUSE_REG - dmfc0 a1, COP_0_EXC_PC REG_S a2, CF_ARGSZ+0*REGSZ(sp) REG_S a3, CF_ARGSZ+1*REGSZ(sp) + PTR_S sp, CF_ARGSZ+2*REGSZ(a0) +#endif + move sp, a0 + dmfc0 a1, COP_0_EXC_PC move a2, ra + LA a0, 1f jal printf dmfc0 a3, COP_0_BAD_VADDR - la sp, start-FRAMESZ(CF_SZ) # set sp to a valid place + LA sp, start-FRAMESZ(CF_SZ) # set sp to a valid place #ifdef DDB LA a0, 2f @@ -373,7 +382,7 @@ LEAF(tlb_write_indexed) ITLBNOPFIX lw a2, 8(a1) lw a3, 12(a1) - dmfc0 t0, COP_0_TLB_HI # Save the current PID. + dmfc0 ta4, COP_0_TLB_HI # Save the current PID. dmtc0 a2, COP_0_TLB_LO0 # Set up entry low0. dmtc0 a3, COP_0_TLB_LO1 # Set up entry low1. @@ -392,7 +401,7 @@ LEAF(tlb_write_indexed) nop nop - dmtc0 t0, COP_0_TLB_HI # Restore the PID. + dmtc0 ta4, COP_0_TLB_HI # Restore the PID. nop dmtc0 zero, COP_0_TLB_PG_MASK # Default mask value. mtc0 v1, COP_0_STATUS_REG # Restore the status register @@ -410,30 +419,30 @@ LEAF(tlb_flush) mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - mfc0 t1, COP_0_TLB_WIRED + mfc0 ta5, COP_0_TLB_WIRED LA v0, KSEG0_BASE # invalid address - dmfc0 t0, COP_0_TLB_HI # Save the PID + dmfc0 ta4, COP_0_TLB_HI # Save the PID dmtc0 v0, COP_0_TLB_HI # Mark entry high as invalid dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry0. dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. /* - * Align the starting value (t1) and the upper bound (a0). + * Align the starting value (ta5) and the upper bound (a0). */ 1: - mtc0 t1, COP_0_TLB_INDEX # Set the index register. - addu t1, t1, 1 # Increment index. + mtc0 ta5, COP_0_TLB_INDEX # Set the index register. + addu ta5, ta5, 1 # Increment index. nop nop nop tlbwi # Write the TLB entry. nop nop - bne t1, a0, 1b + bne ta5, a0, 1b nop - dmtc0 t0, COP_0_TLB_HI # Restore the PID + dmtc0 ta4, COP_0_TLB_HI # Restore the PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -449,7 +458,7 @@ LEAF(tlb_flush_addr) ITLBNOPFIX li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 # Make shure valid hi value. - dmfc0 t0, COP_0_TLB_HI # Get current PID + dmfc0 ta4, COP_0_TLB_HI # Get current PID dmtc0 a0, COP_0_TLB_HI # look for addr & PID nop nop @@ -459,11 +468,11 @@ LEAF(tlb_flush_addr) nop nop # Delay for effect nop - LA t1, KSEG0_BASE # Load invalid entry. + LA ta5, KSEG0_BASE # Load invalid entry. mfc0 v0, COP_0_TLB_INDEX # See what we got bltz v0, 1f # index < 0 => !found nop - dmtc0 t1, COP_0_TLB_HI # Mark entry high as invalid + dmtc0 ta5, COP_0_TLB_HI # Mark entry high as invalid dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry. dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry. @@ -477,7 +486,7 @@ LEAF(tlb_flush_addr) nop nop 1: - dmtc0 t0, COP_0_TLB_HI # restore PID + dmtc0 ta4, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -491,10 +500,10 @@ LEAF(tlb_update) mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - and t1, a0, 0x1000 # t1 = Even/Odd flag + and ta5, a0, 0x1000 # ta5 = Even/Odd flag li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 - dmfc0 t0, COP_0_TLB_HI # Save current PID + dmfc0 ta4, COP_0_TLB_HI # Save current PID dmtc0 a0, COP_0_TLB_HI # Init high reg and a2, a1, PG_G # Copy global bit nop @@ -503,7 +512,7 @@ LEAF(tlb_update) tlbp # Probe for the entry. dsll a1, a1, 34 dsrl a1, a1, 34 - bne t1, zero, 2f # Decide even odd + bne ta5, zero, 2f # Decide even odd mfc0 v0, COP_0_TLB_INDEX # See what we got # EVEN bltz v0, 1f # index < 0 => !found @@ -567,7 +576,7 @@ LEAF(tlb_update) 4: # Make shure pipeline nop # advances before we nop # uses the tlb. - dmtc0 t0, COP_0_TLB_HI # restore PID + dmtc0 ta4, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -581,7 +590,7 @@ LEAF(tlb_read) mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - dmfc0 t0, COP_0_TLB_HI # Get current PID + dmfc0 v0, COP_0_TLB_HI # Get current PID mtc0 a0, COP_0_TLB_INDEX # Set the index register nop @@ -592,21 +601,21 @@ LEAF(tlb_read) nop nop nop - mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry - dmfc0 t3, COP_0_TLB_HI # fetch the hi entry - dmfc0 t4, COP_0_TLB_LO0 # See what we got - dmfc0 t5, COP_0_TLB_LO1 # See what we got - dmtc0 t0, COP_0_TLB_HI # restore PID + mfc0 ta4, COP_0_TLB_PG_MASK # fetch the hi entry + dmfc0 ta5, COP_0_TLB_HI # fetch the hi entry + dmfc0 ta6, COP_0_TLB_LO0 # See what we got + dmfc0 ta7, COP_0_TLB_LO1 # See what we got + dmtc0 v0, COP_0_TLB_HI # restore PID nop nop nop # wait for PID active mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX - sw t2, 0(a1) - sw t3, 4(a1) - sw t4, 8(a1) + sw ta4, 0(a1) + sw ta5, 4(a1) + sw ta6, 8(a1) j ra - sw t5, 12(a1) + sw ta7, 12(a1) END(tlb_read) /*---------------------------------------------------------------- tlb_get_pid diff --git a/sys/arch/mips64/mips64/trap.c b/sys/arch/mips64/mips64/trap.c index 04d82a4ebc4..26e72a34052 100644 --- a/sys/arch/mips64/mips64/trap.c +++ b/sys/arch/mips64/mips64/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.4 2004/08/10 20:28:13 deraadt Exp $ */ +/* $OpenBSD: trap.c,v 1.5 2004/09/09 22:11:38 pefo Exp $ */ /* tracked to 1.23 */ /* @@ -165,7 +165,7 @@ trap(trapframe) struct proc *p = curproc; u_quad_t sticks; vm_prot_t ftype; - extern unsigned onfault_table[]; + extern vaddr_t onfault_table[]; int typ = 0; union sigval sv; @@ -313,6 +313,7 @@ trap(trapframe) #if defined(VMFAULT_TRACE) printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n", map, &vm->vm_map.pmap, va, trapframe->badvaddr, ftype, FALSE, rv, trapframe->pc); +printf("sp %p\n", trapframe->sp); #endif /* * If this was a stack access we keep track of the maximum @@ -427,9 +428,8 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr args.i[4] = locr0->a5; args.i[5] = locr0->a6; args.i[6] = locr0->a7; - i = copyin((void *)(locr0->sp + - 7 * sizeof(register_t)), &args.i[7], - sizeof(register_t)); + i = copyin((void *)locr0->sp, + &args.i[7], sizeof(register_t)); } } break; @@ -475,8 +475,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr args.i[4] = locr0->a5; args.i[5] = locr0->a6; args.i[6] = locr0->a7; - i = copyin((void *)(locr0->sp + - 7 * sizeof(register_t)), &args.i[7], + i = copyin((void *)locr0->sp, &args.i[7], sizeof(register_t)); } break; @@ -603,7 +602,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr iov.iov_len = sizeof(int); uio.uio_iov = &iov; uio.uio_iovcnt = 1; - uio.uio_offset = (off_t)(int)va; + uio.uio_offset = (off_t)(long)va; uio.uio_resid = sizeof(int); uio.uio_segflg = UIO_SYSSPACE; uio.uio_rw = UIO_WRITE; @@ -1169,8 +1168,8 @@ loop: } /* check for bad SP: could foul up next frame */ - if (sp & 3 || sp < 0xffffffff80000000) { - (*printfn)("SP 0x%x: not in kernel\n", sp); + if (sp & 3 || sp < KSEG0_BASE) { + (*printfn)("SP %p: not in kernel\n", sp); ra = 0; subr = 0; goto done; @@ -1201,8 +1200,8 @@ loop: Between((unsigned)a, pc, (unsigned)b) /* check for bad PC */ - if (pc & 3 || pc < 0xffffffff80000000 || pc >= (unsigned)edata) { - (*printfn)("PC 0x%x: not in kernel\n", pc); + if (pc & 3 || pc < KSEG0_BASE || pc >= (unsigned)edata) { + (*printfn)("PC %p: not in kernel\n", pc); ra = 0; goto done; } diff --git a/sys/arch/sgi/conf/GENERIC b/sys/arch/sgi/conf/GENERIC index 4c6d8dba7e1..9df34babddc 100644 --- a/sys/arch/sgi/conf/GENERIC +++ b/sys/arch/sgi/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.7 2004/08/11 15:13:21 deraadt Exp $ +# $OpenBSD: GENERIC,v 1.8 2004/09/09 22:11:39 pefo Exp $ # machine sgi mips64 @@ -8,14 +8,11 @@ include "../../../conf/GENERIC" maxusers 32 # Make options -#makeoption ISALEV="-mips3 -mlong64 -fno-builtin" -makeoption ISALEV="-mips2 -D_MIPS_ISA=_MIPS_ISA_MIPS2" -makeoption ENDIAN="-EB" +#makeoption ABI="-mabi=64" +#makeoption ENDIAN="-EB" # MD options option ARCBIOS # We use arcbios for FW comminication. -#option COMPAT_O32 # Mips o32 ABI compat -#option DB_ELFSIZE=32 #option APERTURE diff --git a/sys/arch/sgi/conf/Makefile.sgi b/sys/arch/sgi/conf/Makefile.sgi index 53bea276d82..72ea3cad98f 100644 --- a/sys/arch/sgi/conf/Makefile.sgi +++ b/sys/arch/sgi/conf/Makefile.sgi @@ -1,4 +1,4 @@ -# $OpenBSD: Makefile.sgi,v 1.4 2004/08/23 14:26:24 pefo Exp $ +# $OpenBSD: Makefile.sgi,v 1.5 2004/09/09 22:11:39 pefo Exp $ # Makefile for OpenBSD # @@ -29,7 +29,6 @@ CPP?= cpp LD?= ld ${ENDIAN} STRIP?= strip TOUCH?= touch -ISALEV?=-mips3 -mlong64 -fno-builtin CPP+=${ENDIAN} CC+=${ENDIAN} AS+=${ENDIAN} @@ -48,9 +47,9 @@ CPPFLAGS= ${INCLUDES} ${IDENT} -D_KERNEL -D__sgi__ CDIAGFLAGS= -Werror -Wall -Wmissing-prototypes -Wstrict-prototypes \ -Wno-uninitialized -Wno-format -Wno-main -CFLAGS= ${DEBUG} -O2 ${CDIAGFLAGS} -mno-abicalls ${ISALEV} \ - ${COPTS} -AFLAGS= -x assembler-with-cpp -traditional-cpp -mno-abicalls ${ISALEV} -D_LOCORE +CFLAGS= ${DEBUG} -O2 ${CDIAGFLAGS} -mno-abicalls ${ABI} \ + ${COPTS} -msoft-float -fno-builtin +AFLAGS= -x assembler-with-cpp -traditional-cpp -mno-abicalls ${ABI} -D_LOCORE ### find out what to use for libkern .include "$S/lib/libkern/Makefile.inc" diff --git a/sys/arch/sgi/conf/files.sgi b/sys/arch/sgi/conf/files.sgi index 2caff721db0..bd27e76f11f 100644 --- a/sys/arch/sgi/conf/files.sgi +++ b/sys/arch/sgi/conf/files.sgi @@ -1,4 +1,4 @@ -# $OpenBSD: files.sgi,v 1.3 2004/08/10 19:08:18 deraadt Exp $ +# $OpenBSD: files.sgi,v 1.4 2004/09/09 22:11:39 pefo Exp $ # # maxpartitions must be first item in files.${ARCH} # @@ -118,8 +118,3 @@ file dev/cninit.c file netinet/in_cksum.c file netns/ns_cksum.c ns -# -# mips o32 ABI compat. -# -#include "compat/mipso32/files.mipso32" - diff --git a/sys/arch/sgi/conf/ld.script b/sys/arch/sgi/conf/ld.script index f9393c3eec1..9076ac46476 100644 --- a/sys/arch/sgi/conf/ld.script +++ b/sys/arch/sgi/conf/ld.script @@ -1,11 +1,11 @@ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradlittlemips", - "elf32-tradbigmips") +OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradlittlemips", + "elf64-tradbigmips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS { /* Read-only sections, merged into text segment: */ - . = 0x80100000 + SIZEOF_HEADERS; + . = 0xffffffff80100000 + SIZEOF_HEADERS; .text : { _ftext = . ; diff --git a/sys/arch/sgi/include/exec.h b/sys/arch/sgi/include/exec.h index de11ac4ac1d..fc07310e027 100644 --- a/sys/arch/sgi/include/exec.h +++ b/sys/arch/sgi/include/exec.h @@ -1,4 +1,4 @@ -/* $OpenBSD: exec.h,v 1.6 2004/08/11 09:55:41 deraadt Exp $ */ +/* $OpenBSD: exec.h,v 1.7 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 1996-2004 Per Fogelstrom, Opsycon AB @@ -35,11 +35,22 @@ * Define what exec "formats" we should handle. */ #define NATIVE_EXEC_ELF +#define NATIVE_ELFSIZE 64 #define EXEC_SCRIPT -#define ARCH_ELFSIZE 32 +/* + * If included from sys/exec.h define kernels ELF format. + */ +#ifdef __LP64__ +#define ARCH_ELFSIZE 64 +#define DB_ELFSIZE 64 +#define ELF_TARG_CLASS ELFCLASS64 +#else +#define ARCH_ELFSIZE 32 +#define DB_ELFSIZE 32 +#define ELF_TARG_CLASS ELFCLASS32 +#endif -#define ELF_TARG_CLASS ELFCLASS32 #if defined(__MIPSEB__) #define ELF_TARG_DATA ELFDATA2MSB #else @@ -49,9 +60,13 @@ #define _NLIST_DO_ELF -#define _KERN_DO_ELF #if defined(_LP64) #define _KERN_DO_ELF64 +#if defined(COMPAT_O32) +#define _KERN_DO_ELF +#endif +#else +#define _KERN_DO_ELF #endif /* Information taken from MIPS ABI supplemental */ @@ -165,5 +180,9 @@ typedef struct { #define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ #define R_MIPS_GPREL32 12 /* GP relative 32 bit */ +#define R_MIPS_64 18 + +#define R_MIPS_REL32_64 ((R_MIPS_64 << 8) | R_MIPS_REL32) + #endif /* !_MIPS_EXEC_H_ */ diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c index 07529a93fa7..aff96b984d3 100644 --- a/sys/arch/sgi/localbus/macebus.c +++ b/sys/arch/sgi/localbus/macebus.c @@ -1,4 +1,4 @@ -/* $OpenBSD: macebus.c,v 1.5 2004/08/11 15:13:35 deraadt Exp $ */ +/* $OpenBSD: macebus.c,v 1.6 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 2000-2004 Opsycon AB (www.opsycon.se) @@ -322,7 +322,11 @@ mace_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) u_int64_t mace_read_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) { +#ifdef __LP64__ + return *(volatile u_int64_t *)(h + o); +#else return lp32_read8((u_int64_t *)(h + o)); +#endif } void @@ -346,7 +350,11 @@ mace_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, u_int32_t v) void mace_write_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, u_int64_t v) { +#ifdef __LP64__ + *(volatile u_int64_t *)(h + o) = v; +#else lp32_write8((u_int64_t *)(h + o), v); +#endif } int @@ -725,7 +733,7 @@ macebus_aux(intrmask_t hwpend, struct trap_frame *cf) } bus_space_write_8(&macebus_tag, mace_h, MACE_ISA_MISC_REG, mask); - if (maceticks++ > 100*15) { + if (maceticks++ > 100*5) { maceticks = 0; } diff --git a/sys/arch/sgi/localbus/macectrl.S b/sys/arch/sgi/localbus/macectrl.S index 83e6820a8a9..153ce326cc9 100644 --- a/sys/arch/sgi/localbus/macectrl.S +++ b/sys/arch/sgi/localbus/macectrl.S @@ -1,4 +1,4 @@ -/* $OpenBSD: macectrl.S,v 1.2 2004/08/10 19:16:18 deraadt Exp $ */ +/* $OpenBSD: macectrl.S,v 1.3 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -52,4 +52,4 @@ END(hw_setintrmask) .data .globl hwmask_addr -hwmask_addr: .long 0 +hwmask_addr: PTR_VAL 0 diff --git a/sys/arch/sgi/pci/macepcimap.c b/sys/arch/sgi/pci/macepcimap.c index 623ba93cb7e..41d7bacd3a3 100644 --- a/sys/arch/sgi/pci/macepcimap.c +++ b/sys/arch/sgi/pci/macepcimap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: macepcimap.c,v 1.2 2004/08/11 15:13:35 deraadt Exp $ */ +/* $OpenBSD: macepcimap.c,v 1.3 2004/09/09 22:11:39 pefo Exp $ */ /* $NetBSD: pci_mace.c,v 1.2 2004/01/19 10:28:28 sekiya Exp $ */ /* @@ -63,6 +63,11 @@ void pciaddr_print_devid(pci_chipset_tag_t, pcitag_t); unsigned int ioaddr_base = 0x1000; unsigned int memaddr_base = 0x80100000; +#ifdef DEBUG +int pcibiosverbose = 1; +#endif + + void pciaddr_remap(pci_chipset_tag_t pc) { diff --git a/sys/arch/sgi/sgi/locore.S b/sys/arch/sgi/sgi/locore.S index 3be0143e7ed..f9ec31d795a 100644 --- a/sys/arch/sgi/sgi/locore.S +++ b/sys/arch/sgi/sgi/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.3 2004/08/10 19:16:18 deraadt Exp $ */ +/* $OpenBSD: locore.S,v 1.4 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -40,8 +40,6 @@ .set noreorder # Noreorder is default style! -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; - .globl idle_stack # idle stack just below kernel. idle_stack: @@ -55,8 +53,8 @@ start: /* * Initialize stack and call machine startup. */ - la sp, start - FRAMESZ(CF_SZ) - la gp, _gp + LA sp, start - FRAMESZ(CF_SZ) + LA gp, _gp jal mips_init # mips_init(argc, argv, envp) sw zero, CF_RA_OFFS(sp) # Zero out old ra for debugger diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c index be785845a35..ff7229a4836 100644 --- a/sys/arch/sgi/sgi/machdep.c +++ b/sys/arch/sgi/sgi/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.9 2004/09/09 10:25:52 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.10 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -188,8 +188,8 @@ mips_init(int argc, int32_t *argv) ssym = (char *)(long)*(int *)end; esym = (char *)(long)*((int *)end + 1); ekern = esym; - if (((int)ssym - (int)end) < 0 || - ((int)ssym - (int)end) > 0x1000 || + if (((long)ssym - (long)end) < 0 || + ((long)ssym - (long)end) > 0x1000 || ssym[0] != ELFMAG0 || ssym[1] != ELFMAG1 || ssym[2] != ELFMAG2 || ssym[3] != ELFMAG3 ) { ssym = NULL; @@ -401,7 +401,7 @@ mips_init(int argc, int32_t *argv) * Copy down exception vector code. If code is to large * copy down trampolines instead of doing a panic. */ - if (e_tlb_miss - tlb_miss > 0x100) { + if (e_tlb_miss - tlb_miss > 0x80) { bcopy(tlb_miss_tramp, (char *)TLB_MISS_EXC_VEC, e_tlb_miss_tramp - tlb_miss_tramp); bcopy(xtlb_miss_tramp, (char *)XTLB_MISS_EXC_VEC, @@ -506,7 +506,7 @@ dobootopts(int argc, int32_t *argv) /* XXX Should this be done differently, eg env vs. args? */ for (i = 1; i < argc; i++) { - cp = (char *)argv[i]; + cp = (char *)(long)argv[i]; if (cp != NULL && strncmp(cp, "OSLoadOptions=", 14) == 0) { if (strcmp(&cp[14], "auto") == 0) boothowto &= ~(RB_SINGLE|RB_ASKNAME); @@ -701,16 +701,18 @@ setregs(p, pack, stack, retval) } #endif -#if !defined(_LP64) +#if !defined(__LP64__) p->p_md.md_flags |= MDP_O32; +#else + p->p_md.md_flags &= ~MDP_O32; #endif bzero((caddr_t)p->p_md.md_regs, sizeof(struct trap_frame)); p->p_md.md_regs->sp = stack; p->p_md.md_regs->pc = pack->ep_entry & ~3; p->p_md.md_regs->t9 = pack->ep_entry & ~3; /* abicall req */ -#if 0 - p->p_md.md_regs->sr = SR_FR_32|SR_KSU_USER|SR_UX|SR_EXL|SR_INT_ENAB; +#if defined(__LP64__) + p->p_md.md_regs->sr = SR_FR_32|SR_XX|SR_KSU_USER|SR_UX|SR_EXL|SR_INT_ENAB; #else p->p_md.md_regs->sr = SR_KSU_USER|SR_XX|SR_EXL|SR_INT_ENAB; #endif diff --git a/sys/arch/sgi/stand/boot/Makefile b/sys/arch/sgi/stand/boot/Makefile index f0a9a98c5c9..f286c8dc408 100644 --- a/sys/arch/sgi/stand/boot/Makefile +++ b/sys/arch/sgi/stand/boot/Makefile @@ -1,16 +1,16 @@ -# $OpenBSD: Makefile,v 1.1 2004/08/23 14:22:40 pefo Exp $ +# $OpenBSD: Makefile,v 1.2 2004/09/09 22:11:39 pefo Exp $ PROG= boot NOMAN= noman -CFLAGS+= -O2 -mno-abicalls -D_NO_ABICALLS -nostdinc -D__sgi__ \ +CFLAGS+= -O2 -mabi=32 -mno-abicalls -D_NO_ABICALLS -nostdinc -D__sgi__ \ -I${.CURDIR}/../include -I${.CURDIR}/../../../.. \ -I${.CURDIR}/../../../../lib/libsa \ -I${.OBJDIR} CFLAGS+= -D__INTERNAL_LIBSA_CREAD ${STANDALONE} -LDFLAGS+= ${SALDFLAGS} -T ${.CURDIR}/../../conf/ld.script -Ttext 80002000 -e __start +LDFLAGS+= ${SALDFLAGS} -T ${.CURDIR}/../../conf/ld.script -Ttext 80010000 -e __start SRCS= start.S boot.c filesystem.c conf.c diskio.c arcbios.c diff --git a/sys/arch/sgi/stand/boot/boot.c b/sys/arch/sgi/stand/boot/boot.c index b5db5c1ad6f..43987048049 100644 --- a/sys/arch/sgi/stand/boot/boot.c +++ b/sys/arch/sgi/stand/boot/boot.c @@ -1,4 +1,4 @@ -/* $OpenBSD: boot.c,v 1.1 2004/08/23 14:22:40 pefo Exp $ */ +/* $OpenBSD: boot.c,v 1.2 2004/09/09 22:11:39 pefo Exp $ */ /* * Copyright (c) 2004 Opsycon AB, www.opsycon.se. @@ -38,12 +38,17 @@ void gets(char *); ssize_t read(int, void *, size_t); int close(int); -void pmon_write(int, char *, int); -void pmon_synccache(void); -int main(int, char **, char **); -int loadfile(char *); -int loadsymtab(int fd, Elf32_Ehdr *eh, int flags); +int main(int, char **); +void dobootopts(int, char **); +Elf32_Addr loadfile(char *); +Elf32_Addr loadfile32(int, Elf32_Ehdr *); +Elf32_Addr loadfile64(int, Elf64_Ehdr *); +int loadsymtab(int, Elf32_Ehdr *, int); + +enum { AUTO_NONE, AUTO_YES, AUTO_NO, AUTO_DEBUG } bootauto = AUTO_NONE; +char *OSLoadPartition = NULL; +char *OSLoadFilename = NULL; unsigned long tablebase; @@ -72,96 +77,187 @@ gettable (int size, char *name, int flags) /* */ int -main(argc, argv, envp) +main(argc, argv) int argc; char **argv; - char **envp; { - char *cp; - int i, ask, entry; char line[1024]; + char *cp; + int i; + Elf32_Addr entry; - ask = 0; - - cp = Bios_GetEnvironmentVariable("OSLoadPartition"); - if (cp != NULL) { - strncpy(line, cp, sizeof(line)); + dobootopts(argc, argv); + if (OSLoadPartition != NULL) { + strlcpy(line, OSLoadPartition, sizeof(line)); i = strlen(line); - cp = Bios_GetEnvironmentVariable("OSLoadFilename"); - if (cp != NULL) - strncpy(&line[i], cp, sizeof(line) - i -1); - else - ask = 1; + if (OSLoadFilename != NULL) + strlcpy(&line[i], OSLoadFilename, sizeof(line) - i -1); } else - ask = 1; + strlcpy("invalid argument setup", line, sizeof(line)); printf("\nOpenBSD/sgi Arcbios boot\n"); for (entry = 0; entry < argc; entry++) printf("arg %d: %s\n", entry, argv[entry]); - while (1) { - do { - printf("Boot: "); - if (ask) { - gets(line); - } - else - printf("%s\n", line); - } while(ask && line[0] == '\0'); + printf("Boot: %s\n", line); + + entry = loadfile(line); + if (entry != NULL) { + printf("start at 0x%x\n", entry); + ((void (*)())entry)(argc, argv); + } + printf("Boot FAILED!\n "); + Bios_Restart(); +} - entry = loadfile(line); - if (entry != -1) { - ((void (*)())entry)(argc, argv); +/* + * Decode boot options. + */ +void +dobootopts(int argc, char **argv) +{ + char *cp; + int i; + + /* XXX Should this be done differently, eg env vs. args? */ + for (i = 1; i < argc; i++) { + cp = argv[i]; + if (cp == NULL) + continue; + + if (strncmp(cp, "OSLoadOptions=", 14) == 0) { + if (strcmp(&cp[14], "auto") == 0) + bootauto = AUTO_YES; + else if (strcmp(&cp[14], "single") == 0) + bootauto = AUTO_NO; + else if (strcmp(&cp[14], "debug") == 0) + bootauto = AUTO_DEBUG; } - ask = 1; + else if (strncmp(cp, "OSLoadPartition=", 16) == 0) + OSLoadPartition = &cp[16]; + else if (strncmp(cp, "OSLoadFilename=", 15) == 0) + OSLoadFilename = &cp[15]; } - return(0); + /* If "OSLoadOptions=" is missing, see if any arg was given */ + if (bootauto == AUTO_NONE && *argv[1] == '/') + OSLoadFilename = argv[1]; } /* * Open 'filename', read in program and return the entry point or -1 if error. */ -int +Elf32_Addr loadfile(fname) register char *fname; { + union { + Elf32_Ehdr eh32; + Elf64_Ehdr eh64; + } eh; int fd, i; - Elf32_Ehdr eh; - Elf32_Phdr *ph; + Elf32_Addr entry; char *errs = 0; - char buf[4096]; if ((fd = oopen(fname, 0)) < 0) { - errs="open err: %s\n"; - goto err; + printf("can't open file %s\n", fname); + return NULL; + } + + /* read the ELF header and check that it IS an ELF header */ + if (oread(fd, (char *)&eh, sizeof(eh)) != sizeof(eh)) { + printf("error: ELF header read error\n"); + return NULL; + } + if (!IS_ELF(eh.eh32)) { + printf("not an elf file\n"); + return NULL; } - /* read the elf header */ - if(oread(fd, (char *)&eh, sizeof(eh)) != sizeof(eh)) { - goto serr; + /* Determine CLASS */ + if (eh.eh32.e_ident[EI_CLASS] == ELFCLASS32) + entry = loadfile32(fd, (void *)&eh); + else if (eh.eh32.e_ident[EI_CLASS] == ELFCLASS64) + entry = loadfile64(fd, (void *)&eh); + else { + printf("unknown ELF class\n"); + return NULL; } + return entry; +} + +Elf32_Addr +loadfile32(int fd, Elf32_Ehdr *eh) +{ + char buf[4096]; + Elf32_Phdr *ph; + int i; ph = (Elf32_Phdr *) buf; - olseek(fd, eh.e_phoff, 0); - if(oread(fd, (char *)ph, 4096) != 4096) { - goto serr; + olseek(fd, eh->e_phoff, 0); + if (oread(fd, (char *)ph, 4096) != 4096) { + printf("unexpected EOF\n"); + return NULL; } tablebase = 0; + printf("Loading ELF32 file\n"); - for(i = 0; i < eh.e_phnum; i++, ph++) { - if(ph->p_type == PT_LOAD) { + for (i = 0; i < eh->e_phnum; i++, ph++) { + if (ph->p_type == PT_LOAD) { + olseek(fd, ph->p_offset, 0); + printf("0x%x:0x%x, ",(long)ph->p_paddr, (long)ph->p_filesz); + if (oread(fd, (char *)ph->p_paddr, ph->p_filesz) != ph->p_filesz) { + printf("unexpected EOF\n"); + return NULL; + } + if(ph->p_memsz > ph->p_filesz) { + printf("Zero 0x%x:0x%x, ", + (long)(ph->p_paddr + ph->p_filesz), + (long)(ph->p_memsz - ph->p_filesz)); + bzero((void *)(ph->p_paddr + ph->p_filesz), + ph->p_memsz - ph->p_filesz); + } + if((ph->p_paddr + ph->p_memsz) > tablebase) { + tablebase = ph->p_paddr + ph->p_memsz; + } + } + } + memset((void *)tablebase, 0, 4096); + loadsymtab(fd, eh, 0); + return(eh->e_entry); +} + +Elf32_Addr +loadfile64(int fd, Elf64_Ehdr *eh) +{ + char buf[4096]; + Elf64_Phdr *ph; + int i; + + ph = (Elf64_Phdr *) buf; + olseek(fd, eh->e_phoff, 0); + if (oread(fd, (char *)ph, 4096) != 4096) { + printf("unexpected EOF\n"); + return NULL; + } + + tablebase = 0; + printf("Loading ELF64 file\n"); + + for (i = 0; i < eh->e_phnum; i++, ph++) { + if (ph->p_type == PT_LOAD) { olseek(fd, ph->p_offset, 0); printf("0x%x:0x%x, ",ph->p_paddr, ph->p_filesz); - if(oread(fd, (char *)ph->p_paddr, ph->p_filesz) != ph->p_filesz) { - goto serr; + if (oread(fd, (char *)(long)ph->p_paddr, ph->p_filesz) != ph->p_filesz) { + printf("unexpected EOF\n"); + return NULL; } if(ph->p_memsz > ph->p_filesz) { printf("Zero 0x%x:0x%x, ", ph->p_paddr + ph->p_filesz, ph->p_memsz - ph->p_filesz); - bzero((void *)(ph->p_paddr + ph->p_filesz), + bzero((void *)(long)(ph->p_paddr + ph->p_filesz), ph->p_memsz - ph->p_filesz); } if((ph->p_paddr + ph->p_memsz) > tablebase) { @@ -169,16 +265,13 @@ loadfile(fname) } } } - printf("start at 0x%x\n", eh.e_entry); - memset(tablebase, 0, 4096); - loadsymtab(fd, &eh, 0); - return(eh.e_entry); -serr: - errs = "%s sz err\n"; -err: - printf(errs, fname); - return (-1); + memset((void *)tablebase, 0, 4096); +// loadsymtab(fd, &eh, 0); + return(eh->e_entry); } + + + int loadsymtab(int fd, Elf32_Ehdr *eh, int flags) { |