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-rw-r--r--sys/arch/vax/include/ka410.h20
-rw-r--r--sys/arch/vax/include/ka420.h20
-rw-r--r--sys/arch/vax/include/ka43.h16
3 files changed, 7 insertions, 49 deletions
diff --git a/sys/arch/vax/include/ka410.h b/sys/arch/vax/include/ka410.h
index 3d0095bf5c2..7136a3d45c3 100644
--- a/sys/arch/vax/include/ka410.h
+++ b/sys/arch/vax/include/ka410.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: ka410.h,v 1.4 2000/04/26 03:08:41 bjc Exp $ */
+/* $OpenBSD: ka410.h,v 1.5 2006/07/25 21:11:08 miod Exp $ */
/* $NetBSD: ka410.h,v 1.2 1997/02/19 10:06:05 ragge Exp $ */
/*
* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
@@ -90,27 +90,13 @@
#define KA410_LAN_END 0x200E0007
#define KA410_LAN_SIZE 0x08
#define KA410_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
-#define KA410_CUR_END 0x200F0007
-#define KA410_CUR_SIZE 0x08
+#define KA410_CUR_END 0x200F003F
+#define KA410_CUR_SIZE 0x40
#define KA410_SCS_DADR 0x200C00A0 /* Tape(SCSI) DMA address register */
#define KA410_SCS_DCNT 0x200C00C0 /* Tape(SCSI) DMA byte count reg. */
#define KA410_SCS_DDIR 0x200C00C4 /* Tape(SCSI) DMA transfer direction */
-#define KA410_CUR_CMD 0x200F0000 /* Cursor Command Register */
-#define KA410_CUR_XPOS 0x200F0004 /* Cursor X position */
-#define KA410_CUR_YPOS 0x200F0008 /* Cursor Y position */
-
-#define KA410_CUR_XMIN1 0x200F000C /* Region 1 left edge */
-#define KA410_CUR_XMAX1 0x200F0010 /* Region 1 right edge */
-#define KA410_CUR_YMIN1 0x200F0014 /* Region 1 top edge */
-#define KA410_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */
-
-#define KA410_CUR_XMIN2 0x200F002C /* Region 2 left edge */
-#define KA410_CUR_XMAX2 0x200F0030 /* Region 2 right edge */
-#define KA410_CUR_YMIN2 0x200F0034 /* Region 2 top edge */
-#define KA410_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */
-
/*
* Definitions for the Configuration and Test Register
*/
diff --git a/sys/arch/vax/include/ka420.h b/sys/arch/vax/include/ka420.h
index ad782ec926d..8c771914324 100644
--- a/sys/arch/vax/include/ka420.h
+++ b/sys/arch/vax/include/ka420.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: ka420.h,v 1.3 2000/04/26 03:08:41 bjc Exp $ */
+/* $OpenBSD: ka420.h,v 1.4 2006/07/25 21:11:08 miod Exp $ */
/* $NetBSD: ka420.h,v 1.2 1998/06/07 18:34:09 ragge Exp $ */
/*
* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
@@ -99,8 +99,8 @@
#define KA420_LAN_END 0x200E0007
#define KA420_LAN_SIZE 0x08
#define KA420_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
-#define KA420_CUR_END 0x200F0007
-#define KA420_CUR_SIZE 0x08
+#define KA420_CUR_END 0x200F003F
+#define KA420_CUR_SIZE 0x40
#define KA420_DMA_BASE 0x202D0000 /* 128KB Data Buffer */
#define KA420_DMA_END 0x202EFFFF
#define KA420_DMA_SIZE 0x20000
@@ -111,20 +111,6 @@
#define KA420_STC_MODE 0x200C00E0 /* Storage Controller Mode register */
-#define KA420_CUR_CMD 0x200F0000 /* Cursor Command Register */
-#define KA420_CUR_XPOS 0x200F0004 /* Cursor X position */
-#define KA420_CUR_YPOS 0x200F0008 /* Cursor Y position */
-
-#define KA420_CUR_XMIN1 0x200F000C /* Region 1 left edge */
-#define KA420_CUR_XMAX1 0x200F0010 /* Region 1 right edge */
-#define KA420_CUR_YMIN1 0x200F0014 /* Region 1 top edge */
-#define KA420_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */
-
-#define KA420_CUR_XMIN2 0x200F002C /* Region 2 left edge */
-#define KA420_CUR_XMAX2 0x200F0030 /* Region 2 right edge */
-#define KA420_CUR_YMIN2 0x200F0034 /* Region 2 top edge */
-#define KA420_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */
-
/*
* Clock-Chip data in NVRAM
*/
diff --git a/sys/arch/vax/include/ka43.h b/sys/arch/vax/include/ka43.h
index dd9e70af928..bd578f5cd4a 100644
--- a/sys/arch/vax/include/ka43.h
+++ b/sys/arch/vax/include/ka43.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: ka43.h,v 1.4 2000/04/26 03:08:41 bjc Exp $ */
+/* $OpenBSD: ka43.h,v 1.5 2006/07/25 21:11:08 miod Exp $ */
/* $NetBSD: ka43.h,v 1.2 1997/04/18 18:53:40 ragge Exp $ */
/*
* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
@@ -184,20 +184,6 @@
#define KA43_SC2_DCNT 0x200C01C0
#define KA43_SC2_DDIR 0x200C01C4
-#define KA43_CUR_CMD 0x200F0000 /* Cursor Command Register */
-#define KA43_CUR_XPOS 0x200F0004 /* Cursor X position */
-#define KA43_CUR_YPOS 0x200F0008 /* Cursor Y position */
-
-#define KA43_CUR_XMIN1 0x200F000C /* Region 1 left edge */
-#define KA43_CUR_XMAX1 0x200F0010 /* Region 1 right edge */
-#define KA43_CUR_YMIN1 0x200F0014 /* Region 1 top edge */
-#define KA43_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */
-
-#define KA43_CUR_XMIN2 0x200F002C /* Region 2 left edge */
-#define KA43_CUR_XMAX2 0x200F0030 /* Region 2 right edge */
-#define KA43_CUR_YMIN2 0x200F0034 /* Region 2 top edge */
-#define KA43_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */
-
/*
* Clock-Chip data in NVRAM
*/