diff options
Diffstat (limited to 'sys')
22 files changed, 29 insertions, 881 deletions
diff --git a/sys/arch/sparc64/include/asm.h b/sys/arch/sparc64/include/asm.h index f431cd3f9b1..51032d1237c 100644 --- a/sys/arch/sparc64/include/asm.h +++ b/sys/arch/sparc64/include/asm.h @@ -1,4 +1,4 @@ -/* $OpenBSD: asm.h,v 1.2 2001/08/20 20:23:52 jason Exp $ */ +/* $OpenBSD: asm.h,v 1.3 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: asm.h,v 1.15 2000/08/02 22:24:39 eeh Exp $ */ /* @@ -50,12 +50,6 @@ #endif #include <machine/frame.h> -#ifdef __arch64__ -#ifndef __ELF__ -#define __ELF__ -#endif -#endif - /* Pull in CCFSZ, CC64FSZ, and BIAS from frame.h */ #ifndef _LOCORE #define _LOCORE diff --git a/sys/arch/sparc64/include/autoconf.h b/sys/arch/sparc64/include/autoconf.h index 079ea8a154a..cbe44f894ea 100644 --- a/sys/arch/sparc64/include/autoconf.h +++ b/sys/arch/sparc64/include/autoconf.h @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.h,v 1.7 2002/03/14 03:16:00 millert Exp $ */ +/* $OpenBSD: autoconf.h,v 1.8 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: autoconf.h,v 1.10 2001/07/24 19:32:11 eeh Exp $ */ /*- @@ -162,7 +162,6 @@ struct bootpath { struct device *dev; /* device that recognised this component */ }; struct bootpath *bootpath_store(int, struct bootpath *); -int sd_crazymap(int); /* Parse a disk string into a dev_t, return device struct pointer */ struct device *parsedisk(char *, int, int, dev_t *); diff --git a/sys/arch/sparc64/include/ctlreg.h b/sys/arch/sparc64/include/ctlreg.h index 1ce17fa4f62..c6ffe50060b 100644 --- a/sys/arch/sparc64/include/ctlreg.h +++ b/sys/arch/sparc64/include/ctlreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ctlreg.h,v 1.6 2002/06/09 23:04:38 mdw Exp $ */ +/* $OpenBSD: ctlreg.h,v 1.7 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */ /* @@ -473,7 +473,6 @@ static __inline__ u_int64_t casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue); #endif -#ifdef __arch64__ static __inline__ u_char lduba(paddr_t loc, int asi) { @@ -495,34 +494,7 @@ lduba(paddr_t loc, int asi) } return (_lduba_v); } -#else -static __inline__ u_char -lduba(paddr_t loc, int asi) -{ - register unsigned int _lduba_v, _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; " -" andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " -" sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " -" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; " -" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; " -" membar #Sync; wr %%g0, 0x82, %%asi" : - "=&r" (_lduba_v), "=&r" (_pstate) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " -" or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) : - "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi)); - } - return (_lduba_v); -} -#endif -#ifdef __arch64__ /* load half-word from alternate address space */ static __inline__ u_short lduha(paddr_t loc, int asi) @@ -545,34 +517,7 @@ lduha(paddr_t loc, int asi) } return (_lduha_v); } -#else -/* load half-word from alternate address space */ -static __inline__ u_short -lduha(paddr_t loc, int asi) { - register unsigned int _lduha_v, _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " -" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " -" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; " -" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; " -" membar #Sync; wr %%g0, 0x82, %%asi" : - "=&r" (_lduha_v), "=&r" (_pstate) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " -" or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); - } - return (_lduha_v); -} -#endif - - -#ifdef __arch64__ /* load unsigned int from alternate address space */ static __inline__ u_int lda(paddr_t loc, int asi) @@ -617,59 +562,7 @@ ldswa(paddr_t loc, int asi) } return (_lda_v); } -#else /* __arch64__ */ -/* load unsigned int from alternate address space */ -static __inline__ u_int -lda(paddr_t loc, int asi) -{ - register unsigned int _lda_v, _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" -" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " -" sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " -" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; " -" stxa %%g0,[%1] %5; membar #Sync; " -" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " -" or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : - "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi)); - } - return (_lda_v); -} - -/* load signed int from alternate address space */ -static __inline__ int -ldswa(paddr_t loc, int asi) -{ - register int _lda_v, _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" -" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" -" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; " -" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_lda_v), "=&r" (_pstate) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " -" or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : - "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi)); - } - return (_lda_v); -} -#endif /* __arch64__ */ -#ifdef __arch64__ /* load 64-bit int from alternate address space -- these should never be used */ static __inline__ u_int64_t ldda(paddr_t loc, int asi) @@ -692,34 +585,7 @@ ldda(paddr_t loc, int asi) } return (_lda_v); } -#else -/* load 64-bit int from alternate address space */ -static __inline__ u_int64_t -ldda(paddr_t loc, int asi) -{ - register long long _lda_v, _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" -" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" -" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; " -" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_lda_v), "=&r" (_pstate) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " -" or %0,%1,%0; ldda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); - } - return (_lda_v); -} -#endif - -#ifdef __arch64__ /* native load 64-bit int from alternate address space w/64-bit compiler*/ static __inline__ u_int64_t ldxa(paddr_t loc, int asi) @@ -742,37 +608,8 @@ ldxa(paddr_t loc, int asi) } return (_lda_v); } -#else -/* native load 64-bit int from alternate address space w/32-bit compiler*/ -static __inline__ u_int64_t -ldxa(paddr_t loc, int asi) -{ - register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; " -" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " -" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " -" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; " -" srlx %0,32,%1; srl %0,0,%0; wr %%g0, 0x82, %%asi" : - "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " -" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; " -" srl %0,0,%0;; wr %%g0, 0x82, %%asi" : - "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi)); - } - return ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); -} -#endif /* store byte to alternate address space */ -#ifdef __arch64__ static __inline__ void stba(paddr_t loc, int asi, u_char value) { @@ -790,32 +627,8 @@ stba(paddr_t loc, int asi, u_char value) "r" (asi)); } } -#else -static __inline__ void -stba(paddr_t loc, int asi, u_char value) -{ - register int _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" -" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; " -" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_pstate) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " -" or %2,%0,%0; stba %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi)); - } -} -#endif /* store half-word to alternate address space */ -#ifdef __arch64__ static __inline__ void stha(paddr_t loc, int asi, u_short value) { @@ -833,34 +646,8 @@ stha(paddr_t loc, int asi, u_short value) "r" (asi) : "memory"); } } -#else -static __inline__ void -stha(paddr_t loc, int asi, u_short value) -{ - register int _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" -" or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate; " -" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_pstate) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi), - "n" (ASI_DCACHE_TAG) : "memory"); - } else { - __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " -" or %2,%0,%0; stha %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi) : "memory"); - } -} -#endif - /* store int to alternate address space */ -#ifdef __arch64__ static __inline__ void sta(paddr_t loc, int asi, u_int value) { @@ -878,33 +665,8 @@ sta(paddr_t loc, int asi, u_int value) "r" (asi) : "memory"); } } -#else -static __inline__ void -sta(paddr_t loc, int asi, u_int value) -{ - register int _loc_hi, _pstate; - - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" -" or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate; " -" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_pstate) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi), - "n" (ASI_DCACHE_TAG) : "memory"); - } else { - __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " -" or %2,%0,%0; sta %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : - "r" ((int)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi) : "memory"); - } -} -#endif /* store 64-bit int to alternate address space */ -#ifdef __arch64__ static __inline__ void stda(paddr_t loc, int asi, u_int64_t value) { @@ -922,33 +684,7 @@ stda(paddr_t loc, int asi, u_int64_t value) "r" (asi) : "memory"); } } -#else -static __inline__ void -stda(paddr_t loc, int asi, u_int64_t value) -{ - register int _loc_hi, _pstate; - _loc_hi = (((u_int64_t)loc)>>32); - if (PHYS_ASI(asi)) { - __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " -" or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate;" -" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_pstate) : - "r" ((long long)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi), - "n" (ASI_DCACHE_TAG) : "memory"); - } else { - __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " -" or %2,%0,%0; stda %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi) : - "r" ((long long)(value)), "r" ((unsigned long)(loc)), - "r" (_loc_hi), "r" (asi) : "memory"); - } -} -#endif - -#ifdef __arch64__ /* native store 64-bit int to alternate address space w/64-bit compiler*/ static __inline__ void stxa(paddr_t loc, int asi, u_int64_t value) @@ -968,104 +704,6 @@ stxa(paddr_t loc, int asi, u_int64_t value) "r" ((unsigned long)(loc)), "r" (asi) : "memory"); } } -#else -/* native store 64-bit int to alternate address space w/32-bit compiler*/ -static __inline__ void -stxa(paddr_t loc, int asi, u_int64_t value) -{ - int _stxa_lo, _stxa_hi, _loc_hi; - - _stxa_lo = value; - _stxa_hi = ((u_int64_t)value)>>32; - _loc_hi = (((u_int64_t)(u_long)loc)>>32); - - if (PHYS_ASI(asi)) { - __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " -" or %1,%3,%1; rdpr %%pstate,%2; or %0,%5,%0; wrpr %2,8,%%pstate; " -" stxa %1,[%0]%%asi; wrpr %2,0,%%pstate; andn %0,0x1f,%1; " -" membar #Sync; stxa %%g0,[%1] %8; membar #Sync; wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_stxa_hi), - "=&r" ((int)(_stxa_lo)) : - "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); - } else { - __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " -" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : - "=&r" (_loc_hi), "=&r" (_stxa_hi) : - "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi) : "memory"); - } -} -#endif - -#if 0 -#ifdef __arch64__ -/* native store 64-bit int to alternate address space w/64-bit compiler*/ -static __inline__ u_int64_t -casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) -{ - if (PHYS_ASI(asi)) { - __asm __volatile("wr %4,%%g0,%%asi; casxa [%3]%%asi,%2,%1;" -" andn %3,0x1f,%0; membar #Sync; stxa %%g0,[%0] %5; membar #Sync; " -" wr %%g0, 0x82, %%asi" : - "=&r" (loc), "+r" (value) : - "r" ((unsigned long)(oldvalue)), - "r" ((unsigned long)(loc)), - "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); - } else { - __asm __volatile("wr %3,%%g0,%%asi; casxa [%1]%%asi,%2,%0; " -" wr %%g0, 0x82, %%asi" : - "+r" (value) : - "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) : - "memory"); - } - return (value); -} -#else -/* native store 64-bit int to alternate address space w/32-bit compiler*/ -static __inline__ u_int64_t -casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) -{ - int _casxa_lo, _casxa_hi, _loc_hi, _oval_hi; - - _casxa_lo = value; - _casxa_hi = ((u_int64_t)value)>>32; - _oval_hi = ((u_int64_t)oldvalue)>>32; - _loc_hi = (((u_int64_t)(u_long)loc)>>32); - -#ifdef __notyet -/* - * gcc cannot handle this since it thinks it has >10 asm operands. - */ - if (PHYS_ASI(asi)) { - __asm __volatile("wr %6,%%g0,%%asi; sllx %1,32,%1; sllx %0,32,%0; " -" sllx %3,32,%3; or %1,%2,%1; rdpr %%pstate,%2; or %0,%4,%0; or %3,%5,%3; " -" wrpr %2,8,%%pstate; casxa [%0]%%asi,%3,%1; wrpr %2,0,%%pstate; " -" andn %0,0x1f,%3; membar #Sync; stxa %%g0,[%3] %7; membar #Sync; " -" sll %1,0,%2; srax %1,32,%1; wr %%g0, 0x82, %%asi " : - "+r" (_loc_hi), "+r" (_casxa_hi), - "+r" (_casxa_lo), "+r" (_oval_hi) : - "r" ((unsigned long)(loc)), - "r" ((unsigned int)(oldvalue)), - "r" (asi), "n" (ASI_DCACHE_TAG)); - } else { - __asm __volatile("wr %7,%%g0,%%asi; sllx %1,32,%1; sllx %5,32,%0; " -" or %1,%2,%1; sllx %3,32,%2; or %0,%4,%0; or %2,%4,%2; " -" casxa [%0]%%asi,%2,%1; sll %1,0,%2; srax %o1,32,%o1; wr %%g0, 0x82, %%asi " : - "=&r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo) : - "r" ((int)(_oval_hi)), "r" ((int)(oldvalue)), - "r" ((unsigned long)(loc)), "r" (_loc_hi), - "r" (asi) : "memory"); - } -#endif - return (((u_int64_t)_casxa_hi<<32)|(u_int64_t)_casxa_lo); -} -#endif -#endif /* 0 */ - - /* flush address from data cache */ #define flush(loc) ({ \ @@ -1113,22 +751,12 @@ casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) /* Complete all outstanding stores before any new loads */ #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) -#ifdef __arch64__ /* read 64-bit %tick register */ #define tick() ({ \ register u_long _tick_tmp; \ __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ _tick_tmp; \ }) -#else -/* read 64-bit %tick register on 32-bit system */ -#define tick() ({ \ - register u_int _tick_hi = 0, _tick_lo = 0; \ - __asm __volatile("rdpr %%tick, %0; srl %0,0,%1; srlx %0,32,%0 " \ - : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ - (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ -}) -#endif extern void next_tick(long); #endif diff --git a/sys/arch/sparc64/include/db_machdep.h b/sys/arch/sparc64/include/db_machdep.h index 80c00ed7571..1d9e84106e8 100644 --- a/sys/arch/sparc64/include/db_machdep.h +++ b/sys/arch/sparc64/include/db_machdep.h @@ -1,4 +1,4 @@ -/* $OpenBSD: db_machdep.h,v 1.6 2002/03/14 01:26:45 millert Exp $ */ +/* $OpenBSD: db_machdep.h,v 1.7 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: db_machdep.h,v 1.12 2001/07/07 15:16:13 eeh Exp $ */ /* @@ -144,16 +144,9 @@ int kdb_trap(int, struct trapframe64 *); /* * We will use elf symbols in DDB when they work. */ -#if 1 #define DB_ELF_SYMBOLS -#ifdef __arch64__ #define DB_ELFSIZE 64 -#else -#define DB_ELFSIZE 32 -#endif -#else -#define DB_AOUT_SYMBOLS -#endif + /* * KGDB definitions */ diff --git a/sys/arch/sparc64/include/exec.h b/sys/arch/sparc64/include/exec.h index 3773b9ea9fb..e844bf0fdcc 100644 --- a/sys/arch/sparc64/include/exec.h +++ b/sys/arch/sparc64/include/exec.h @@ -1,4 +1,4 @@ -/* $OpenBSD: exec.h,v 1.5 2001/08/19 20:20:45 art Exp $ */ +/* $OpenBSD: exec.h,v 1.6 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: elf_machdep.h,v 1.7 2001/02/11 00:18:49 eeh Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB @@ -17,15 +17,9 @@ #define _KERN_DO_ELF64 #define _NLIST_DO_ELF -#ifdef __arch64__ #define ARCH_ELFSIZE 64 /* MD native binary size */ #define ELF_TARG_CLASS ELFCLASS64 #define ELF_TARG_MACH EM_SPARCV9 -#else -#define ARCH_ELFSIZE 32 /* MD native binary size */ -#define ELF_TARG_CLASS ELFCLASS32 -#define ELF_TARG_MACH EM_SPARC -#endif #define ELF_TARG_DATA ELFDATA2MSB diff --git a/sys/arch/sparc64/include/openfirm.h b/sys/arch/sparc64/include/openfirm.h index 7d27aaff1ad..e70f7bda1be 100644 --- a/sys/arch/sparc64/include/openfirm.h +++ b/sys/arch/sparc64/include/openfirm.h @@ -1,4 +1,4 @@ -/* $OpenBSD: openfirm.h,v 1.3 2002/03/14 03:16:00 millert Exp $ */ +/* $OpenBSD: openfirm.h,v 1.4 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: openfirm.h,v 1.8 2001/07/20 00:07:14 eeh Exp $ */ /* @@ -39,13 +39,8 @@ /* All cells are 8 byte slots */ typedef u_int64_t cell_t; -#ifdef __arch64__ #define HDL2CELL(x) (cell_t)(u_int)(int)(x) #define ADR2CELL(x) (cell_t)(x) -#else -#define HDL2CELL(x) (cell_t)(u_int)(int)(x) -#define ADR2CELL(x) (cell_t)(u_int)(int)(x) -#endif int OF_test (char *service); int OF_test_method (int handle, char *method); diff --git a/sys/arch/sparc64/include/param.h b/sys/arch/sparc64/include/param.h index 1f3e8743857..1839527cce7 100644 --- a/sys/arch/sparc64/include/param.h +++ b/sys/arch/sparc64/include/param.h @@ -1,4 +1,4 @@ -/* $OpenBSD: param.h,v 1.10 2002/06/15 00:38:37 art Exp $ */ +/* $OpenBSD: param.h,v 1.11 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: param.h,v 1.25 2001/05/30 12:28:51 mrg Exp $ */ /* @@ -73,15 +73,9 @@ #define _MACHINE sparc64 #define MACHINE "sparc64" -#ifdef __arch64__ #define _MACHINE_ARCH sparc64 #define MACHINE_ARCH "sparc64" #define MID_MACHINE MID_SPARC64 -#else -#define _MACHINE_ARCH sparc -#define MACHINE_ARCH "sparc" -#define MID_MACHINE MID_SPARC -#endif #ifdef _KERNEL /* XXX */ #ifndef _LOCORE /* XXX */ @@ -100,13 +94,7 @@ * (within reasonable limits). * */ -#define ALIGNBYTES32 0x7 -#define ALIGNBYTES64 0xf -#ifdef __arch64__ -#define ALIGNBYTES ALIGNBYTES64 -#else -#define ALIGNBYTES ALIGNBYTES32 -#endif +#define ALIGNBYTES 0xf #define ALIGN(p) (((u_long)(p) + ALIGNBYTES) & ~ALIGNBYTES) #define ALIGN32(p) (((u_long)(p) + ALIGNBYTES32) & ~ALIGNBYTES32) #define ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0) @@ -127,12 +115,8 @@ extern int nbpg, pgofset, pgshift; #define BLKDEV_IOSIZE 2048 #define MAXPHYS (64 * 1024) -#ifdef __arch64__ /* We get stack overflows w/8K stacks in 64-bit mode */ #define SSIZE 2 /* initial stack size in pages */ -#else -#define SSIZE 2 -#endif #define USPACE (SSIZE*8192) diff --git a/sys/arch/sparc64/include/psl.h b/sys/arch/sparc64/include/psl.h index 846a443fedb..2a44d978c59 100644 --- a/sys/arch/sparc64/include/psl.h +++ b/sys/arch/sparc64/include/psl.h @@ -1,4 +1,4 @@ -/* $OpenBSD: psl.h,v 1.7 2002/06/11 05:01:17 art Exp $ */ +/* $OpenBSD: psl.h,v 1.8 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: psl.h,v 1.20 2001/04/13 23:30:05 thorpej Exp $ */ /* @@ -150,21 +150,12 @@ * about possible memory barrier bugs. */ -#ifdef __arch64__ #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) -#else -#define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) -#define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) -#define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) -#define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) -#define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) -#define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) -#endif /* diff --git a/sys/arch/sparc64/include/reg.h b/sys/arch/sparc64/include/reg.h index 4026348d993..5f6e81e3415 100644 --- a/sys/arch/sparc64/include/reg.h +++ b/sys/arch/sparc64/include/reg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: reg.h,v 1.2 2002/03/17 18:38:43 art Exp $ */ +/* $OpenBSD: reg.h,v 1.3 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: reg.h,v 1.8 2001/06/19 12:59:16 wiz Exp $ */ /* @@ -193,19 +193,11 @@ struct fpreg32 { int fr_fsr; /* %fsr */ }; -#if defined(__arch64__) /* Here we gotta do naughty things to let gdb work on 32-bit binaries */ #define reg reg64 #define fpreg fpreg64 #define fpstate fpstate64 #define trapframe trapframe64 #define rwindow rwindow64 -#else -#define reg reg32 -#define fpreg fpreg32 -#define fpstate fpstate32 -#define trapframe trapframe32 -#define rwindow rwindow32 -#endif #endif /* _MACHINE_REG_H_ */ diff --git a/sys/arch/sparc64/include/signal.h b/sys/arch/sparc64/include/signal.h index f273daf3029..237ba5b6191 100644 --- a/sys/arch/sparc64/include/signal.h +++ b/sys/arch/sparc64/include/signal.h @@ -1,4 +1,4 @@ -/* $OpenBSD: signal.h,v 1.3 2001/11/17 20:43:22 deraadt Exp $ */ +/* $OpenBSD: signal.h,v 1.4 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: signal.h,v 1.10 2001/05/09 19:50:49 kleink Exp $ */ /* @@ -65,23 +65,6 @@ typedef int sig_atomic_t; * * All machines must have an sc_onstack and sc_mask. */ -#if defined(__LIBC12_SOURCE__) || defined(_KERNEL) -struct sigcontext13 { - int sc_onstack; /* sigstack state to restore */ - int sc_mask; /* signal mask to restore (old style) */ - /* begin machine dependent portion */ - long sc_sp; /* %sp to restore */ - long sc_pc; /* pc to restore */ - long sc_npc; /* npc to restore */ -#ifdef __arch64__ - long sc_tstate; /* tstate to restore */ -#else - long sc_psr; /* psr portion to restore */ -#endif - long sc_g1; /* %g1 to restore */ - long sc_o0; /* %o0 to restore */ -}; -#endif /* __LIBC12_SOURCE__ || _KERNEL */ struct sigcontext { int sc_onstack; /* sigstack state to restore */ int __sc_mask13; /* signal mask to restore (old style) */ @@ -89,23 +72,11 @@ struct sigcontext { long sc_sp; /* %sp to restore */ long sc_pc; /* pc to restore */ long sc_npc; /* npc to restore */ -#ifdef __arch64__ long sc_tstate; /* tstate to restore */ -#else - long sc_psr; /* psr portion to restore */ -#endif long sc_g1; /* %g1 to restore */ long sc_o0; /* %o0 to restore */ int sc_mask; /* signal mask to restore (new style) */ }; -#else /* _LOCORE */ -/* XXXXX These values don't work for _LP64 */ -#define SC_SP_OFFSET 8 -#define SC_PC_OFFSET 12 -#define SC_NPC_OFFSET 16 -#define SC_PSR_OFFSET 20 -#define SC_G1_OFFSET 24 -#define SC_O0_OFFSET 28 #endif /* _LOCORE */ /* diff --git a/sys/arch/sparc64/include/vmparam.h b/sys/arch/sparc64/include/vmparam.h index 3a940230deb..2bdc7a09b97 100644 --- a/sys/arch/sparc64/include/vmparam.h +++ b/sys/arch/sparc64/include/vmparam.h @@ -1,4 +1,4 @@ -/* $OpenBSD: vmparam.h,v 1.8 2002/03/14 01:26:45 millert Exp $ */ +/* $OpenBSD: vmparam.h,v 1.9 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: vmparam.h,v 1.18 2001/05/01 02:19:19 thorpej Exp $ */ /* @@ -57,12 +57,7 @@ * is the top (end) of the user stack. */ #define USRTEXT 0x2000 /* Start of user text */ -#define USRSTACK32 0xffffe000L -#ifdef __arch64__ #define USRSTACK 0xffffffffffffe000L -#else -#define USRSTACK USRSTACK32 -#endif /* * Virtual memory related constants, all in bytes diff --git a/sys/arch/sparc64/sparc64/autoconf.c b/sys/arch/sparc64/sparc64/autoconf.c index e4f733ec800..de4c6d97c35 100644 --- a/sys/arch/sparc64/sparc64/autoconf.c +++ b/sys/arch/sparc64/sparc64/autoconf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: autoconf.c,v 1.24 2002/06/07 19:31:08 jason Exp $ */ +/* $OpenBSD: autoconf.c,v 1.25 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: autoconf.c,v 1.51 2001/07/24 19:32:11 eeh Exp $ */ /* @@ -110,8 +110,6 @@ char platform_type[32]; static char *str2hex(char *, int *); static int mbprint(void *, const char *); -static void crazymap(char *, int *); -int st_crazymap(int); void sync_crash(void); int mainbus_match(struct device *, void *, void *); static void mainbus_attach(struct device *, struct device *, void *); @@ -227,11 +225,6 @@ bootstrap(nctx) int nctx; { extern int end; /* End of kernel */ -#ifndef __arch64__ - /* Assembly glue for the PROM */ - extern void OF_sym2val32(void *); - extern void OF_val2sym32(void *); -#endif /* * Initialize ddb first and register OBP callbacks. @@ -251,14 +244,8 @@ bootstrap(nctx) #ifdef DDB db_machine_init(); ddb_init(); -#ifdef __arch64__ /* This can only be installed on an 64-bit system cause otherwise our stack is screwed */ OF_set_symbol_lookup(OF_sym2val, OF_val2sym); -#else -#if 1 - OF_set_symbol_lookup(OF_sym2val32, OF_val2sym32); -#endif -#endif #endif pmap_bootstrap(KERNBASE, (u_long)&end, nctx); @@ -466,56 +453,6 @@ bootpath_store(storep, bp) } /* - * Set up the sd target mappings for non SUN4 PROMs. - * Find out about the real SCSI target, given the PROM's idea of the - * target of the (boot) device (i.e., the value in bp->v0val[0]). - */ -static void -crazymap(prop, map) - char *prop; - int *map; -{ - int i; - - /* - * Set up the identity mapping for old sun4 monitors - * and v[2-] OpenPROMs. Note: dkestablish() does the - * SCSI-target juggling for sun4 monitors. - */ - for (i = 0; i < 8; ++i) - map[i] = i; -} - -int -sd_crazymap(n) - int n; -{ - static int prom_sd_crazymap[8]; /* static: compute only once! */ - static int init = 0; - - if (init == 0) { - crazymap("sd-targets", prom_sd_crazymap); - init = 1; - } - return prom_sd_crazymap[n]; -} - -int -st_crazymap(n) - int n; -{ - static int prom_st_crazymap[8]; /* static: compute only once! */ - static int init = 0; - - if (init == 0) { - crazymap("st-targets", prom_st_crazymap); - init = 1; - } - return prom_st_crazymap[n]; -} - - -/* * Determine mass storage and memory configuration for a machine. * We get the PROM's root device and make sure we understand it, then * attach it as `mainbus0'. We also set up to handle the PROM `sync' diff --git a/sys/arch/sparc64/sparc64/clock.c b/sys/arch/sparc64/sparc64/clock.c index c45a1453664..e90738b007c 100644 --- a/sys/arch/sparc64/sparc64/clock.c +++ b/sys/arch/sparc64/sparc64/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.12 2002/04/04 17:01:12 jason Exp $ */ +/* $OpenBSD: clock.c,v 1.13 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: clock.c,v 1.41 2001/07/24 19:29:25 eeh Exp $ */ /* @@ -693,17 +693,7 @@ cpu_initclocks() /* Initialize the %tick register */ lasttick = start_time; -#ifdef __arch64__ __asm __volatile("wrpr %0, 0, %%tick" : : "r" (start_time)); -#else - { - int start_hi = (start_time>>32), start_lo = start_time; - __asm __volatile("sllx %1,32,%0; or %0,%2,%0; wrpr %0, 0, %%tick" - : "=&r" (start_hi) /* scratch register */ - : "r" ((int)(start_hi)), "r" ((int)(start_lo))); - } -#endif - /* * Now handle machines w/o counter-timers. diff --git a/sys/arch/sparc64/sparc64/cpu.c b/sys/arch/sparc64/sparc64/cpu.c index 4cd0b713792..e7de4d8020c 100644 --- a/sys/arch/sparc64/sparc64/cpu.c +++ b/sys/arch/sparc64/sparc64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.8 2002/06/11 10:57:51 art Exp $ */ +/* $OpenBSD: cpu.c,v 1.9 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: cpu.c,v 1.13 2001/05/26 21:27:15 chs Exp $ */ /* @@ -90,39 +90,11 @@ struct cfattach cpu_ca = { extern struct cfdriver cpu_cd; -#if defined(SUN4C) || defined(SUN4M) -static char *psrtoname(int, int, int, char *); -#endif static char *fsrtoname(int, int, int, char *); #define IU_IMPL(v) ((((u_int64_t)(v))&VER_IMPL) >> VER_IMPL_SHIFT) #define IU_VERS(v) ((((u_int64_t)(v))&VER_MASK) >> VER_MASK_SHIFT) -#ifdef notdef -/* - * IU implementations are parceled out to vendors (with some slight - * glitches). Printing these is cute but takes too much space. - */ -static char *iu_vendor[16] = { - "Fujitsu", /* and also LSI Logic */ - "ROSS", /* ROSS (ex-Cypress) */ - "BIT", - "LSIL", /* LSI Logic finally got their own */ - "TI", /* Texas Instruments */ - "Matsushita", - "Philips", - "Harvest", /* Harvest VLSI Design Center */ - "SPEC", /* Systems and Processes Engineering Corporation */ - "Weitek", - "vendor#10", - "vendor#11", - "vendor#12", - "vendor#13", - "vendor#14", - "vendor#15" -}; -#endif - int cpu_match(parent, vcf, aux) struct device *parent; @@ -306,40 +278,6 @@ struct info { #define ANY 0xff /* match any FPU version (or, later, IU version) */ -#if defined(SUN4C) || defined(SUN4M) -static struct info iu_types[] = { - { 1, 0x0, 0x4, 4, "MB86904" }, - { 1, 0x0, 0x0, ANY, "MB86900/1A or L64801" }, - { 1, 0x1, 0x0, ANY, "RT601 or L64811 v1" }, - { 1, 0x1, 0x1, ANY, "RT601 or L64811 v2" }, - { 1, 0x1, 0x3, ANY, "RT611" }, - { 1, 0x1, 0xf, ANY, "RT620" }, - { 1, 0x2, 0x0, ANY, "B5010" }, - { 1, 0x4, 0x0, 0, "TMS390Z50 v0 or TMS390Z55" }, - { 1, 0x4, 0x1, 0, "TMS390Z50 v1" }, - { 1, 0x4, 0x1, 4, "TMS390S10" }, - { 1, 0x5, 0x0, ANY, "MN10501" }, - { 1, 0x9, 0x0, ANY, "W8601/8701 or MB86903" }, - { 0 } -}; - -static char * -psrtoname(impl, vers, fver, buf) - register int impl, vers, fver; - char *buf; -{ - register struct info *p; - - for (p = iu_types; p->valid; p++) - if (p->iu_impl == impl && p->iu_vers == vers && - (p->fpu_vers == fver || p->fpu_vers == ANY)) - return (p->name); - - /* Not found. */ - sprintf(buf, "IU impl 0x%x vers 0x%x", impl, vers); - return (buf); -} -#endif /* SUN4C || SUN4M */ /* NB: table order matters here; specific numbers must appear before ANY. */ static struct info fpu_types[] = { diff --git a/sys/arch/sparc64/sparc64/cpuvar.h b/sys/arch/sparc64/sparc64/cpuvar.h index 64995988923..fa6f3330c55 100644 --- a/sys/arch/sparc64/sparc64/cpuvar.h +++ b/sys/arch/sparc64/sparc64/cpuvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuvar.h,v 1.3 2002/03/14 01:26:45 millert Exp $ */ +/* $OpenBSD: cpuvar.h,v 1.4 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: cpuvar.h,v 1.2 1999/11/06 20:18:13 eeh Exp $ */ /* @@ -45,35 +45,6 @@ #include <sparc64/sparc64/cache.h> /* for cacheinfo */ /* - * CPU/MMU module information. - * There is one of these for each "mainline" CPU module we support. - * The information contained in the structure is used only during - * auto-configuration of the CPUs; some fields are copied into the - * per-cpu data structure (cpu_softc) for easy access during normal - * operation. - */ -struct cpu_softc; -struct module_info { - int cpu_type; - enum vactype vactype; - void (*cpu_match)(struct cpu_softc *, struct module_info *, int); - void (*getcacheinfo)(struct cpu_softc *sc, int node); - void (*hotfix)(struct cpu_softc *); - void (*mmu_enable)(void); - void (*cache_enable)(void); - int ncontext; /* max. # of contexts (we use) */ - - void (*get_faultstatus)(void); - void (*cache_flush)(caddr_t, u_int); - void (*vcache_flush_page)(int); - void (*vcache_flush_segment)(int, int); - void (*vcache_flush_region)(int); - void (*vcache_flush_context)(void); - void (*pcache_flush_line)(int, int); -}; - - -/* * The cpu_softc structure. This structure maintains information about one * currently installed CPU (there may be several of these if the machine * supports multiple CPUs, as on some Sun4m architectures). The information @@ -87,63 +58,17 @@ struct cpu_softc { int node; /* PROM node for this CPU */ /* CPU information */ - char *cpu_name; /* CPU model */ - int cpu_impl; /* CPU implementation code */ - int cpu_vers; /* CPU version code */ - int mmu_impl; /* MMU implementation code */ - int mmu_vers; /* MMU version code */ - int master; /* 1 if this is bootup CPU */ - int id; /* Module ID for MP systems */ int bus; /* 1 if CPU is on MBus */ - int mxcc; /* 1 if a MBus-level MXCC is present */ - - caddr_t mailbox; /* VA of CPU's mailbox */ - - - int mmu_ncontext; /* Number of contexts supported */ - int mmu_nregion; /* Number of regions supported */ - int mmu_nsegment; /* [4/4c] Segments */ - int mmu_npmeg; /* [4/4c] Pmegs */ - int sun4_mmu3l; /* [4]: 3-level MMU present */ -#if defined(SUN4_MMU3L) -#define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l) -#else -#define HASSUN4_MMU3L (0) -#endif - - /* Context administration */ - int *ctx_tbl; /* [4m] SRMMU-edible context table */ - union ctxinfo *ctxinfo; - union ctxinfo *ctx_freelist; /* context free list */ - int ctx_kick; /* allocation rover when none free */ - int ctx_kickdir; /* ctx_kick roves both directions */ - - /* MMU tables that map `cpuinfo'' on each CPU */ - int *L1_ptps; /* XXX */ /* XXX - of these, we currently use only cpu_type */ int arch; /* Architecture: CPU_SUN4x */ - int class; /* Class: SuperSPARC, microSPARC... */ - int classlvl; /* Iteration in class: 1, 2, etc. */ - int classsublvl; /* stepping in class (version) */ - int cpu_type; /* Type: see CPUTYP_xxx below */ int hz; /* Clock speed */ /* Cache information */ struct cacheinfo cacheinfo; /* see cache.h */ - /* FPU information */ - int fpupresent; /* true if FPU is present */ - int fpuvers; /* FPU revision */ - - /* various flags to workaround anomalies in chips */ - int flags; /* see CPUFLG_xxx, below */ - - /* Per processor counter register (sun4m only) */ - struct counter_4m *counterreg_4m; - /* * The following pointers point to processes that are somehow * associated with this CPU--running on it, using its FPU, @@ -152,41 +77,6 @@ struct cpu_softc { * XXXMP: much more needs to go here */ struct proc *fpproc; /* FPU owner */ - - /* - * The following are function pointers to do interesting CPU-dependent - * things without having to do type-tests all the time - */ - - /* bootup things: access to physical memory */ - u_int (*read_physmem)(u_int addr, int space); - void (*write_physmem)(u_int addr, u_int data); - void (*cache_tablewalks)(void); - void (*mmu_enable)(void); - void (*hotfix)(struct cpu_softc *); - - /* locore defined: */ - void (*get_faultstatus)(void); - - /* Cache handling functions */ - void (*cache_enable)(void); - void (*cache_flush)(caddr_t, u_int); - void (*vcache_flush_page)(int); - void (*vcache_flush_segment)(int, int); - void (*vcache_flush_region)(int); - void (*vcache_flush_context)(void); - void (*pcache_flush_line)(int, int); - -#ifdef SUN4M - /* hardware-assisted block operation routines */ - void (*hwbcopy)(const void *from, void *to, size_t len); - void (*hwbzero)(void *buf, size_t len); - - /* routine to clear mbus-sbus buffers */ - void (*mbusflush)(void); -#endif - - /* XXX: Add more here! */ }; /* @@ -204,73 +94,14 @@ struct cpu_softc { */ #define CPUCLS_UNKNOWN 0 -#if defined(SUN4) -#define CPUCLS_SUN4 1 -#endif - -#if defined(SUN4C) -#define CPUCLS_SUN4C 5 -#endif - -#if defined(SUN4M) -#define CPUCLS_MICROSPARC 10 /* MicroSPARC-II */ -#define CPUCLS_SUPERSPARC 11 /* Generic SuperSPARC */ -#define CPUCLS_HYPERSPARC 12 /* Ross HyperSPARC RT620 */ -#endif - /* * CPU busses */ #define CPU_NONE 0 /* No particular bus */ -#define CPU_MBUS 1 /* SBUS attached */ #define CPU_UPA 2 /* UPA bus attached */ /* - * CPU types. Each of these should uniquely identify one platform/type of - * system, i.e. "MBus-based 75 MHz SuperSPARC-II with ECache" is - * CPUTYP_SS2_MBUS_MXCC. The general form is - * CPUTYP_proctype_bustype_cachetype_etc_etc - * - * XXX: This is far from complete/comprehensive - * XXX: ADD SUN4, SUN4C TYPES - */ -#define CPUTYP_UNKNOWN 0 - -#define CPUTYP_4_100 1 /* Sun4/100 */ -#define CPUTYP_4_200 2 /* Sun4/200 */ -#define CPUTYP_4_300 3 /* Sun4/300 */ -#define CPUTYP_4_400 4 /* Sun4/400 */ - -#define CPUTYP_SLC 10 /* SPARCstation SLC */ -#define CPUTYP_ELC 11 /* SPARCstation ELC */ -#define CPUTYP_IPX 12 /* SPARCstation IPX */ -#define CPUTYP_IPC 13 /* SPARCstation IPC */ -#define CPUTYP_1 14 /* SPARCstation 1 */ -#define CPUTYP_1P 15 /* SPARCstation 1+ */ -#define CPUTYP_2 16 /* SPARCstation 2 */ - -/* We classify the Sun4m's by feature, not by model (XXX: do same for 4/4c) */ -#define CPUTYP_SS2_MBUS_MXCC 20 /* SuperSPARC-II, Mbus, MXCC (SS20) */ -#define CPUTYP_SS1_MBUS_MXCC 21 /* SuperSPARC-I, Mbus, MXCC (SS10) */ -#define CPUTYP_SS2_MBUS_NOMXCC 22 /* SuperSPARC-II, on MBus w/o MXCC */ -#define CPUTYP_SS1_MBUS_NOMXCC 23 /* SuperSPARC-I, on MBus w/o MXCC */ -#define CPUTYP_MS2 24 /* MicroSPARC-2 */ -#define CPUTYP_MS1 25 /* MicroSPARC-1 */ -#define CPUTYP_HS_MBUS 26 /* MBus-based HyperSPARC */ -#define CPUTYP_CYPRESS 27 /* MBus-based Cypress */ - -/* - * CPU flags - */ -#define CPUFLG_CACHEPAGETABLES 0x1 /* caching pagetables OK on Sun4m */ -#define CPUFLG_CACHEIOMMUTABLES 0x2 /* caching IOMMU translations OK */ -#define CPUFLG_CACHEDVMA 0x4 /* DVMA goes through cache */ -#define CPUFLG_SUN4CACHEBUG 0x8 /* trap page can't be cached */ -#define CPUFLG_CACHE_MANDATORY 0x10 /* if cache is on, don't use - uncached access */ - -/* * Related function prototypes */ void getcpuinfo(struct cpu_softc *sc, int node); diff --git a/sys/arch/sparc64/sparc64/db_interface.c b/sys/arch/sparc64/sparc64/db_interface.c index 138bfc6656e..056c9fb09aa 100644 --- a/sys/arch/sparc64/sparc64/db_interface.c +++ b/sys/arch/sparc64/sparc64/db_interface.c @@ -1,4 +1,4 @@ -/* $OpenBSD: db_interface.c,v 1.10 2002/06/11 08:09:42 mdw Exp $ */ +/* $OpenBSD: db_interface.c,v 1.11 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: db_interface.c,v 1.61 2001/07/31 06:55:47 eeh Exp $ */ /* @@ -515,17 +515,10 @@ db_dump_dtlb(addr, have_addr, count, modif) dump_dtlb(buf); p = buf; for (i=0; i<64;) { -#ifdef __arch64__ db_printf("%2d:%16.16lx %16.16lx ", i++, p[0], p[1]); p += 2; db_printf("%2d:%16.16lx %16.16lx\n", i++, p[0], p[1]); p += 2; -#else - db_printf("%2d:%16.16qx %16.16qx ", i++, p[0], p[1]); - p += 2; - db_printf("%2d:%16.16qx %16.16qx\n", i++, p[0], p[1]); - p += 2; -#endif } } } else { diff --git a/sys/arch/sparc64/sparc64/disksubr.c b/sys/arch/sparc64/sparc64/disksubr.c index 75d9d478363..7746630555c 100644 --- a/sys/arch/sparc64/sparc64/disksubr.c +++ b/sys/arch/sparc64/sparc64/disksubr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: disksubr.c,v 1.8 2002/03/14 01:26:45 millert Exp $ */ +/* $OpenBSD: disksubr.c,v 1.9 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: disksubr.c,v 1.13 2000/12/17 22:39:18 pk Exp $ */ /* @@ -48,9 +48,6 @@ #include <machine/autoconf.h> #include <machine/cpu.h> -#if defined(SUN4) -#include <machine/oldmon.h> -#endif #include <dev/sbus/sbusvar.h> #include "cd.h" diff --git a/sys/arch/sparc64/sparc64/machdep.c b/sys/arch/sparc64/sparc64/machdep.c index 8472f106339..c4e0764f119 100644 --- a/sys/arch/sparc64/sparc64/machdep.c +++ b/sys/arch/sparc64/sparc64/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.43 2002/06/14 21:34:59 todd Exp $ */ +/* $OpenBSD: machdep.c,v 1.44 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: machdep.c,v 1.108 2001/07/24 19:30:14 eeh Exp $ */ /*- @@ -108,13 +108,6 @@ #include <uvm/uvm.h> #include <sys/sysctl.h> -#ifndef ELFSIZE -#ifdef __arch64__ -#define ELFSIZE 64 -#else -#define ELFSIZE 32 -#endif -#endif #include <sys/exec_elf.h> #ifdef SYSVMSG @@ -427,15 +420,10 @@ allocsys(caddr_t v) * Set up registers on exec. */ -#ifdef __arch64__ #define STACK_OFFSET BIAS #define CPOUTREG(l,v) copyout(&(v), (l), sizeof(v)) #undef CCFSZ #define CCFSZ CC64FSZ -#else -#define STACK_OFFSET 0 -#define CPOUTREG(l,v) copyout(&(v), (l), sizeof(v)) -#endif /* ARGSUSED */ void @@ -449,9 +437,7 @@ setregs(p, pack, stack, retval) struct fpstate64 *fs; int64_t tstate; int pstate = PSTATE_USER; -#ifdef __arch64__ Elf_Ehdr *eh = pack->ep_hdr; -#endif /* Don't allow misaligned code by default */ p->p_md.md_flags &= ~MDP_FIXALIGN; @@ -463,7 +449,6 @@ setregs(p, pack, stack, retval) * %g1: address of PS_STRINGS (used by crt0) * %tpc,%tnpc: entry point of program */ -#ifdef __arch64__ /* Check what memory model is requested */ switch ((eh->e_flags & EF_SPARCV9_MM)) { default: @@ -480,7 +465,7 @@ setregs(p, pack, stack, retval) pstate = PSTATE_MM_RMO|PSTATE_IE; break; } -#endif + tstate = (ASI_PRIMARY_NO_FAULT<<TSTATE_ASI_SHIFT) | ((pstate)<<TSTATE_PSTATE_SHIFT) | (tf->tf_tstate & TSTATE_CWP); @@ -526,10 +511,6 @@ struct sigframe { int sf_signo; /* signal number */ int sf_code; /* signal code (unused) */ siginfo_t *sf_sip; /* points to siginfo_t */ -#ifndef __arch64__ - struct sigcontext *sf_scp; /* SunOS user addr of sigcontext */ - int sf_addr; /* SunOS compat, always 0 for now */ -#endif struct sigcontext sf_sc; /* actual sigcontext */ siginfo_t sf_si; }; @@ -668,10 +649,6 @@ sendsig(catcher, sig, mask, code, type, val) */ sf.sf_signo = sig; sf.sf_sip = NULL; -#ifndef __arch64__ - sf.sf_scp = 0; - sf.sf_addr = 0; /* XXX */ -#endif /* * Build the signal context to be used by sigreturn. @@ -682,11 +659,7 @@ sendsig(catcher, sig, mask, code, type, val) sf.sf_sc.sc_sp = (long)tf->tf_out[6]; sf.sf_sc.sc_pc = tf->tf_pc; sf.sf_sc.sc_npc = tf->tf_npc; -#ifdef __arch64__ sf.sf_sc.sc_tstate = tf->tf_tstate; /* XXX */ -#else - sf.sf_sc.sc_psr = TSTATECCR_TO_PSR(tf->tf_tstate); /* XXX */ -#endif sf.sf_sc.sc_g1 = tf->tf_global[1]; sf.sf_sc.sc_o0 = tf->tf_out[0]; @@ -798,11 +771,7 @@ sys_sigreturn(p, v, retval) } /* take only psr ICC field */ -#ifdef __arch64__ tf->tf_tstate = (u_int64_t)(tf->tf_tstate & ~TSTATE_CCR) | (scp->sc_tstate & TSTATE_CCR); -#else - tf->tf_tstate = (u_int64_t)(tf->tf_tstate & ~TSTATE_CCR) | PSRCC_TO_TSTATE(scp->sc_psr); -#endif tf->tf_pc = (u_int64_t)scp->sc_pc; tf->tf_npc = (u_int64_t)scp->sc_npc; tf->tf_global[1] = (u_int64_t)scp->sc_g1; diff --git a/sys/arch/sparc64/sparc64/netbsd_machdep.c b/sys/arch/sparc64/sparc64/netbsd_machdep.c index 0a3bcd9a6a6..c5c527cb5f5 100644 --- a/sys/arch/sparc64/sparc64/netbsd_machdep.c +++ b/sys/arch/sparc64/sparc64/netbsd_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: netbsd_machdep.c,v 1.2 2001/11/06 19:53:16 miod Exp $ */ +/* $OpenBSD: netbsd_machdep.c,v 1.3 2002/06/15 17:23:31 art Exp $ */ /*- * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. @@ -120,22 +120,13 @@ extern int sigpid; struct netbsd_sigframe { int sf_signo; /* signal number */ int sf_code; /* code */ -#ifndef __arch64__ - struct sigcontext *sf_scp; /* SunOS user addr of sigcontext */ - int sf_addr; /* SunOS compat, always 0 for now */ -#endif struct netbsd_sigcontext sf_sc; /* actual sigcontext */ }; -#ifdef __arch64__ #define STACK_OFFSET BIAS #define CPOUTREG(l,v) copyout(&(v), (l), sizeof(v)) #undef CCFSZ #define CCFSZ CC64FSZ -#else -#define STACK_OFFSET 0 -#define CPOUTREG(l,v) copyout(&(v), (l), sizeof(v)) -#endif /* * Send an interrupt to process. @@ -184,10 +175,6 @@ netbsd_sendsig(catcher, sig, mask, code, type, val) */ sf.sf_signo = sig; sf.sf_code = 0; /* XXX */ -#ifndef __arch64__ - sf.sf_scp = 0; - sf.sf_addr = 0; /* XXX */ -#endif /* * Build the signal context to be used by sigreturn. @@ -198,11 +185,7 @@ netbsd_sendsig(catcher, sig, mask, code, type, val) sf.sf_sc.sc_sp = (long)tf->tf_out[6]; sf.sf_sc.sc_pc = tf->tf_pc; sf.sf_sc.sc_npc = tf->tf_npc; -#ifdef __arch64__ sf.sf_sc.sc_tstate = tf->tf_tstate; /* XXX */ -#else - sf.sf_sc.sc_psr = TSTATECCR_TO_PSR(tf->tf_tstate); /* XXX */ -#endif sf.sf_sc.sc_g1 = tf->tf_global[1]; sf.sf_sc.sc_o0 = tf->tf_out[0]; @@ -276,13 +259,8 @@ netbsd_sys___sigreturn14(p, v, retval) (nbsc.sc_pc == 0) || (nbsc.sc_npc == 0)) return (EINVAL); /* take only psr ICC field */ -#ifdef __arch64__ tf->tf_tstate = (u_int64_t)(tf->tf_tstate & ~TSTATE_CCR) | (scp->sc_tstate & TSTATE_CCR); -#else - tf->tf_tstate = (u_int64_t)(tf->tf_tstate & ~TSTATE_CCR) | - PSRCC_TO_TSTATE(scp->sc_psr); -#endif tf->tf_pc = (u_int64_t)scp->sc_pc; tf->tf_npc = (u_int64_t)scp->sc_npc; tf->tf_global[1] = (u_int64_t)scp->sc_g1; diff --git a/sys/arch/sparc64/sparc64/process_machdep.c b/sys/arch/sparc64/sparc64/process_machdep.c index ade3346b299..eaf29ff35c7 100644 --- a/sys/arch/sparc64/sparc64/process_machdep.c +++ b/sys/arch/sparc64/sparc64/process_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: process_machdep.c,v 1.4 2002/03/17 18:38:43 art Exp $ */ +/* $OpenBSD: process_machdep.c,v 1.5 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: process_machdep.c,v 1.10 2000/09/26 22:05:50 eeh Exp $ */ /* @@ -87,7 +87,6 @@ process_read_regs(p, regs) struct reg32* regp = (struct reg32*)regs; int i; -#ifdef __arch64__ if (!(curproc->p_flag & P_32)) { /* 64-bit mode -- copy out regs */ regs->r_tstate = tf->tf_tstate; @@ -102,7 +101,7 @@ process_read_regs(p, regs) } return (0); } -#endif + /* 32-bit mode -- copy out & convert 32-bit regs */ regp->r_psr = TSTATECCR_TO_PSR(tf->tf_tstate); regp->r_pc = tf->tf_pc; @@ -154,7 +153,6 @@ process_write_regs(p, regs) struct reg32* regp = (struct reg32*)regs; int i; -#ifdef __arch64__ if (!(curproc->p_flag & P_32)) { /* 64-bit mode -- copy in regs */ tf->tf_pc = regs->r_pc; @@ -169,7 +167,7 @@ process_write_regs(p, regs) (regs->r_tstate & TSTATE_CCR); return (0); } -#endif + /* 32-bit mode -- copy in & convert 32-bit regs */ tf->tf_pc = regp->r_pc; tf->tf_npc = regp->r_npc; diff --git a/sys/arch/sparc64/sparc64/trap.c b/sys/arch/sparc64/sparc64/trap.c index 98b919289b5..d3599549dfd 100644 --- a/sys/arch/sparc64/sparc64/trap.c +++ b/sys/arch/sparc64/sparc64/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.19 2002/05/16 21:11:18 miod Exp $ */ +/* $OpenBSD: trap.c,v 1.20 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: trap.c,v 1.73 2001/08/09 01:03:01 eeh Exp $ */ /* @@ -1308,7 +1308,7 @@ syscall(tf, code, pc) if (error) goto bad; } else { -#if defined(__arch64__) && !defined(COMPAT_NETBSD32) +#if !defined(COMPAT_NETBSD32) error = EFAULT; goto bad; #else @@ -1337,7 +1337,6 @@ syscall(tf, code, pc) *argp++ = *ap++; #ifdef KTRACE if (KTRPOINT(p, KTR_SYSCALL)) { -#if defined(__arch64__) register_t temp[8]; /* Need to xlate 32-bit->64-bit */ @@ -1347,16 +1346,12 @@ syscall(tf, code, pc) temp[j] = args.i[j]; ktrsyscall(p, code, i * sizeof(register_t), (register_t *)temp); -#else - ktrsyscall(p, code, - callp->sy_argsize, (register_t *)args.i); -#endif } #endif if (error) { goto bad; } -#endif /* __arch64__ && !COMPAT_NETBSD32 */ +#endif /* !COMPAT_NETBSD32 */ } #ifdef SYSCALL_DEBUG scdebug_call(p, code, (register_t *)&args); diff --git a/sys/arch/sparc64/sparc64/vm_machdep.c b/sys/arch/sparc64/sparc64/vm_machdep.c index 72b95f68a16..e770ad5a7ff 100644 --- a/sys/arch/sparc64/sparc64/vm_machdep.c +++ b/sys/arch/sparc64/sparc64/vm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vm_machdep.c,v 1.7 2002/03/14 01:26:45 millert Exp $ */ +/* $OpenBSD: vm_machdep.c,v 1.8 2002/06/15 17:23:31 art Exp $ */ /* $NetBSD: vm_machdep.c,v 1.38 2001/06/30 00:02:20 eeh Exp $ */ /* @@ -179,28 +179,14 @@ vunmapbuf(bp, len) uvm_km_free_wakeup(kernel_map, kva, len); bp->b_data = bp->b_saveaddr; bp->b_saveaddr = NULL; - -#if 0 /* XXX: The flush above is sufficient, right? */ - if (CACHEINFO.c_vactype != VAC_NONE) - cpuinfo.cache_flush(bp->b_data, len); -#endif } /* * The offset of the topmost frame in the kernel stack. */ -#ifdef __arch64__ #define TOPFRAMEOFF (USPACE-sizeof(struct trapframe)-CC64FSZ) #define STACK_OFFSET BIAS -#else -#undef trapframe -#define trapframe trapframe64 -#undef rwindow -#define rwindow rwindow32 -#define TOPFRAMEOFF (USPACE-sizeof(struct trapframe)-CC64FSZ) -#define STACK_OFFSET 0 -#endif #ifdef DEBUG char cpu_forkname[] = "cpu_fork()"; |