Age | Commit message (Collapse) | Author |
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- Reorder parameters list in the first usage() case
- Sentence rewording
ok dtucker@
jmc@ noticed usage() missed -a flag too
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for the vnode.
ok beck@
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used by the processor chip. Although we have a SENSOR_WATTHOUR sensor
type its units are not really suitable for this sensor. So add a
SENSOR_ENERGY type that uses micro Joules as its unit.
ok deraadt@
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(on OpenBSD) or out of tree (in Portable).
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ok dlg@
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ok dlg@
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bettertls.com, and a verification suite to try each certificate
in the same manner as the web based tests do using X509_verify.
This includes the list of "known" failures today in our validaion
code so we can move forward without moving back.
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to hint we are doing the minimum scheduler sleep (and as side effect,
collecting potential signal status)
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via $SSH_ASKPASS_REQUIRE, including force-enable/disable.
bz#69 ok markus@
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ok patrick@
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ok inoguchi@, tb@
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ok inoguchi@ tb@
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This is no longer necessary since the TLS_method() now supports TLSv1.3.
Reverts r1.211 of ssl_lib.c.
ok beck@ inoguchi@ tb@
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A number of these tests are known to fail due to bugs/incorrect
verification implementation.
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ok beck@ tb@
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This provides a script that generates a variety of certificate chains
and assembles them into bundles containing various permutations, which
can be used to test our X.509 verification.
A Go program is included to verify each of these bundles.
ok beck@ tb@
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callers use spltty.
ok kettenis
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Otherwise we end up switching to TLSv1.3 and using a TLSv1.3 cipher suite.
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a mapping from the page tables.
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be 8 bytes in the 64-bit ABI just like in the 32-bit ABI. But that means
there is no "spare" word in the TCB that we can use to store a pointer
to our struct pthread. So we have to treat powerpc64 special.
Also recognize that the thread pointer points 0x7000 bytes after the TCB.
Since the TCB is 8 bytes this means that TCB_OFFSET should be 0x7008.
Pointed out by guenther@; ok deraadt@
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Makes the test work on architectures where char is unsigned.
ok deraadt@, millert@
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supporting code was already there. The driver supports establishing multiple
handlers on the same pin. Make sure that a single pin can only be established
on a specific core by recording the struct cpu_info * of the first establish,
and returning NULL if someone tries to share the pin with a different core.
For LPIs, typically used for MSIs, the routing is done by targetting an LPI
to a specific "collection". We create a collection per core, indexing it by
cpu_number().
For this we need to know a CPU's "processor number", unless GITS_TYPER_PTA is
set. Since we now attach CPUs early, and the redistributors are not banked,
we can retrieve that information early on. It's important to move this as far
up as possible, as it's not as easy as on ampintc(4) to re-route LPIs.
To establish an LPI on a different core, we now only have the pass the CPU's
number as part of the map command which is sent to the hardware.
Prompted by dlg@
ok kettenis@
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supporting code was already there. The driver supports establishing multiple
handlers on the same pin. Make sure that a single pin can only be established
on a specific core by recording the struct cpu_info * of the first establish,
and returning NULL if someone tries to share the pin with a different core.
Since the array of CPU masks, used for enabling/disabling interrupt routing to
specific cores, is only populated during cpu_boot_secondary_processors(), each
core will re-route the interrupts once a core read its mask. Until then, the
core will not receive interrupts for that pin.
While there, remove a call to ampintc_setipl(), which seems to be a no-op. It
tries to set the same value that's already set. Since the function that calls
it is supposed to calculate a pin's mask and do the routing, this doesn't seem
to be the correct place for such a call. agintc(4) doesn't have it either.
Prompted by dlg@
ok kettenis@
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in the chipset tag for establishing interrupts now takes a struct cpu_info *.
The normal pci_intr_establish() macro passes NULL as ci, which indicates that
the primary CPU is to be used.
The PCI controller drivers can then simply pass the ci on to our arm64/armv7
interrupt establish "framework".
Prompted by dlg@
ok kettenis@
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a struct cpu_info *. From a driver point of view the fdt_intr_establish_*
API now also exist same functions with a *_cpu suffix. Internally the
"old" functions now call their *_cpu counterparts, passing NULL as ci.
NULL will be interpreted as primary CPU in the interrupt controller code.
The internal framework for interrupt controllers has been changed so that
the establish methods provided by an interrupt controller function always
takes a struct cpu_info *.
Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt
line for multiple pins. On those we simply disallow trying to establish
an interrupt on a non-primary CPU, returning NULL.
Since we do not have MP yet on armv7, all armv7 interrupt controllers do
return NULL if an attempt is made to establish an interrupt on a different
CPU. That said, so far there's no way this can happen. If we ever gain
MP support, this is a reminder that the interrupt controller drivers have
to be adjusted.
Prompted by dlg@
ok kettenis@
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VERASE would perform (sometimes irrelevant) compute in the kernel which
can be heavy (especially with our insufficient tty subsystem locking). Use
tsleep_nsec for 1 tick in such circumstances to yield cpu, and also bring
interruptability to ptcwrite()
https://syzkaller.appspot.com/bug?extid=462539bc18fef8fc26cc
ok kettenis millert, discussions with greg and anton
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brings in changes from
'drm/ttm: stop always moving BOs on the LRU on page fault'
5d50fcbda7b0acd301bb1fc3d828df0aa29237b8
and some other minor changes
ok kettenis@
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ok jmc@
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into more delayed writes if the vnd is mounted from a file on an MNT_ASYNC
filesystem. This prevents a situaiton where the cleaner can not clean
delayed writes out without making more delayed writes, and we end up
waiting for the syncer to spit things occasionaly when it runs.
noticed and reported by sven falempin <sven.falempin@gmail.com> on tech,
who validated this fixes his issue.
ok krw@
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entries to forwarding packets to it. The RSS flow table contains flow
table entries that match specific types of traffic and send them to TIRs
set up to hash on the appropriate fields, then deliver packets through an
RQT to all our rx queues. We still only have one queue, but now all we
need to do is plug in an intrmap to add more.
ok dlg@
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negotiations fail.
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<machine/frame.h>.
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