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This mandatory function will get invoked in pci_probe_device(), and allows
a pci host driver to alter the pci_attach_args passed to a device when
attaching.
This function will also, if returning non-zero, cause the device to be
skipped completely during all the phases of the PCI device discovery
(i.e. ressource enumeration, ressource assignment, and actual attachment).
This particular feature is experimental and might be reverted in the future
(or the scope narrowed to device attachment only).
A dummy #define pci_probe_device_hook() 0 is added to all platforms except
sgi, where real functions (currently only returning 0) are added; real meat
will be added shortly.
Discussed at s2k11, no objection from the usual suspects.
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(interrupt was not for me), 1 (positive interrupt was for me), or -1
(i am not sure...). We have continued with this practice in as many
drivers as possible, throughout the tree.
This makes some of the architectures use that information in their
interrupt handler calling code -- if 1 is returned (and we know
this specific machine does not have edge-shared interrupts), we
finish servicing other possible handlers on the same pin. If the
interrupt pin remains asserted (from a different device), we will
end up back in the interrupt servicing code of course... but this is
cheaper than calling all the chained interrupts on a pin.
This does of course count on shared level interrupts being properly
sorted by IPL.
There have been some concerns about starvation of drivers which
incorrectly return 1. Those drivers should be hunted down so that
they return -1.
(other architectures will follow)
ok kettenis drahn dlg miod
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given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@
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Bogus chunks pointed out by matthew@ and miod@. No cookies for
marco@ and jasper@.
ok deraadt@ miod@ matthew@ jasper@ macro@
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ok kettenis, deraadt
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side effect, this change makes displayed messages shorter.
miod@ has observed that `Horse' is the codename of the chip, which
gets paired with a `Saddle' companion chip. there is one hose
(i.e., bus) per chip; others (`Tsunami') have two hoses per chip,
or even four (`Typhoon'); so, `Horse' is not really a typo.
written with clever advice from krw@ and miod@
miod@ has suggested the capitalization for `Saddle'.
ok krw@, miod@
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are very close to the Tsunami systems (rpb family 34) and share the existing
Tsunami code; the tsc(4) Tsunami controller code is extended to handle the
Titan differences, except for the Titan AGP GART which is left unsupported
for now.
Tested to not cause regressions on DS20 (deraadt@) and ES40 (miod@).
Titan support tested by Sergey Prysiazhnyi on DS25, many thanks for your time!
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From FreeBSD.
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BUS_SPACE_MAP_LINEAR in i/o space, or noncacheable linear TURBOchannel
mappings).
From NetBSD
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tga on non-bwx machines. Reported and fix tested by kurt@
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Tested by myself, sthen, oga, kettenis, and jasper.
Input from sthen and jasper.
ok kettenis
(Manpage follows shortly.)
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provide and use BUS_SPACE_BARRIER_xxx.
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bus_space_alloc() as a bitmask of flags, and not a boolean controlling
cacheability; and make sure the three MI BUS_SPACE_MAP_xxx values documented
in the manual page are defined on all platforms as well.
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from ray; ok ray, deraadt
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from NetBSD.
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the motherboard eisa id, instead of using a ``one size fits all'' value which
is too large on more than half the eisa-capable alpha designs.
The id -> slot # logic is based on the alpha ECU configuration files, so we
should not perform worse than ECU itself (and see all slots ECU sees too).
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bother trying to probe more.
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configures when it can. ok kettenis@
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per-platform implementation, instead of selected members of it; this allows
us to get rid of some globals, and paves the way for better bridge support
on some models.
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plugged to the bottom 4 PCI slots of AlphaServer 1000A (attaching to pci1
behind a ppb) to get interrupts.
No regressions on AlphaServer 800 (which do not have these extra slots).
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is not used yet, but this seems to ``warm up'' the eisa chips so that
accesses to the eisa bus later do not cause machine checks.
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instead of only the starting address. From NetBSD.
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Not sure what's more surprising: how long it took for NetBSD to
catch up to the rest of the BSDs (including UCB), or the amount of
code that NetBSD has claimed for itself without attributing to the
actual authors.
OK deraadt@
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appropriate. Removes unwanted messages that got printed when mapping pins
on PCI-PCI bridges that don't matter.
ok miod@
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ok brad@ fgsch@ also tested by oga@
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size(*p) as the first malloc() parameter where p is declared locally
and thus easy to check. Add M_ZERO to gpe_table allocation in acpi.c
even though there is no obvious bzero or memset nearby.
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platform interrupt string when establishing pciide interrupts
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that have over 1.0G. Allow direct dma requests to fall back to SGMAPs.
From NetBSD via brad; discussed with Miod, tested by myself
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This code makes it possible to run on some of the AlphaServers,
namely AlphaServer 4100 and 1200.
add mcbus(4) and mcpcia(4) to provide support for the system bus and
the MCPCIA-to-PCI bus adapter that can be found in these systems
allow the pci_swiz_bus code to handle variable extent names
to be able to handle more than one mcpcia(4)
"just commit it" deraadt@
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domain number such that we can distinguish between busses with the same bus
number that are behind different host bridges. Domains can be accessed by
using different device nodes.
ok deraadt@
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Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors.
From thorpej NetBSD
Tested by myself and a number of end-users.
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eventually we can determine whether or not to allocate a spill
page on a per-mapping basis.
From NetBSD
ok martin@
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remove alpha_pci_decompose_tag().
From NetBSD
ok martin@
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ok miod@, additional testing jsg@
from NetBSD
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used. No functional change.
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NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
From NetBSD
ok grange@ kettenis@
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interrupt counter for a given shared interrupt descriptor.
When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector.
from NetBSD via KUDO Takashi
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from KUDO Takashi
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