| Age | Commit message (Expand) | Author |
|---|
| 2024-06-24 | Show AMD SEV bits during identify CPU in dmesg. | Alexander Bluhm |
| 2024-06-09 | Add a compiler barrier where missing in CPU_BUSY_CYCLE() implems | Jeremie Courreges-Anglas |
| 2024-06-07 | Make sure we select the deepest possible C-state during suspend-to-idle. | Mark Kettenis |
| 2024-05-29 | Implement the guts for "suspend-to-idle" on amd64. This enables suspend | Mark Kettenis |
| 2024-05-21 | remove switch_exit() prototypes, replaced by sched_exit() | Jonathan Gray |
| 2024-05-12 | Delete the cpu_perf_e[abd]x and cpu_apmi_edx globals and move the | Philip Guenther |
| 2024-05-01 | Add per-CPU caches to the pmemrange allocator. | Martin Pieuchot |
| 2024-04-19 | Revert per-CPU caches a double-free has been found by naddy@. | Martin Pieuchot |
| 2024-04-17 | Add per-CPU caches to the pmemrange allocator. | Martin Pieuchot |
| 2024-04-14 | Implement support for AVX-512. This required some fixes to the so-far | Mark Kettenis |
| 2024-04-03 | Add ci_cpuid_level and ci_vendor holding the per-CPU basic cpuid | Philip Guenther |
| 2024-02-25 | clockintr: rename "struct clockintr_queue" to "struct clockqueue" | Scott Soule Cheloha |
| 2024-02-12 | Retpolines are an anti-pattern for IBT, so we need to shift protecting | Philip Guenther |
| 2024-02-03 | Add new amd64-only sysctl machdep.retpoline which says whether the cpu | Theo de Raadt |
| 2024-01-24 | clockintr: switch from callee- to caller-allocated clockintr structs | Scott Soule Cheloha |
| 2023-08-23 | all platforms: separate cpu_initclocks() from cpu_startclock() | Scott Soule Cheloha |
| 2023-07-27 | Follow the lead of mips64 and make cpu_idle_cycle() just call the | Philip Guenther |
| 2023-07-25 | statclock: move profil(2), GPROF code to profclock(), gmonclock() | Scott Soule Cheloha |
| 2023-07-25 | cpu_idle_{enter,leave} are no-ops on amd64 now, so just #define | Philip Guenther |
| 2023-07-04 | amd64: cpu_info: rearrange members, keep ci_mds_tmp 32-byte aligned | Scott Soule Cheloha |
| 2022-11-29 | Move the generic variable definitions from the ASM at the top of | Philip Guenther |
| 2022-11-08 | amd64: switch to clockintr(9) | Scott Soule Cheloha |
| 2022-11-08 | amd64: add delay_fini() | Scott Soule Cheloha |
| 2022-09-20 | Split out handling of cpu family specific MSRs from cpu_init_msrs() | Robert Nagy |
| 2022-08-30 | Initial support for mmio assist for vmm(4) | Dave Voutila |
| 2022-08-25 | amd64, i386: add delay_init(): basic delay(9) implementation management | Scott Soule Cheloha |
| 2022-08-22 | remove extern for cpu var removed in 2015 | Jonathan Gray |
| 2022-08-12 | amd64: simplify TSC synchronization testing | Scott Soule Cheloha |
| 2022-08-07 | Start to add annotations to the cpu_info members, doing I/a/o for | Philip Guenther |
| 2022-07-12 | remove cache parts of struct cpu_info only vmm used | Jonathan Gray |
| 2022-06-28 | rewrite amd64 printing of cache details | Jonathan Gray |
| 2022-06-26 | Delete trailing whitespace. No code change. | Mike Larkin |
| 2022-04-26 | On CPUs that have MPERF/APERF support use that information to install a | Claudio Jeker |
| 2021-08-31 | vmm(4): add ipi for vmclear, unlock kernel | Dave Voutila |
| 2021-07-06 | Introduce CPU_IS_RUNNING() and us it in scheduler-related code to prevent | Mark Kettenis |
| 2021-06-18 | The pmap needs to know which CPUs to send IPIs when TLB entries | Philip Guenther |
| 2021-06-02 | kernel: introduce per-CPU panic(9) message buffers | cheloha |
| 2020-06-03 | let the random subsystem read the tsc for event "timestamps". | David Gwynne |
| 2020-05-31 | introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c. | David Gwynne |
| 2020-04-28 | Use the same inittodr()/resettodr() implementation as on arm64/armv7/sparc64 | Mark Kettenis |
| 2020-04-15 | Remove unused protoype. | Mark Kettenis |
| 2019-12-20 | Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL. | Jonathan Gray |
| 2019-08-09 | Add TSC synchronization for multiprocessor machines. | Paul Irofti |
| 2019-05-17 | Mitigate Intel's Microarchitectural Data Sampling vulnerability. | Philip Guenther |
| 2019-05-12 | Delete cpu_idle_{enter,leave}_fcn() as unused. Add RETGUARD checks to | Philip Guenther |
| 2019-01-19 | Add a pwraction sysctl that controls what the power button does on acpi. | Ted Unangst |
| 2018-12-05 | Include srp.h where struct cpu_info uses srp to avoid erroring out when | Jonathan Gray |
| 2018-08-21 | Perform mitigations for Intel L1TF screwup. There are three options: | Theo de Raadt |
| 2018-07-11 | Declare cpu_meltdown in <machine/cpu.h> | Philip Guenther |
| 2018-07-06 | Split trap() into kerntrap() and usertrap(), with all the signal generation | Philip Guenther |
