src - OpenBSD base system

Age	Commit message (Expand)	Author
2017-08-12	add some extra comments that got left out of the previous IA32_MISC_ENABLE	Mike Larkin
2017-08-09	Add IA32_MISC_ENABLE MSR and bitfield values, to be used shortly by	Mike Larkin
2017-08-09	reorder some MSRs in the MSR list that were out of order. No functional	Mike Larkin
2017-06-20	remove some magic numbers in the flush-by-asid code and check if the CPU	Mike Larkin
2017-06-20	SVM: better cleanbits handling. Fixes an issue on Bulldozer CPUs causing	Mike Larkin
2017-05-30	FPU context save/restore for SVM in vmm(4), matches a previous diff	Mike Larkin
2017-03-28	add RDTSCP flags to identcpu.c	Mike Larkin
2017-01-24	SVM: missing msr defintion for host save area physaddr	Mike Larkin
2017-01-19	SVM: VMCB intercept definitions	Mike Larkin
2017-01-13	Disable and lock Silicon Debug feature on modern Intel CPUs	Mike Belopuhov
2016-10-06	add a debug function that was useful in finding the previous	Mike Larkin
2016-09-30	Compute CR3 target count. Needed for upcoming debugging diff.	Mike Larkin
2016-09-27	read and cache VMFUNC capability during boot. for use in an upcoming diff	Mike Larkin
2016-09-10	Enable VMM debug and add a few new controls	Mike Larkin
2016-09-03	fix typo "mode" -> "model" when referring to "Model specific registers"	Mike Larkin
2016-09-03	add SDBG to cpuid bits and identcpu	Mike Larkin
2016-07-16	Fix an incorrect shift value when calculating the mask for the VMCS MSR	Mike Larkin
2016-06-22	Identify UMIP feature, if available.	Mike Larkin
2016-04-26	Add decode functions for some of the MSRs that are commonly used. Only	Mike Larkin
2016-04-26	Convert some magic numbers into #defines - this is needed for some MTRR	Mike Larkin
2016-04-25	cr0, cr3, cr4 diagnostics / debug functions (used when VMs crash)	Mike Larkin
2016-01-10	Page fault handling tweaks for vmm:	Stefan Kempf
2015-12-07	Add cpuid bits documented in the August 2015 revision of	Jonathan Gray
2015-11-13	vmm(4) kernel code	Mike Larkin
2015-06-07	Add CR4_FSGSBASE	Philip Guenther
2015-05-28	Save the cpuid(6) eax bits in the cpu_info and report the SENSOR and ARAT	Philip Guenther
2015-04-19	Add support for x2apic mode	Stefan Fritsch
2015-03-25	Mark CPUID_LEAF inline asm as volatile to prevent the compiler from reordering	Mark Kettenis
2015-03-21	Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit	Mark Kettenis
2015-01-19	Make use of an msr available on recent Intel processors to obtain the	Jonathan Gray
2014-12-22	Clean up some weird spacing. No functional change.	Mike Larkin
2014-12-16	Define and print HV cpuid flag.	Stefan Fritsch
2014-11-30	Mask out EFER_LMA when restoring saved EFER on zzz/ZZZ resume as it's a	Mike Larkin
2014-07-03	Add identcpu detection for 1-GByte pages	Matthew Dempsky
2013-08-24	Cleanup amd64 and i386 MTRR code -	Mike Larkin
2013-06-02	fix tpyo	Philip Guenther
2013-05-06	the use of modern intel performance counter msrs to measure the number of	David Gwynne
2012-11-10	Recent x86 CPUs come with a constant time stamp counter. If this is	Marcus Glocker
2012-10-09	Sync "Structured Extended Feature Flags" cpuid bits with	Jonathan Gray
2012-08-24	Synchronize CR4 and CPUID portions of <machine/specialreg.h> for i386 and amd64	Philip Guenthe
2012-03-27	Implement the AMD suggested workaround for family 10h & 12h errata 721	Jonathan Gray
2011-12-26	Add the missing ECX cpu flags from CPUID at 0x80000001.	Christiano F. Haesbaert
2010-04-29	Add the CR_PAT MSR to the list of defined msrs.	Owain Ainsworth
2010-03-21	Add some additional Intel CPUID values for recent and upcoming processors.	Jonathan Gray
2009-10-07	add support for the temperature sensor of VIA Nano and C7-M CPUs.	Kevin Lo
2009-09-20	Back out via nano temperature sensor changes.	Jonathan Gray
2009-09-20	add support for VIA Nano cpu core temperature sensor	Kevin Lo
2009-05-31	Add VIA crypto features support to amd64. ok deraadt@	Matthieu Herrb
2008-08-13	Disable the fantastics mis-feature on some newer Turion CPUs called C1E.	Artur Grabowski
2008-06-13	Detect if Intel's Safer Mode Extensions (SMX) are present,	Jonathan Gray