Age | Commit message (Collapse) | Author |
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close causes a suspend. resumes are not tied to this; they happen
unconditionally. this is a temporary knob for the 4.8 release; afterwards
it will move to a more convenient place
much moaning discussing where to put the knob with kettenis
tested by various including phessler
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ok deraadt
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all jumbled up in the same functions. the rtc (mc chip) and clock (i8243)
startup was also mixed up. they the soft state and hardware state can
be started in the right order, and it is easy to restart just the
neccessary parts upon resume. tested in numerous cases:
(apic, pic) * (GENERIC.MP, GENERIC) * (mp, non-mp) * (i386, amd64)
ok kettenis
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context of some random process that happened to be switched onto the FPU
after the decision was made to send the IPI.
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ok kettenis, deraadt
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the FPU in the kernel.
From Mike Belopuhov; Little bits by myself.
Comments/OK kettenis@
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doing thread-local storage and fix a typo in one that was already defined.
ok kettenis@ drahn@
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boot messages can be too big to fit.
sure deraadt@
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and thus should be using spltty()
from Matthew Dempsky
ok oga guenther
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more to come later)
Specfically, there is no reason to reserve a special virtual address just so we
can do boot dump, we have a direct map of every page anyway.
since pmap_map is deprecated and MD only anyway, this means we can remove that
interface too. If anything this should increase reliability since pmap_enter
won't fail under memory pressure during dump (unlikely but possible). It is also
simpler and smaller ;)
Tested by myself and ckuethe, no regressions.
ok miod@
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PAT allows setting per-mapping cachability bits. Our main interest in it
for write combining mappings so we do not have to rely so heaviliy on
mtrrs (which are stupidly set up on more and more machines). MD flags to
pmap allow setting these bits (which bus_space now uses for PREFETCHABLE
maps), if a vm page has a bit set, then we will use WC for all mappings
of a page (used for userland mappings). We also check for known errata
and fall back to UC- mappings in that case.
comments from kettenis@, tedu@ and william@. kettenis@, tedu@ ok.
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"Absolutely, don't forget i386" kettenis@.
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ok miod@
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HARD uncached on anything since the P3), use just PCD which is UC-
(uncached but mtrrs can override it to write combining).
Now kernel mappings of WC-mtrred memory actually get write combining
memory.
the speed up is very very nice.
ok kettenis@, deraadt@, beck@ (who likes his scrollbars non-wibbly)
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into the sg_dma code instead of main bus_dma. Add identical code to i386
since this will be used in the next commit.
ok kettenis@ back in december.
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first name is used, and remove any #define foo_region foo compatibility
defines.
Also, on sparc64, do not provide a `raw' version of bus_space_copy.
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With some additions from sthen@
ok kettenis@ sthen@
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spotted by ckuethe and must be in immediately before my build gets there..
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code):
pmap_flush_cache(vaddr_t, vsize_t) and pmap_flush_page(paddr_t) to flush
the cache for virtual addresses and physical pages respectively using
the clflush instruction. These apis will shortly be used by the agp
bus_dma functions to avoid doing a wbinvd on each dmamap_sync.
ok kettenis@, some comments from miod@
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instruction.
ok kettenis@ as part of a larger diff.
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the cpu.
ok kettenis@ as part of a larger diff.
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rather than defining it separately for each architecture.
Also set it to 4, to accommodate for future UTF-8 support (rfc3629).
Diff by stsp, committing to catch the libc major bump
ok kettenis@, guenther@
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ok jsing@, miod@
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some improvements suggested by jsg@
"commit" deraadt@
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i386 and amd64 to make avoid legacy ISA I/O registers. Fixes issues with
ThinkPad T-series Dock II units as reported by sobrado@
ok miod@
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They break ramdisks as noticed by jasper, and have not been
adequately discussed.
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ok deraadt@
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ldt_{alloc,free} to shave a few. ok jasper@, oga@
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Tested by myself, sthen, oga, kettenis, and jasper.
Input from sthen and jasper.
ok kettenis
(Manpage follows shortly.)
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right now, we do a pmap_kenter_pa(), we then get the pte (behind pmap's
back) and check for the cache inhibit bit (if needed). If it isn't what
we want (this is the normal case) then we change it ourselves, and do a
manual tlb shootdown (i386 was a bit more stupid about it than amd64,
too).
Instead, make it so that like on some other archs (sparc64 comes to
mind) you can pass in flags in the low bits of the physical address,
pmap then does everything correctly for you.
Discovered this when I had some code doing a lot of bus_space_maps(), it
was incredibly slow, and profilling was dominated by
pmap_tlb_shootwait();
discussed with kettenis@, miod@, toby@ and art@.
ok art@
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provide and use BUS_SPACE_BARRIER_xxx.
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bus_space_alloc() as a bitmask of flags, and not a boolean controlling
cacheability; and make sure the three MI BUS_SPACE_MAP_xxx values documented
in the manual page are defined on all platforms as well.
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of the bus_space_tag_t it contains; an upcoming implementation will need
to know the rbus_tag_t for which it works at this point.
All callers updated accordingly; no functional change intended.
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logic to be chipset dependent; no functional change yet.
ok kettenis@
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allocator).
"i can't see any obvious problems" oga
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My
bios0: ASUSTeK Computer INC. P5K-E
cpu0: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.74 MHz
cpu1: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
cpu2: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
cpu3: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
can't boot with this in. It always hangs somewhere in fsck'ing if
any, or between netstart and local daemons if no fsck'ing. Also
fubars theo's real amd machine.
Much more testing needed for this.
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eventually be needed by bouncebuffers, and I need it for some of my evil
graphics shitz.
ok kettenis@ with some tweaks
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in the IPI handler so that it works when it interrupts userspace,
waiting for the droppmap IPI to complete when destroying it, and
(most importantly) don't call pmap_tlb_droppmap() from cpu_exit().
Tested by myself and ckuethe, as our machines choked on the original.
ok @art
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Tested on multiple i386 and it works, amd64 works also with a few
exceptions that will get fixed.
The initial effort of importing was done by oga@, thanks!
Lots of testing and debugging by mlarkin@ and me.
Okay deraadt@, oga@, mlarkin@.
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but even with proposed fixes, the reaper panics are back.
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ok gwk@, toby@, marco@
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to free ranges.
Classify memory based on region with associated use-counter (which is used
to construct a priority list of where to allocate memory).
Based on code from tedu@, help from many.
Ok art@
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curcpu when we were freeing a pmap. Tested and working for a few weeks
now, but I was a bit too busy to commit it earlier.
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