| Age | Commit message (Collapse) | Author |
|---|
|
|
|
A few functions and symbols were included in non-VMM builds. This
tucks more of them behind the "#ifdef NVMM > 0" check and cleans
up RAMDISK kernels.
ok mpi@, feedback from chris@
|
|
Some packets were dropped by vio_encap() when using bounce buffers.
These mbufs are too fragmented for the pre allocated bounce buffer
pages. By returing EFBIG the network driver will call m_defrag()
and try again. This fixes the problem.
OK sf@ hshoexer@
|
|
Bring the pieces for vmm(4) to support guests with SEV memory
encryption on AMD CPUs. The corresponding vmd(8) changes will
follow.
Emulate cpuid 0x8000001f so the guest can discover SEV features.
Allow vmd(8) to enable SEV on VM creation. Inform vmd(8) about the
c-bit position and ASID assigned to each VCPU.
Note that vmd(8) has to be rebuilt with the new header files.
from hshoexer@; input dv@; OK mlarkin@
|
|
If the physical pages are contiguous, _bus_dmamap_load_buffer()
tries to merge the segments. In case of mbuf chains, it can happen
that the physical bounce buffers are contiguous, but the virtual
addresses of mbuf m_data are not. Then during transmit _bus_dmamap_sync()
tries to copy segments where it cannot access the virtual source
address which is mapped in a different mbuf. So if bounce buffers
are used, physical and virtual buffer must be contigous, to merge
a segment.
While there, split check and decrement of variable i in a for loop
to make the code readable.
with and OK hshoexer@
|
|
|
|
|
|
With bounce buffers, we must pass a larger size to free()
ok bluhm@ hshoexer@
|
|
There was an off-by-one bug when comparing the used pages for bounce
buffers with the available pages. As a result _bus_dmamap_load_buffer()
returned ENOMEM although there was one buffer left.
Also the _dm_nused field was updated and never reset in case of an
error. Use a local variable to count the used pages and update
global map->_dm_nused only if _bus_dmamap_load_buffer() was successful.
This fixes hanging network transmits if bounce buffers are enforced
for vio(4).
OK sf@ hshoexer@
|
|
To debug bounce buffers easily on non-SEV hardware, introduce a
define FORCE_BOUNCE_BUFFER that activates them. Default is off,
no functional change.
OK miod@
|
|
When running as SEV guest, as indicated by variable cpu_sev_guestmode,
allocate additional pages for each segment on dma map creation.
These pages are mapped with the PMAP_NOCRYPT attribute, i.e. the
crypt bit is not set in the PTE. Thus, these pages are shared with
the hypervisor.
When the map is loaded with actual pages, the address in the
descriptor is replaced by the corresponding bounce buffer. Using
bus_dmamap_sync(), data is copied from the encrypted pages used by
guest drivers to the unencrypted bounce buffers shared with the
hypervisor, and vice versa.
If the kernel is not running in SEV guest mode, which means as
normal host or non-SEV guest, no bounce buffers are used.
from hshoexer@; based on ancient code of mickey@; OK kettenis@
|
|
This driver is not working yet, it's a copy of qwx(4) which bit-by-bit will be
adjusted to work on the newer generation of chips. Even though this is only a
minor bump over the previous generation, the changes are large enough that
bringup, debugging and long-term maintenance would suffer trying to squash them
into a single driver. This can be reconsidered once we have reached a stable
state.
|
|
so mpi(4) gets removed from the floppy.
|
|
Corrects an off-by-one error that results in EPT pte's not being
removed properly.
ok mlarkin@
|
|
ok mlarkin@, deraadt@
|
|
various Intel SoCs. The driver takes care of calling the AML methods
needed to enter low power idle states during suspend-to-idle (S0i).
The driver also implements some debug code that prints the residency of
various power states in dmesg. Based on some earlier code by jcs@
ok jcs@
|
|
like the others.
Nudged, test, and ok deraadt@
|
|
us from trying to put devices into the D3 power state which some hardware
doesn't appreciate.
ok ratchov@, deraadt@
|
|
According to the AMD64 Architecture Programmer's Manual volume 2
the intercept SVM_INTERCEPT_INVLPGA needs to be set in vmcb.intercept1
(vector 3, offest 00Ch) instead of intercept2 (vector 4, offset
010h). SVM_INTERCEPT_INVLPGA is bit 26, so before vcpu_reset_regs_svm()
was actually setting an intercept for CR10, which does not exist.
from hshoexer@; OK mlarkin@
|
|
vmm(4) only supports using nested paging on Intel or AMD and no
longer supports HLAT or shadow paging.
ok mlarkin@
|
|
Actually determine the C-bit position if we are running as a guest
with SEV enabled. Configure pg_crypt, pg_frame and pg_lgframe
accordingly, using the physical address bit reduction provided by
cpuid.
from hshoexer@; OK mlarkin@
|
|
the stack utilization ends up near the the deep end of the stack where,
retcleans are useful. tested for a while in snaps
ok bluhm
|
|
Designed to let userland peek at AT_HWCAP and AT_HWCAP2 using an already
existing interface coming from FreeBSD. Headers bits were snatched from
there. Input & ok kettenis@
libc bump and sets sync will follow soon
|
|
Since vmm handles nested page faults in the vcpu run loop, trying
to avoid trips back to userland, it's possible for the thread to
move host cpus. vmm(4) already updates some local cpu state when
this happens, but also needs to update the host cr3 in the vmcs to
allow vmx to restore the proper cr3 value on the next vm exit.
Additionally, we should be flushing the ept cache on the new cpu.
If the single context flush is available, use that instead of the
global flush.
ok mlarkin@
|
|
|
|
Similar to the NX-bit apply the C-bit to the PTEs built by locore0.
Right now, pg_crypt is initialized to 0, so nothing will change.
from hshoexer@; OK mlarkin@
|
|
Makes as much of the core of vmd mi, pushing x86-isms into separate
compilation units. Adds build logic for arm64, but no emulation
yet. (You can build vmd, but it won't have a vmm device to connect
to.)
Some more cleanup probably needed around interrupt controller
abstraction, but that can come as we implement more than the i8259.
ok mlarkin@
|
|
The C-bit in a page table entry is used by a SEV guest to specify,
which pages are to be encrypted and which not. The latter is needed
to share pages with the hypervisor for virtio(4).
The actual position of the C-bit within a PTE is CPU implementation
dependend and needs to be determined dynamically at system boot.
The position of the C-bit also determines the actual size of page
frame mask. This will be provided by a separate change.
To be able to use the same kernel as both host and guest, the C-bit
is provided as variable similar to the NX-bit. Same holds for the
page frame masks.
Right now, pg_crypt is set to 0, pg_frame an pg_lgframe to PG_FRAME
and PG_LGFRAME respectively. Thus the kernel works as a host system
same as before.
Also introduce a PMAP_NOCRYPT flag. A guest will use this with
busdma to establish unencrypted mappings that can be shared with
the hypervisor.
from hshoexer@; OK mlarkin@
|
|
ok mlarkin
|
|
To prepare for mi/md splitting vmd, need to fixup the dev/vmm/vmm.h
mi header. Move the vm_run_params struct and clean up the includes
in vmd.
"sure", mlarkin@
|
|
when merging changes from FreeBSD in i386 rev 1.10
db_Esca5 was added but not used
ok mlarkin@
|
|
ok kettenis@, mlarkin@, miod@, claudio@
|
|
|
|
|
|
last use (in inteldrm) was removed in March
|
|
was replaced a while ago.
ok tb
|
|
ok mglocker@
|
|
this may print an (MSI) interrupt that sneaks in just before we actually
enter the idle loop on the primary CPU. While such an interrupt shouldn't
happen, they won't prevent the machine from reaching a low power idle state.
So at this point these non-wakeup interrupts only need to be investigated
when the primary CPU gets woken up repeatedly.
ok mglocker@, deraadt@
|
|
Enable identifycpu() to discover and show AMD SEV related information
provided by cpuid.
The "crypt bit" for page table entries is stored in amd64_pos_cbit,
although it is not used yet.
Registers ecx and edx provide the number of guest and minimum ASID
for SEV-only guests. At least the latter value can be configured
in the BIOS, so it is useful to have this information in dmesg.
Therefore define emtpy bit masks for printf("%b") to get the raw
numbers.
from hshoexer@; OK mlarkin@
|
|
ok deraadt@
|
|
removed in subr_hibernate.c rev 1.35
|
|
The Unchartevice 6640MA notebook comes with such a CentaurHauls CPU,
installs via RAMDISK_CD (with AHCI fix), but GENERIC would hang after
cpu0: 4MB 64b/line 16-way L2 cache
Pretty sure Intel TPM sensor code should run on Intel CPUs, anyway.
Idea from brynet
OK deraadt brynet
|
|
have disabled interrupts at the CPU level again. So instead of
cpu_suspended use a new intr_suspended variable that is set and cleared in
intr_enable_wakeup() and intr_disable_wakeup().
ok mglocker@, mlarkin@
|
|
differed on the second or later cache, the generated dmesg didn't
report the earlier, identical cache levels correctly.
report, testing, and ok jsg@
|
|
Several commands for basic platform initialization and launch of
SEV/SEV-ES enabled guests are implemented. These can be used by
e.g. vmd(8) later.
from hshoexer@; OK mlarkin@
|
|
|
|
|
|
Having differences between architectures is asking for problems. And
adding a barrier here just makes sense in most cases. This is also what
cpu_relax() provides in Linux land.
ok kettenis@ claudio@
|
|
|
|
|
