Age | Commit message (Collapse) | Author |
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First brought up by naddy@ in the usertc thread, OK kettenis@.
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the cpu is specified by a struct cpu_info *, which should generally
come from an intrmap.
this is adapted from a diff that patrick@ sent round a few years
ago for a pci_intr_map_msix_cpuid, where you asked for an msi vector
on a specific cpu, and then called pci_intr_establish with the
handle you get. kettenis pointed out that it's hard on some archs
to carry cpu on a pci interrupt handle, so i tweaked it to turn it
into a pci_intr_establish_cpu instead.
jmatthew@ and i (but mostly jmatthew@ to be honest) have been
experimenting with this api on multiple archs and it is working out
well. i'm putting this diff in now on amd64 so people can kick the
tyres a bit.
tested with hacked up vmx(4), ix(4), and mcx(4)
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intr_barrier passed NULL to sched_barrier before this, which ends
up being the primary cpu. that's been mostly right until this point,
but is set to change.
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Do the same for rdseed.
ok deraadt@
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and alternatively XOR'd against TSC. now always run both sequences, and
also support rdseed as a third procedure.
ok kettenis naddy
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adds kernel support for
amdgpu: vega20, raven2, renoir, navi10, navi14
inteldrm: icelake, tigerlake
Thanks to the OpenBSD Foundation for sponsoring this work, kettenis@ for
helping, patrick@ for helping adapt rockchip drm and many developers for
testing.
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ok kettenis
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rnd.c uses nanotime to get access to some bits that change quickly
between events that it can mix into the entropy pool. it doesn't
use nanotime to get a monotonically increasing set or ordered and
accurate timestamps, it just wants something with bits that change.
there's been discussions for years about letting rnd use a clock
that's super fast to read, but not necessarily accurate, but it
wasn't until recently that i figured out it wasn't interested in
time at all, so things like keeping a fast clock coherent between
cpu cores or correct according to ntp is unecessary. this means we
can just let rnd read the cycle counters on cpus and things will
be fine. cpus with cycle counters that vary in their speed and
arent kept consistent between cores may even be desirable in this
context.
so this is the first step in converting rnd.c to reading cycle
counter. it copies the nanotime backend to each arch, and they can
replace it with something MD as a second step later on.
djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits.
thanks to visa for his eyes.
ok deraadt@ visa@
deraadt@ says he will help handle any MD fallout that occurs.
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conversion steps). it only contains kernel prototypes for 4 interfaces,
all of which legitimately belong in sys/systm.h, which are already included
by all enqueue_randomness() users.
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EFIFB_HEIGHT and EFIFB_WIDTH instead of efifb_std_descr.n{rows,cols}.
Because the efifb resolution doesn't change, this ensures 'ri_emuwidth'
and 'ri_emuheight' will always get the same value when we remap and
later when we attach, so the text area is always displayed at the same
position.
This fixes display glitches happening on smaller screens or with larger
fonts, which caused the content previously displayed in the area that
was becoming margins when remapping to remain there.
OK jsg@
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to select the VGA or the EFI framebuffer properly. Previous
initializes VGA unconditionally, it caused serious problems like the
video distortion and so on. As a downside of this commit, some early
panic or debug messages will not be displayed.
test Andrew Daugherity, jsg
ok jsg kettenis
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This is the same change made in rev 1.21 to match the drm drivers.
It was reverted as Lucas Raab reported problems with inteldrm taking
over the fb with a 4k display. Lucas confirmed that this is no longer
an issue.
Prompted by a similar patch from John Carmack to raise the limits.
ok kettenis@
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discussed with deraadt@
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from John Carmack
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miod explained it was initially a long as it was thought drivers may
need to allocate storage but in practice they don't need more than
32 bits for an attribute.
suggested and reviewed by miod@
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Suggested by John Carmack. miod agrees a rename would make sense and
explained it was initially thought drivers may need to allocate storage
but in practice they don't need more than 32 bits for an attribute.
ok mpi@
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ok kettenis@, visa@
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This shrinks the ramdisks a tiny bit.
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ok deraadt@, mpi@, visa@
ok cheloha@ as well (would have preferred in new file for this code)
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sad
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information on ACPI 5.0 and later.
ok krw@, patrick@
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ok sthen@, patrick@
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While here use the kqfilter equivalent to `seltrue' to ensure both
interfaces are coherent.
ok visa@
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the file system such that implementations can use it to guess the right
century.
ok mpi@
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passed in when setting the RTC time instead of the global time_second.
ok mpi@
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and move it to the end of machdep.c. Rework the actual implementation
for te MC14818 compatible RTC into something that can be used as a todr_handle.
ok mpi@
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low_mask as already used on high_mask to convince compiler to use 64
bits.
CID 1480717
CID 1480778
ok pd@
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random stack garbage.
CID 1492655
ok pd@
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Upgrade stacktrace_save() to stacktrace_save_at() on architectures where
the latter is missing. Define stacktrace_save() as an inline function
in header <sys/stacktrace.h> to reduce duplication of code.
OK mpi@
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cache-coherent or not. To implement this, acpi(4) gets two bus_dma tags
and passes the appropriate one when attaching devices based on _CCA.
On i386/amd64, where for all practical purpose DMA is always cache-coherent,
the two tags are the same. But on arm64 they are distinct.
ok patrick@
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This exposes VMM_IOC_MPROTECT_EPT which can be used by vmd to lock in physical
pages. Currently, vmd just terminates the vm in case it gets a protection fault
in the future.
This feature is used by solo5 which uses vmm(4) as a backend hypervisor.
ok mpi@
Patch from Adam Steen <adam@adamsteen.com.au>
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* Switch to using vcpu->vc_vmx_cr0_fixed[1|0] to check must be 0|1 bits,
rather than the cpu capabilities.
* Add the checks on the new values as per the SDM 2.5 CONTROL REGISTERS.
2.1 Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros.
Writing a nonzero value to any of the upper 32 bits results in a
general-protection exception, #GP(0).
2.2 setting the PG flag when the PE flag is clear causes a general-protection
exception (#GP).
11.5.1 Cache Control Registers and Bits, Table 11-5. Cache Operating Modes
2.3 CD: 0, NW: 1, Invalid setting. Generates a general-protection exception
(#GP) with an error code of 0.
*. Don't alway assume, if the guest is not disabling paging, they are
enabling it, check the guest is actually enabling paging. also only read
cr4 when we actually need it, not right at the start.
ok mpi@
Patch from Adam Steen <adam@adamsteen.com.au>
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arm64 and i386, the chain of call frames is continuous from kernel
to userspace. The unwinder has to stop at the latest when it reaches
the start of the kernel stack.
OK mpi@
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Reported-by: syzbot+48e38ebd31c030b5841c@syzkaller.appspotmail.com
Found by Greg Steuck <greg (at) nest (dot) cx>
Discussed with deraadt@
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This variant of stacktrace_save() takes an aditionnal argument to skip
an arbitrary number of frame. This allows to skip recording frames used
to execute the profiling code and produces outputs easier to understand.
Inputs from and ok visa@
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find a media device path node. Fixes booting OpenBSD on some older U-Boot
versions that are in wide circulation such as 2017.09 and 2017.11.
ok patrick@
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the previous code relied on newer cpus having properly filled in
values for som e new cpuid fields, but these are definitely not
filled in properly if you're running in a certain type of virtual
machine, which meant a lot of cores were misidentified as threads.
this new code follows what most other operating systems seem to do.
they read the "initial local apic id", which is globally unique in
a system, and cut it up into the package, core, and smt values. the
line between a package and the cores/threads inside a package is
determined by the "ApicIdSize". once the package is masked off, the
remaining core/thread ids is divided up by the ThreadsPerCore value.
the latter defaults to 1, unless we're on a newer (eg, zen) chip
that provides a higher value.
this seems to work well across a variety of machines of different
vintages.
thanks to mark patruck, hrvoje popovski, and sthen@ for a lot of testing.
ok sthen@
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when not running on a supported mode. This matches code elsewhere
in the file and prevents using the uninitialized vrs later in
the function.
Coverity CID 148078
as discussed with mike larkin
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CID 1453255
ok deraadt@
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Fix build with gcc.
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