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makes Enhanced SpeedStep work on new machines, but requires
acpimadt0 to be enabled.
ok by jsg@ and claudio@
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bus_space_alloc() as a bitmask of flags, and not a boolean controlling
cacheability; and make sure the three MI BUS_SPACE_MAP_xxx values documented
in the manual page are defined on all platforms as well.
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of the bus_space_tag_t it contains; an upcoming implementation will need
to know the rbus_tag_t for which it works at this point.
All callers updated accordingly; no functional change intended.
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logic to be chipset dependent; no functional change yet.
ok kettenis@
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More architectures hopefully to follow.
ok kettenis@
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allocator).
"i can't see any obvious problems" oga
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separately).
a change at or just before the hackathon has either exposed or added a
very very nasty memory corruption bug that is giving us hell right now.
So in the interest of kernel stability these diffs are being backed out
until such a time as that corruption bug has been found and squashed,
then the ones that are proven good may slowly return.
a quick hitlist of the main commits this backs out:
mine:
uvm_objwire
the lock change in uvm_swap.c
using trees for uvm objects instead of the hash
removing the pgo_releasepg callback.
art@'s:
putting pmap_page_protect(VM_PROT_NONE) in uvm_pagedeactivate() since
all callers called that just prior anyway.
ok beck@, ariane@.
prompted by deraadt@.
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three
commits:
1) The sysctl allowing bufcachepercent to be changed at boot time.
2) The change moving the buffer cache hash chains to a red-black tree
3) The dynamic buffer cache (Which depended on the earlier too).
ok on the backout from marco and todd
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ok deraadt@ kettenis@
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> extend uvm_page_physload to have the ability to add "device" pages to the
> system.
since it was overlayed over a system that we warned would go "in to be
tested, but may be pulled out". oga, you just made me spend 20 minutes
of time I should not have had to spend doing this.
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My
bios0: ASUSTeK Computer INC. P5K-E
cpu0: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.74 MHz
cpu1: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
cpu2: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
cpu3: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz, 2405.46 MHz
can't boot with this in. It always hangs somewhere in fsck'ing if
any, or between netstart and local daemons if no fsck'ing. Also
fubars theo's real amd machine.
Much more testing needed for this.
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this might need to be revisted later if its clear that there are machines
which only come up with a single state but more may appear after a PPC
change but for now we will just not initilize on systems with a single
state a boot. Solves a divide by zero panic when using the PDC diff on
broken hardware.
ok marco@, krw@
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as well, reminded by miod@
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eventually be needed by bouncebuffers, and I need it for some of my evil
graphics shitz.
ok kettenis@ with some tweaks
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system.
This is needed in the case where you need managed pages so you can
handle faulting and pmap_page_protect() on said pages when you manage
memory in such regions (i'm looking at you, graphics cards).
these pages are flagged PG_DEV, and shall never be on the freelists,
assert this. behaviour remains unchanged in the non-device case,
specifically for all archs currently in the tree we panic if called
after bootstrap.
ok art@, kettenis@, ariane@, beck@.
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in the IPI handler so that it works when it interrupts userspace,
waiting for the droppmap IPI to complete when destroying it, and
(most importantly) don't call pmap_tlb_droppmap() from cpu_exit().
Tested by myself and ckuethe, as our machines choked on the original.
ok @art
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still support all different methods of getting states without e.g.
(highest/lowest state), and on i386 use the tables. The only change
should be the deletion of the mV from the printf at boot.
ok jsg@
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IPIs are handled without blocking interrupts. This solves the random lockups
people have been seeing with apmd -C, thanks to marco@ for showing me how
to reliably recreate this hang, and claudio@ for telling me it was also
affecting his Athlon64 machine so I stopped chasing bugs in est.
ok oga@, weingart@
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immediately when biglock wasn't held. But there is nothing inherently
wrong with doing copyin/copyout faults without holding biglock, so
just remove the check because it prevent us from doing copyin in
syscall before we grab the biglock.
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aperture, which will take your memory, bind it to agp, and return you the
aperture address. It's essentially the same as iommu on amd64 in the way it
works.
This will be used by the upcoming (works but is slow and will not be
enabled at first) drm memory management code for intel igp chipsets.
Right now the sync function for intagp is really slow (doing a wbinvd()
on every sync), this is in the process of getting fixed, but the size of
the diffs in my trees was getting silly.
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information in files.conf like it should be.
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Tested on multiple i386 and it works, amd64 works also with a few
exceptions that will get fixed.
The initial effort of importing was done by oga@, thanks!
Lots of testing and debugging by mlarkin@ and me.
Okay deraadt@, oga@, mlarkin@.
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that wasn't needed.
ok pirofti@
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but even with proposed fixes, the reaper panics are back.
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ok art
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size on a running system.
ok art@, oga@
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arches. ok todd@ beck@
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Okay jordan@ and marco@.
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except thinkpads, they will use the acpithinkpad driver. The driver is
also hooked into wsconsole. So brightness can be adjusted via:
$ wsconsctl display.brightness=<percentage>
This is very helpfull on some laptops that have a nasty bios and get two
steps instead of one when pressing the brightness button.
Tested on various dell, fujitsu, acer, samsung and other laptops.
Okay marco@, miod@. Suggestions from kettenis@.
Lots of reviews and help from miod@, thanks!
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ok marco@
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global lock, switch the uvm object pages to being kept in a per-object
RB_TREE. Right now this is approximately the same speed, but cleaner.
When biglock usage is reduced this will improve concurrency due to lock
contention..
ok beck@ art@. Thanks to jasper for the speed testing.
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via an interrupt handler in acpi_sleep_machdep.
okay mlarkin@ marco@
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ok gwk@, toby@, marco@
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against the vendor string, then cpu family, then if the cpu claims to
have it.
requested by toby@
Also match against Via's cpu string to enable MTRR on matthieu@'s VIA Nano
compile tested on i386 by wcmaier@
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this version by Art.
additional ok by marco@
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to free ranges.
Classify memory based on region with associated use-counter (which is used
to construct a priority list of where to allocate memory).
Based on code from tedu@, help from many.
Ok art@
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of the vendor check for intel and use the EST cpu feature flag to determine
if we should call the est init routine. Tested on mattieu@'s via nano laptop.
ok deraadt@, jsg@
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bigmem kernels work again.
ok oga@, ariane@.
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#ifdef CRYPTO. noticed by marco@
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ok marco@
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ok toby
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BIOSen it's a complete lie. Instead use the information from the memory
map like we do on i386.
ok weingart@, oga@
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curcpu when we were freeing a pmap. Tested and working for a few weeks
now, but I was a bit too busy to commit it earlier.
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