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see the ancient mode 2 on machines capable of running OpenBSD/amd64.
ok deraadt@, toby@, oga@
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mapping to the gart than the old code, and shouldn't conflict with
bouncebuffers when they're added.
This is essentially the sparc64 iommu code that's been modularised a bit
so I can eventually use the same code for agp-based dma for memory
managed drm drivers.
Now, this would overflow ramdiskA, so iommu and sg_dma are now #ifndef
SMALL_KERNEL.
ok kettenis@, marco@. SMALL_KERNEL discussions with deraadt.
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ok oga@
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Replaces pchb with amas for the AMD64 address map.
amas0 at pci0 dev 24 function 1 "AMD AMD64 0Fh Address Map" rev 0x00
Currently disabled (causing pchb to attach instead).
ok art@
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Saves every damned driver calling bzero(), and continues the M_ZERO,
PR_ZERO symmetry.
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``please commit'' deraadt
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always increment uvmexp.softs while inside the lock.
While i'm here, make alpha's dispatch loop look like the rest.
"sure" miod@
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in sysctl hw.ncpufound; ok miod kettenis
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simplelocks + splhigh().
First part of making it possible to make mpsafe softinterrupts.
"oh yes, definitely" miod@
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enable it (I have found the code that does enable it problematic on
quite a few machines, however, that's a different issue). So provide
some code that so if the bios initialised the iommu for us, we'll use
what it gave us. Makes iommu work on a machine of todd's.
while i'm here, we don't need to scan all pci functoins to find the
hypertransport bridge. the gart is always on function 3, so just scan
for all the bridges and not iterate over the functions too.
Thanks to todd for his infinite patience while I gave him diffs that
went ``Boom!''.
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when we setmapsize it's not zero.
*sigh*
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zero so that we return an empty map on error.
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I just spent five hours looking in the wrong place because of this.
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For the possibility of sleeping, the first two flags are UVM_PLA_WAITOK
and UVM_PLA_NOWAIT. It is an error not to show intention, so assert that
one of the two is provided. Switch over every caller in the tree to
using the appropriate flag.
ok art@, ariane@
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ok reyk@
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bus address space. Fixes a problem reported by david@.
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based on the BIOS memory map.
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processors, so the registers to configure addition HyperTransport links
are absent. Don't try attaching addition pci busses on these processors
to avoid probing non-existant registers.
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dmamap rather than all the bytes that are described by the sg list we're
mapping.
tested on iwn by me and beck@
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the bug in it. bugfix will be committed next.
make bus_dmamap_load_raw respect the constraints of the dmamap we're
loading the raw memory into, particularly the segment size constraint.
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ok oga
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SiS chipset that we'll never see on and amd64 machine.
ok oga@
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loading the raw memory into, particularly the segment size constraint.
written in june/july last year, but my studies held me back from handling
it.
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- remove dead (#if 0) code
- move switch_error panics to after cpu_switchto to make branch prediction
happier and the code more readable.
no functional change
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In the future, we need to mark the correct parts of the direct map
uncached, but that's another diff.
art@, kettenis@ ok.
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theoretically the current solution of using the direct (and direct
uncached) maps is better for tlb pressure, two direct maps is dangerous,
especially when we support Page Attribute Tables (soon), since that will
cause illegal cache aliases. When that work is done a clever solution
may be worked out.
"reluctant ok, the uncached direct map is evil" art@
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MD code would free resources that couldn't be freed until we were no
longer running in that processor. However, it's is unused on all
architectures since mikeb@'s tss changes on x86 earlier in the year.
ok miod@
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made testers of art's affinity diff go insane)
ok krw@ miod@
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- Split up run queues so that every cpu has one.
- Make setrunqueue choose the cpu where we want to make this process
runnable (this should be refined and less brutal in the future).
- When choosing the cpu where we want to run, make some kind of educated
guess where it will be best to run (very naive right now).
Other:
- Set operations for sets of cpus.
- load average calculations per cpu.
- sched_is_idle() -> curcpu_is_idle()
tested, debugged and prodded by many@
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levels. This will allow for platforms where soft interrupt levels do not
map to real hardware interrupt levels to have soft ipl values overlapping
hard ipl values without breaking spl asserts.
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11h (Turion) still needs testing, so isn't part of this commit.
ok reyk@, marco@
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Firstly, don't keep identical data for each of the GARTs (we keep them
in sync, but there is one per cpu socket), all that varies is the
pci_tag_t, so just keep an array of those and have the rest of the
information once.
Secondly, don't keep the softc as a global, use the _cookie field of the
dmatag_t, that's what it's there for.
Finally, use dmamap_map to map the page tables, instead of the direct NC
map. This is because later changes to support PAT will be a lot easier
with one direct map (where we change the cacheability if needed), since
otherwise it's just asking for illegal cache aliases.
More changes will be upcoming.
Tested by a few people, with an without bigmem, thanks to those.
weingart@ liked the direction this is going, marco@ and kettenis@ oked it.
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a define needed to get to ``private'' functions that needs to be defined
5 or more times isn't much use and may cause namespace issues anyway.
Other archs will probably follow.
Discussed in portugal. "Hell yes" weingart@, ok kettenis@, no
objections miod@
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on amd64 as well.
ok dlg@
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ok jsg@
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try to be smart for the address range, uvm_pglistalloc() is smart enough
nowadays.
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APM_IOC_{SUSPEND,STANDBY}_REQ: This is to fix an issue with apm suspend
where a call to zzz suspended the machine immediately, not giving anyone
listening for apm events (other than apmd) a chance to deal with the
upcoming change. This hit X hard since the introduction of drm, since it
needs to have time to idle the 3d engine and otherwise get the device
into a recoverable state. Such things are needed until we support
modesetting in the kernel.
Now, instead of forcing a suspend, using ioctl sends out an event similar
to if you had put the lid down, giving all userland applications a
chance to reply.
tested by sthen@ and beck@, especial thanks to sthen for sitting there
while I tried to debug this remotely, I owe him beer.
Prompted by and ok deraadt@
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ok deraadt@
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ok toby and tedu
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hanging machines. backed out correctly this time, as pointed out by tedu.
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code from mlarkin and me
help from art,toby,jordan and several others
ok jordan, go for it deraadt
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"I like it" deraadt "sweet" tedu "love it" marco
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if attempts are made to read it. So read MSR_TEMPERATURE_TARGET only
when ci_model == 0xe.
Found when my Core i7 box blew up. FreeBSD allows a few more chips
but this allows my box to boot.
ok jsg@
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