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2018-01-15Improve defense against branch predictor target injection (Spectre "variant 2")Mark Kettenis
attacks. OpenBSD/armv7 is already in pretty good shape as we have always been flushing the branch predictor cache on context switches. This diff adds additional flushes to page faults in kernel address space. The impact on performance should be minimal as these page faults should only happen when userland (deliberately or accidentally) tries to access kernel addres space which would lead to a fatal signal (SIGSEGV or SIGBUS). Loosely based on changes made by Marc Zyngier in Linux and based on information in Arm Trusted Firmware Security Advisory TFV 6. Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets the ACTRL[0] bit for this diff to be effective. Also note that with this diff Cortex-A57 is still vulnerable. ok jsg@
2017-10-01set MAXSSIZ to the same value as on all other architectures (32MB)Christian Weisgerber
ok deraadt@
2017-09-05Move mutex, condvar, and thread-specific data routes, pthread_once, andPhilip Guenther
pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
2017-08-27Add glass console support for arm64. This uses the "stdout-path" propertyMark Kettenis
of the /chosen node in the device tree to decide whether the framebuffer should be used as the console device. Most, if not all, machines will have that set to use a serial console and there is no easy way yet to change that. ok jsg@
2017-08-20Add Cortex-A55 and Cortex-A75 part numbers.Jonathan Gray
2017-08-12remove apmwarn sysctl which is not usedTed Unangst
2017-07-31Use unsigned long instead of uint32_t, which is the appropriate integerMark Kettenis
type for storing pointers in our universe. Avoids an implicit dependence on <sys/types.h>. ok tom@
2017-07-12remove CPU_LIDSUSPEND/machdep.lidsuspendMartin Natano
"fire away!" tedu
2017-06-29kill RCSID macros; discussed with millertTheo de Raadt
2017-06-23Unbreak profiling assembly functions in userland by defining theMartin Pieuchot
correct prologue if compiled with -DPROF. ok deraadt@
2017-05-18Fix kernel build on armv7 and sh.Visa Hankala
Pointed out by deraadt@
2017-05-12Make atomic.h ready to be included in userland.Martin Pieuchot
- keep setbits/clearbits and virtio barriers inside _KERNEL - prefix def_atomic_xxx macros with underscores
2017-05-08add a BUS_DMA_64BIT flag to bus_dma on all our archs.David Gwynne
this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
2017-04-27Bring over the changes to mainbus(4) and simplebus(4) from arm64.Mark Kettenis
2017-04-24Add support for Cortex-A12. Even though ARM rebranded these as Cortex-A17Mark Kettenis
they have a different ID from "real" Cortex-A17 cores. ok phessler@, patrick@
2017-04-20Hook up mutex(9) to witness(4).Visa Hankala
2017-04-13Provide mips64 with kernel-facing TCB_{GET,SET} macros that store itPhilip Guenther
in struct mdproc. With that, all archs have those and the __HAVE_MD_TCB macro can be unifdef'ed as always defined. ok kettenis@ visa@ jsing@
2017-03-03Fix the lidsuspend sysctl name in arm/include/cpu.hTom Cosgrove
From Markus Hennecke, thanks
2017-03-02Add a new sysctl machdep.lidaction. The sysctl works as follows:Martin Natano
machdep.lidaction=0 # do nothing machdep.lidaction=1 # suspend machdep.lidaction=2 # hibernate lidsuspend is just an alias for lidaction, so if you change one, the other one will have the same value. The plan is to remove machdep.lidsuspend eventually when people have upgraded their /ets/sysctl.conf. discussed with deraadt, who came up with the new MIB name no objections mlarkin ok stsp halex jcs
2017-02-15Bump MAXTSIZ to 64M on arm.Jeremie Courreges-Anglas
Needed for ports/devel/llvm which builds large executables with a .text section over 32M. Remove the comment about the +/-32M limitation of branch instructions, which can be lifted using other techniques (eg cc -mlong-calls) and should not be enforced by the kernel. ok guenther@ patrick@ jsg@ kettenis@
2017-02-08In exec_elf.c: expand ELFNAME(), ELFNAME2(), and ELFNAMEEND() exceptPhilip Guenther
leaving out the size, so that ELFNAME2(exec,makecmds) becomes exec_elf_makecmds instead of exec_elf{32,64}_makecmds and then delete the ELFNAME2() and ELFNAMEEND() macros. Move the prototypes for functions local to exec_elf.c to there from exec_elf.h. Simplify the SMALL_KERNEL conditionals around the ELF coredump code. Change exec_conf.c to use the size-generic names and macros Remove exec_elf{32,64}.c and just build exec_elf.c; delete the _KERN_DO_ELF and _KERN_DO_ELF64 #defines. ok jca@, encouragement from deraadt@ and tom@
2017-02-06add a license for the code in here, all of which i seem to have written.David Gwynne
this has been pointed out to me by a couple of people now.
2017-01-06there is no longer a need to ifdef __armv7__ armv6 rev instructionsJonathan Gray
2017-01-06unifdef CPU_ARMv7 and ARM_ARCH_7Jonathan Gray
ok kettenis@ patrick@
2017-01-05Complete idle PCB allocation for secondary processors so that it makesPatrick Wildt
sense and builds as part of an MP kernel. ok kettenis@ mpi@
2017-01-04unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)Jonathan Gray
and remove some xscale definitions. ok kettenis@
2017-01-01recognise Cortex A32Jonathan Gray
2016-12-30Remove unused headers.Jeremie Courreges-Anglas
ISA and PIO don't really fit in the ARM landscape. Suggested by patrick@ and kettenis@, ok deraadt@
2016-10-22If an Access Flag fault happens while we were running the kernel andPatrick Wildt
it happened on a kernel page, we need to consult the kernel pmap instead of the current proc's pmap. Fixes panic when using tmpfs. ok kettenis@
2016-10-05Some device trees use 64-bit intermediate virtual addresses. ThisPatrick Wildt
means that even though the hardware in the end never leaves the 32-bit address space, some addresses used solely in the device tree can be bigger than 32-bit. As bus_space_map(9) takes addresses of size bus_addr_t, which is 32-bit on ARMv7, we cannot pass those virtual addresses to the parent bus, even though it will be mapped back into a 32-bit address in the end. To work around this, make bus_space_map(9) take a 64-bit address. Since this is implemented as a macro and function pointer we can safely do that without harming any other architecture. ok kettenis@ deraadt@
2016-10-02The userspace TCB_GET() shouldn't take an argumentPhilip Guenther
ok deraadt@ tom@ patrick@
2016-09-24Stick the thread control block pointer into a CPU register on ARMv7.Patrick Wildt
ok guenther@
2016-09-24If the value of r0 upon entering the kernel is zero, interpret this as theMark Kettenis
address of the end of the symbol table. This will make it possible to get rid of the code in the bootloader that patches up the kernel with the updated esym value. ok tom@, patrick@
2016-09-21Modernize arm assembly in the kernel for clang.Mark Kettenis
Based on a similar diff in bitrig. No binary change when compiled with gcc. ok patrick@
2016-09-16Define PT_ARM_EXIDX.Mark Kettenis
ok guenther@
2016-09-03Increase the number of mbufs on most architectures. This is basedAlexander Bluhm
on a guess how much memory a typical machine has. If the value is too high, users may run out of kernel memory. Then we will have to adjust this again. OK claudio@ deraadt@
2016-08-27Add support for the PXN bit in level 1 translation table descriptors andMark Kettenis
enable it on CPUs that support it. When enabled, this prevents the kernel from executing userland code. ok jsg@, tom@
2016-08-26Implement bus dma support for loading raw mappings so that we can usePatrick Wildt
xhci(4) on ARM. The only way the load raw operation can get to know about the coherent flag is via the segments. Store it there when the memory is initially mapped. Also store the virtual address which we need to know when we have to flush the caches on a non-coherent mapping. ok kettenis@
2016-08-26Remove the code that switches around MMU domains on armv7. MMU domains areMark Kettenis
basically a relic from the past. Using them doesn't make a lot of sense the way our pmaps work. Support for MMU domains isn't present in long-descriptor translation table format, so it is clearly on its way out. Based on a diff from Artituri Alm. ok patrick@
2016-08-25Enable the UWXN bit in the SCTRL register when available. This shouldMark Kettenis
prevent the kernel from accidentally executing userland pages that are writable. ok jsg@, patrick@
2016-08-24Replace pmap_fault_fixup() with an access flag fault handler on armv7.Mark Kettenis
ok tom@
2016-08-22Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with theJonathan Gray
BUS_DMA_COHERENT flag was mapped as device memory which does not use the store buffer. It is now mapped as normal inner and outer non-cacheable which does. While we drain the cpu store buffer for this case, on cortex a9 systems we also need to explicitly drain the PL310 L2's store buffer. With PL310 revisions r3p2 and later this is done automatically after being present in the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310 errata 769419. This change restores io performance with a usb flash drive attached to my cubox. Raw reads go from 3 MB/s to 19 MB/s for example. Based on code written by patrick@ some time ago. ok kettenis@ patrick@
2016-08-20Don't set MSGBUFSIZE here such that the setting in <machine/param.h> takesMark Kettenis
effect. This will let us have different settings on armv7 and zaurus and also unconfuses this developer. ok tom@, deraadt@
2016-08-19Start using to XN flag to enforce that mappings without PROT_EXEC areMark Kettenis
non-executable. ok visa@, deraadt@
2016-08-19Adjust the definitions of L1_S_COHERENT_v7, L2_L_COHERENT_v7 andMark Kettenis
L2_S_COHERENT_v7 such that bus_dmamap_sync(9) avoids unnecessary cache flushes again for DMA'able memory mapped with the BUS_DMA_COHERENT flag. I broke this in pmap7.c rev 1.35. ok tom@
2016-08-19Use Access Flag to do page reference emulation.Mark Kettenis
ok visa@
2016-08-18Separate out the Access Flag bit from the Access Permission bits in theMark Kettenis
armv7 pmap. ok tom@
2016-08-14Remove code for Intel 80219/80321 xscale processors used by armish.Jonathan Gray
Generic xscale support and support for pxa2x0 used by zaurus remains.
2016-08-14Fix setting the SMP bit in the Auxiliary Control Register. The old code wasMark Kettenis
toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP bit is essential since without it the CPU doesn't actually use its caches. The SMP bit supposed to be set before turning on the caches and the MMU, so move the setting of the Auxiliary Control Register before setting the System Control Register. ok jsg@
2016-08-10Add defines for the Access Flag as found on armv7. Fix definition of theMark Kettenis
non Global bit Small page desciptions. iConsistently name the S-bit Sharable in comments.
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