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2016-10-22If an Access Flag fault happens while we were running the kernel andPatrick Wildt
it happened on a kernel page, we need to consult the kernel pmap instead of the current proc's pmap. Fixes panic when using tmpfs. ok kettenis@
2016-10-05Some device trees use 64-bit intermediate virtual addresses. ThisPatrick Wildt
means that even though the hardware in the end never leaves the 32-bit address space, some addresses used solely in the device tree can be bigger than 32-bit. As bus_space_map(9) takes addresses of size bus_addr_t, which is 32-bit on ARMv7, we cannot pass those virtual addresses to the parent bus, even though it will be mapped back into a 32-bit address in the end. To work around this, make bus_space_map(9) take a 64-bit address. Since this is implemented as a macro and function pointer we can safely do that without harming any other architecture. ok kettenis@ deraadt@
2016-10-02The userspace TCB_GET() shouldn't take an argumentPhilip Guenther
ok deraadt@ tom@ patrick@
2016-09-24Stick the thread control block pointer into a CPU register on ARMv7.Patrick Wildt
ok guenther@
2016-09-24If the value of r0 upon entering the kernel is zero, interpret this as theMark Kettenis
address of the end of the symbol table. This will make it possible to get rid of the code in the bootloader that patches up the kernel with the updated esym value. ok tom@, patrick@
2016-09-21Modernize arm assembly in the kernel for clang.Mark Kettenis
Based on a similar diff in bitrig. No binary change when compiled with gcc. ok patrick@
2016-09-16Define PT_ARM_EXIDX.Mark Kettenis
ok guenther@
2016-09-03Increase the number of mbufs on most architectures. This is basedAlexander Bluhm
on a guess how much memory a typical machine has. If the value is too high, users may run out of kernel memory. Then we will have to adjust this again. OK claudio@ deraadt@
2016-08-27Add support for the PXN bit in level 1 translation table descriptors andMark Kettenis
enable it on CPUs that support it. When enabled, this prevents the kernel from executing userland code. ok jsg@, tom@
2016-08-26Implement bus dma support for loading raw mappings so that we can usePatrick Wildt
xhci(4) on ARM. The only way the load raw operation can get to know about the coherent flag is via the segments. Store it there when the memory is initially mapped. Also store the virtual address which we need to know when we have to flush the caches on a non-coherent mapping. ok kettenis@
2016-08-26Remove the code that switches around MMU domains on armv7. MMU domains areMark Kettenis
basically a relic from the past. Using them doesn't make a lot of sense the way our pmaps work. Support for MMU domains isn't present in long-descriptor translation table format, so it is clearly on its way out. Based on a diff from Artituri Alm. ok patrick@
2016-08-25Enable the UWXN bit in the SCTRL register when available. This shouldMark Kettenis
prevent the kernel from accidentally executing userland pages that are writable. ok jsg@, patrick@
2016-08-24Replace pmap_fault_fixup() with an access flag fault handler on armv7.Mark Kettenis
ok tom@
2016-08-22Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with theJonathan Gray
BUS_DMA_COHERENT flag was mapped as device memory which does not use the store buffer. It is now mapped as normal inner and outer non-cacheable which does. While we drain the cpu store buffer for this case, on cortex a9 systems we also need to explicitly drain the PL310 L2's store buffer. With PL310 revisions r3p2 and later this is done automatically after being present in the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310 errata 769419. This change restores io performance with a usb flash drive attached to my cubox. Raw reads go from 3 MB/s to 19 MB/s for example. Based on code written by patrick@ some time ago. ok kettenis@ patrick@
2016-08-20Don't set MSGBUFSIZE here such that the setting in <machine/param.h> takesMark Kettenis
effect. This will let us have different settings on armv7 and zaurus and also unconfuses this developer. ok tom@, deraadt@
2016-08-19Start using to XN flag to enforce that mappings without PROT_EXEC areMark Kettenis
non-executable. ok visa@, deraadt@
2016-08-19Adjust the definitions of L1_S_COHERENT_v7, L2_L_COHERENT_v7 andMark Kettenis
L2_S_COHERENT_v7 such that bus_dmamap_sync(9) avoids unnecessary cache flushes again for DMA'able memory mapped with the BUS_DMA_COHERENT flag. I broke this in pmap7.c rev 1.35. ok tom@
2016-08-19Use Access Flag to do page reference emulation.Mark Kettenis
ok visa@
2016-08-18Separate out the Access Flag bit from the Access Permission bits in theMark Kettenis
armv7 pmap. ok tom@
2016-08-14Remove code for Intel 80219/80321 xscale processors used by armish.Jonathan Gray
Generic xscale support and support for pxa2x0 used by zaurus remains.
2016-08-14Fix setting the SMP bit in the Auxiliary Control Register. The old code wasMark Kettenis
toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP bit is essential since without it the CPU doesn't actually use its caches. The SMP bit supposed to be set before turning on the caches and the MMU, so move the setting of the Auxiliary Control Register before setting the System Control Register. ok jsg@
2016-08-10Add defines for the Access Flag as found on armv7. Fix definition of theMark Kettenis
non Global bit Small page desciptions. iConsistently name the S-bit Sharable in comments.
2016-08-10Shuffle armv7 access permission bits around to something that is compatibleMark Kettenis
with setting the Access Flag Enable bit in the System Control Register. The new settings mean that read-only userland pages are no longer writable by the kernel, which is a good thing. Set the Access Flag Enable bit. ok patrick@
2016-08-08Mapping non-cachable memory as cachable and subsequently changing the mappingMark Kettenis
to non-cachable is retarded. Fix this by introducing PMAP_NOCACHE and PMAP_DEVICE flags that can be or'ed into the physical address passed to pmap_kenter(9), like we have on many of our other architectures. This way we can also properly distinguish between device memory and normal (non-cachable) memory. ok visa@
2016-08-07Add XOR cookies for lr and sp. Stop saving/restoring r12 to/from the jmpbuf.Philip Guenther
Switch from calling obsolete sig{block,setmask} to directly using the sigprocmask syscall. ok deraadt@ kettenis@
2016-08-06Put page tables in normal cachable memory on armv7. Check if the MMU walksMark Kettenis
the page tables coherently and also skip flushing modified ptes out of the cache in that case. Speeds up building a kernel with a factor of two on Cortex-A9 (tested by me) and Cortex-A8 (tested by mglocker@). ok patrick@
2016-07-31Recognise Cortex A35 and Cortex A73.Jonathan Gray
2016-07-31Instead of testing MIDR values for every model of Cortex processor checkJonathan Gray
MMFR0 for an ARMv7 VMSA MMU that can handle short descriptors when setting ARMv7 function pointers. ARMv8 in AArch32 mode is documented to set the same bits. ok patrick@
2016-07-27Instead of passing the raw reg property to simplebus nodes,Patrick Wildt
pass a pre-processed array of fdt_reg structs. This means that the drivers don't have to understand the cell properties themselves but can rely on the 64-bit addr/size pairs. ok kettenis@
2016-07-13The "#address-cells" and "#size-cells" properties define the sizePatrick Wildt
of the memory address and length information. The root node passes this information down to the children and it can be overwritten by other nodes inbetween. Pass these properties as part of the fdt attach args, so that we can grab that information quickly inside the drivers. ok kettenis@
2016-06-09Fetch "reg" and "interrupts" properties and pass them down as attach args toMark Kettenis
our children. ok jsg@
2016-05-27Remove the non ELF macrosTheo de Raadt
ok millert
2016-05-21Implement openprom(4) for armv7.Mark Kettenis
ok deraadt@
2016-05-16Implement membar(9) for armv5. As there are no barrier instructions inJonathan Gray
armv5 this is just a "memory" clobber hint to the compiler. ok kettenis@
2016-05-10SROP mitigation. sendsig() stores a (per-process ^ &sigcontext) cookieTheo de Raadt
inside the sigcontext. sigreturn(2) checks syscall entry was from the exact PC addr in the (per-process ASLR) sigtramp, verifies the cookie, and clears it to prevent sigcontext reuse. not yet tested on landisk, sparc, *88k, socppc. ok kettenis
2016-05-04Initial support for MSI-X. Only supported on amd64 for now. I have diffs toMark Kettenis
actually use this in em(4) and xhci(4), but I'm not committing those yet because we almost certainly need to save and restore the MSI-X registers during suspend/resume. However, this allows mpi@ to play with multiple-vector support in networking hardware. Requested by mpi@ ok mlarkin@, mikeb@
2016-05-02Rework mainbus and implement simplebus to be able to span a tree-likePatrick Wildt
topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices. ok jsg@ kettenis@
2016-04-27G/C DDB_REGS.Martin Pieuchot
2016-04-25Implement atomic operations using the atomic instructions availablePatrick Wildt
since ARMv6K. As we also support ARMs that are older than that, guard the new atomic operations with an ifdef specifically for ARMv7. ok jsg@
2016-04-25Add macros to access cp14/cp15 registers by name instead of sixJonathan Gray
arguments to instructions. Based on a file from FreeBSD. ok patrick@
2016-04-24whitespace cleanupPatrick Wildt
2016-04-24EABI's Procedure Call Standard (AAPCS) requires the stack pointerPatrick Wildt
to be 8-byte aligned. To guarantee this, align the stack pointers passed to user processes and make sure the in-kernel stacks are properly aligned, too. ok jsg@
2016-04-04Store curcpu pointer in TPIDRPRW.Patrick Wildt
This will especially be helpful in future multiprocessor efforts. ok jsg@
2016-04-04Read cache line sizes from CP15 Cache Type Register.Patrick Wildt
Previously we used the primary data cache's information on how big the cache lines are. The CTR gives us better information about how big the smallest cache line sizes (controlled by the CPU) are. ok jsg@
2016-04-04Set the SMP/coherency bit in ACTLR on Cortex A models it is documentedJonathan Gray
to exist on. This is required to use ldrex/strex in some cases. ok patrick@
2016-04-03Add cpu_auxcontrol() to clear and set bits in the implementation/modelJonathan Gray
specific Auxiliary Control Register (ACTLR). ok patrick@
2016-04-03remove unused cpu_lock codeJonathan Gray
2016-03-22Remove support for ARM11. This was the last unused and unmaintainedPatrick Wildt
processor in our code. Now we're left with only armv7 and XScale for armish and zaurus. ok jsg@
2016-03-22Remove support for ARM10.Patrick Wildt
ok jsg@
2016-03-22Remove support for ARM9E. This is another step in the plan to removePatrick Wildt
all unused and unmaintained ARM processors from the past. ok bmercer@ jsg@
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