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AgeCommit message (Collapse)Author
2019-11-07Convert db_addr_t -> vaddr_t but leave the typedef for now.Martin Pieuchot
2019-10-27Add code to spin up secondary CPUs.Mark Kettenis
ok jsg@
2019-09-30Synch the cpu match/attach/identify code with arm64. This drops someMark Kettenis
information from dmesg that is no longer relevant to ARMv7 CPUs in favour of printing the full architected cache hierarchy in the same way as we do on arm64. It also is another small step towards SMP support on armv7. ok patrick@
2019-09-23Implement DVFS support.Mark Kettenis
ok patrick@
2019-03-13Store whether or not the VFP was active on entering the unhandledPatrick Wildt
instruction trap and pass it to the VFP fault handler, so that it knows if we faulted with the VFP active or disabled. Reading the status in the VFP fault handler does not work since at that point the VFP already got disabled. ok kettenis@
2019-01-22flense more trailing whitespacePeter Hessler
2019-01-22remove trailing whitespace in the Laptop Package part of the license text.Peter Hessler
no words or punctation were modified.
2018-12-05Include srp.h where struct cpu_info uses srp to avoid erroring out whenJonathan Gray
including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
2018-10-02Unify the MD byteswapping code as much as possible across architectures.Christian Weisgerber
Use inline functions instead of GNU C statement expressions, and make them available to userland. With clues from guenther@. ok guenther@ kettenis@
2018-09-14Unify and bump some of the NMBCLUSTERS defines. Some archs had it set toClaudio Jeker
4MB which is far too low especially when the platform is able to run MP. New limits are, amd64 = 256M; arm64, mips64, sparc64 = 64M; alpha, arm, hppa, i386, powerpc = 32M; m88k, sh = 8M Still rather conservative numbers but much better than before. At least some hangs of arm64 build boxes was caused by this. OK kettenis@, visa@
2018-08-08Extend the FDT interrupt API to support masking and unmasking IRQs.Patrick Wildt
Discussed with kettenis@
2018-08-06Make it possible to build a MULTIPROCESSOR kernel on armv7. While thisMark Kettenis
doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup of <machine/cpu.h> along the lines of what I did earlier on arm64. Makes armv7 use the MI mplock implementation and implements copyin32. ok patrick@
2018-08-06Give the FDT interrupt API a more generic naming by replacing thePatrick Wildt
arm_intr_* prefix with fdt_intr_*. ok kettenis@
2018-07-09Add PCI machdep headers based on the arm64 port.Patrick Wildt
ok kettenis@
2018-06-30Remove strange /* End of file */ style.Theo de Raadt
2018-06-23Save and restore FPU registers around signal handlers.Mark Kettenis
Fixes the random crashes in sh(1). ok guenther@
2018-06-22Save and restore the relevant FPU state on armv7.Mark Kettenis
ok deraadt@
2018-05-07Use speed from device tree for serial console on armv7 too.Mark Kettenis
ok visa@, patrick@
2018-03-20To allow sharing more code between armv7 and arm64 platforms, introducePatrick Wildt
a common bus space tag that can be used for early console attachment. ok kettenis@
2018-03-16Make FPU registers available in core dumps and through ptrace(2).Mark Kettenis
ok visa@, patrick@
2018-03-05Do not redefine PAGE_SHIFT/PAGE_SIZE/PAGE_MASK in vmparam.h; thoseTheo de Raadt
definitions are already found in param.h ok jsg
2018-03-05#define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archTheo de Raadt
needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
2018-03-01AAPCS requires 8-byte alignment for 64-bit types. We missed this when weMark Kettenis
did the big EABI switch. Do it now before we get into trouble with using floating-point and vector instructions that actually require things to be properly aligned. This breaks the ABI. In particular, file descriptor passing will be broken if kernel and userland are not in sync. Upgrading from a snap is highly recommended. ok otto@, patrick@, jsg@, phessler@, deraadt@
2018-02-10Convert armv7 to MI mutex.Martin Pieuchot
Tested by jsg@, ok patrick@
2018-01-26Add kernel support for the VFP FPU/SIMD unit. Based on a diff by drahn@.Mark Kettenis
This allows us to use floating-pointer and vector instructions in userland code. The current implementation assumes all 32 VFP registers are present. This should be the case on all armv7 hardware currently supported by OpenBSD. ok patrick@
2018-01-23Revise 'struct fpreg' such that it can actually represent the full VFPv3-D32Mark Kettenis
state. ok patrick@
2018-01-15Improve defense against branch predictor target injection (Spectre "variant 2")Mark Kettenis
attacks. OpenBSD/armv7 is already in pretty good shape as we have always been flushing the branch predictor cache on context switches. This diff adds additional flushes to page faults in kernel address space. The impact on performance should be minimal as these page faults should only happen when userland (deliberately or accidentally) tries to access kernel addres space which would lead to a fatal signal (SIGSEGV or SIGBUS). Loosely based on changes made by Marc Zyngier in Linux and based on information in Arm Trusted Firmware Security Advisory TFV 6. Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets the ACTRL[0] bit for this diff to be effective. Also note that with this diff Cortex-A57 is still vulnerable. ok jsg@
2017-10-01set MAXSSIZ to the same value as on all other architectures (32MB)Christian Weisgerber
ok deraadt@
2017-09-05Move mutex, condvar, and thread-specific data routes, pthread_once, andPhilip Guenther
pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
2017-08-27Add glass console support for arm64. This uses the "stdout-path" propertyMark Kettenis
of the /chosen node in the device tree to decide whether the framebuffer should be used as the console device. Most, if not all, machines will have that set to use a serial console and there is no easy way yet to change that. ok jsg@
2017-08-20Add Cortex-A55 and Cortex-A75 part numbers.Jonathan Gray
2017-08-12remove apmwarn sysctl which is not usedTed Unangst
2017-07-31Use unsigned long instead of uint32_t, which is the appropriate integerMark Kettenis
type for storing pointers in our universe. Avoids an implicit dependence on <sys/types.h>. ok tom@
2017-07-12remove CPU_LIDSUSPEND/machdep.lidsuspendMartin Natano
"fire away!" tedu
2017-06-29kill RCSID macros; discussed with millertTheo de Raadt
2017-06-23Unbreak profiling assembly functions in userland by defining theMartin Pieuchot
correct prologue if compiled with -DPROF. ok deraadt@
2017-05-18Fix kernel build on armv7 and sh.Visa Hankala
Pointed out by deraadt@
2017-05-12Make atomic.h ready to be included in userland.Martin Pieuchot
- keep setbits/clearbits and virtio barriers inside _KERNEL - prefix def_atomic_xxx macros with underscores
2017-05-08add a BUS_DMA_64BIT flag to bus_dma on all our archs.David Gwynne
this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
2017-04-27Bring over the changes to mainbus(4) and simplebus(4) from arm64.Mark Kettenis
2017-04-24Add support for Cortex-A12. Even though ARM rebranded these as Cortex-A17Mark Kettenis
they have a different ID from "real" Cortex-A17 cores. ok phessler@, patrick@
2017-04-20Hook up mutex(9) to witness(4).Visa Hankala
2017-04-13Provide mips64 with kernel-facing TCB_{GET,SET} macros that store itPhilip Guenther
in struct mdproc. With that, all archs have those and the __HAVE_MD_TCB macro can be unifdef'ed as always defined. ok kettenis@ visa@ jsing@
2017-03-03Fix the lidsuspend sysctl name in arm/include/cpu.hTom Cosgrove
From Markus Hennecke, thanks
2017-03-02Add a new sysctl machdep.lidaction. The sysctl works as follows:Martin Natano
machdep.lidaction=0 # do nothing machdep.lidaction=1 # suspend machdep.lidaction=2 # hibernate lidsuspend is just an alias for lidaction, so if you change one, the other one will have the same value. The plan is to remove machdep.lidsuspend eventually when people have upgraded their /ets/sysctl.conf. discussed with deraadt, who came up with the new MIB name no objections mlarkin ok stsp halex jcs
2017-02-15Bump MAXTSIZ to 64M on arm.Jeremie Courreges-Anglas
Needed for ports/devel/llvm which builds large executables with a .text section over 32M. Remove the comment about the +/-32M limitation of branch instructions, which can be lifted using other techniques (eg cc -mlong-calls) and should not be enforced by the kernel. ok guenther@ patrick@ jsg@ kettenis@
2017-02-08In exec_elf.c: expand ELFNAME(), ELFNAME2(), and ELFNAMEEND() exceptPhilip Guenther
leaving out the size, so that ELFNAME2(exec,makecmds) becomes exec_elf_makecmds instead of exec_elf{32,64}_makecmds and then delete the ELFNAME2() and ELFNAMEEND() macros. Move the prototypes for functions local to exec_elf.c to there from exec_elf.h. Simplify the SMALL_KERNEL conditionals around the ELF coredump code. Change exec_conf.c to use the size-generic names and macros Remove exec_elf{32,64}.c and just build exec_elf.c; delete the _KERN_DO_ELF and _KERN_DO_ELF64 #defines. ok jca@, encouragement from deraadt@ and tom@
2017-02-06add a license for the code in here, all of which i seem to have written.David Gwynne
this has been pointed out to me by a couple of people now.
2017-01-06there is no longer a need to ifdef __armv7__ armv6 rev instructionsJonathan Gray
2017-01-06unifdef CPU_ARMv7 and ARM_ARCH_7Jonathan Gray
ok kettenis@ patrick@
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