| Age | Commit message (Expand) | Author |
|---|
| 2017-04-24 | Stop dumping registers on "normal" segmentation faults. Do print the contents | Mark Kettenis |
| 2017-04-15 | The tlb flushes in pmap_set_{l1,l2,l3} use ranges that don't fully make sense. | Mark Kettenis |
| 2017-04-13 | Use the non-interrupt-safe pool allocator for the vp pool to avoid runninng | Mark Kettenis |
| 2017-04-11 | Revise 'struct fpreg' and dump floating-point register in core dumps. Also | Mark Kettenis |
| 2017-04-04 | Cleanup the code further. Get rid of the remaining C++-style comments, | Mark Kettenis |
| 2017-04-02 | On ARMv8, the translation table walk is fully coherent so there is no | Mark Kettenis |
| 2017-03-28 | Add an instruction synchronisation barrier instruction after changing | Jonathan Gray |
| 2017-03-28 | Previous W^X diff only changed the access permissions in the bootstrap page | Mark Kettenis |
| 2017-03-24 | Simplify ASID allocation code considerably by allocating an ASID up front | Mark Kettenis |
| 2017-03-22 | Implement kernel W^X for arm64. For this purpose align the different segments | Mark Kettenis |
| 2017-03-21 | Revise the definition of "struct reg" to have a layout compatible with other | Mark Kettenis |
| 2017-03-16 | Remove some unused variables, unused types, duplicated/unused function | Mark Kettenis |
| 2017-03-13 | When we do an ASID rollover, we unassign all ASIDs and do a complete | Mark Kettenis |
| 2017-03-13 | Don't limit physmem to 2GB confirmed to work with 16GB by deraadt@. | Jonathan Gray |
| 2017-03-12 | Add a "dsm ishst" barrier before TLB maintenance instructions. The ARMv8 | Mark Kettenis |
| 2017-03-12 | Bring SROP mitigation to arm64. Make some small modifications to the arm | Mark Kettenis |
| 2017-03-12 | Simplify pmap_proc_iflush(); there is no need for the per-page logic if we | Mark Kettenis |
| 2017-03-09 | Change the interrupt routing API to take a pointer to a "struct cpu_info" | Mark Kettenis |
| 2017-03-08 | Establish API to route interrupts to specific CPU cores. | Patrick Wildt |
| 2017-02-28 | Switch geteblks()'s size argument from int to size_t. It's called with | Martin Natano |
| 2017-02-25 | MSI interrupts are established in a different way as well. Instead of | Patrick Wildt |
| 2017-02-24 | Retire the global interrupt establish and disestablish API. It has been | Patrick Wildt |
| 2017-02-24 | Implement an API for establishing legacy PCI interrupts. This specific | Patrick Wildt |
| 2017-02-22 | The AMD Seattle SoC incorporates DMA coherent controllers, especially | Patrick Wildt |
| 2017-02-20 | STACKALIGN() already does the right thing by casting the given argument | Patrick Wildt |
| 2017-02-19 | Fix asynchronous system traps so that they actually work. Fixes at | Patrick Wildt |
| 2017-02-18 | Extend and fix bus_dmamap_load_raw() implementation to make xhci(4) | Patrick Wildt |
| 2017-02-17 | Fix up and use the device memory attribute for device mappings. Add | Patrick Wildt |
| 2017-02-17 | Use a proper memory attribute for write-through instead of reusing | Patrick Wildt |
| 2017-02-17 | Remove a bunch of dead code in bus dma. This code still needs actual | Patrick Wildt |
| 2017-02-17 | Implement DDB backtrace support. In addition to the actual tracing, | Patrick Wildt |
| 2017-02-17 | Fix inverted PMAP_CANFAIL logic. | Jonathan Gray |
| 2017-02-15 | whitespace fixes | Patrick Wildt |
| 2017-02-15 | Implement permission checks in the copy routines. When they were | Patrick Wildt |
| 2017-02-12 | Split up fork1(): | Philip Guenther |
| 2017-02-08 | Pass the physical address to the end of symbols to the kernel. From | Patrick Wildt |
| 2017-02-07 | Since the instruction cache does not in any way snoop the data cache | Patrick Wildt |
| 2017-02-07 | For consistency sake, apply the inner shareable attribute to the bootstrap | Patrick Wildt |
| 2017-02-06 | Move cache and tlb flush functions, which were mostly inline assembly, | Patrick Wildt |
| 2017-02-06 | Change the pmap_pmap_pool ipl from IPL_VM to IPL_NONE. Matches the | Jonathan Gray |
| 2017-02-05 | _dmamem_alloc_range() stores physical addresses in the segments, so | Patrick Wildt |
| 2017-02-05 | Add implementation for intr_barrier(9). | Patrick Wildt |
| 2017-02-05 | Implement another pagetable level for bootstrapping machines that have | Patrick Wildt |
| 2017-02-05 | As far as we understood the architecture reference manual it should | Patrick Wildt |
| 2017-02-04 | Read the data cache size instead of hardcoding some value. We might | Patrick Wildt |
| 2017-02-04 | A bit of code and comment cleanup. | Patrick Wildt |
| 2017-02-04 | Remove gdb waitcount debug code and dummy print. | Patrick Wildt |
| 2017-02-03 | Implement a helper that creates an L0 pagetable entry pointing to | Patrick Wildt |
| 2017-02-03 | Set the context id and counter offset to a known value. Enable access | Patrick Wildt |
| 2017-02-03 | Use PAGE_SHIFT instead of encoding the number. | Patrick Wildt |
