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of the esr_el1 register for unhandled userland exceptions (and continue to
dump the registers in that case).
Handle breakpoint traps and make sure we call refreshcreds() on userland traps.
ok jsg@
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But those tlb flushes shouldn't be necessary anyway, so simply remove them.
Simplify the tlb flushing code now that we no longer flush ranges, and
revive the branch that doesn't flush a specific ASID for the kernel pmap
since its mappings are global.
ok patrick@, visa@
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out of kva in the kmem_map. Avoids a hang when spawning a lot of processes.
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reset the floating-point register state upon exec.
ok guenther@
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remove some debug printfs, get rid of STATIC and __inline defines and
remove a bit more unused code.
ok drahn@, visa@
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reason to explicitly flush the cache before invalidating the TLB. The
barrier that is included in out TLB flushing code should be enough to
guarantee that the TLB walking hardware sees the updated page table
contents, so the explicit barriers can go as well. Sanitize the code
immediately surrounding the removed bits while I'm there.
Tested by jsg@, ok drahn@, visa@
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the vfp state via cpacr_el1. This matches the advice given in the
"Synchronization requirements for system registers" section of the ARMv8
ARM.
Without this an overdrive 1000 with A1120 (Cortex A57 r1p2) reliably
triggers "panic: VFP exception in the kernel" when init(8) is run.
ok drahn@ kettenis@
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tables. We need to set them in the final kernel page tables as well.
ok visa@
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when a pmap is created and freeing it when the pmap is destroyed. This
diff relies on the fill 16-bit ASID space being implemented in the processor.
While this is documented as an optional feature in the ARMv8 architecture
reference manual, all ARMv8 processors seen in the wild so far implement
the full 16-bit space. This change incorporates changes by drahn@ to
allocate an empty page table for the lower half of the address space for the
kernel.
ok drahn@, patrick@
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containing .text, .rodata and .data/.bss at 2MB boundaries and set the
appropriate access permissions on the block translations.
ok patrick@
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operating systems. Implement process_read_regs() and make
process_read_fpregs() clear the struct fpreg to avoid leaking kernel stack
contents. This makes core dumps actually usable.
ok drahn@
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prototypes and duplicate defines.
Also remove PMAP_CACHE_PTE, which is unused and misleading since the page
tables are mapped as normal write-back cached memory.
Fix a bunch on KNF issues as well.
ok patrick@
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TLB flush to remove any cached translations. The problem is that we
do this while we're still running with the page tables of the old
process. Even if we don't actually reference any userland pages, the
CPU can speculatively load translations into the TLB. And those might
survive until we reassign the ASID of the old process to a new
process. This new process will then see the wrong physical page,
which inevitably leads to corruption of some sorts.
Fix this issue by delaying the TLB flush until after we switch to the
page tables and ASID of the new process.
ok patrick@, drahn@
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architecture reference manual says this is required (D4.7 under "Ordering
and completion of TLB maintenance instructions" to guarantee that the
translation table walk can observe previous store to the page tables. It
also has a note that says
In all cases in this section, where a DMB or DSB is referred to, it
refers to a DMB or DSB whose required access type is both loads and
stores.
But both Linux and FreeBSD use a Store-Store barrier here.
Sadly this doesn't fix the arm64 stability problems (or at least not all
of them).
ok patrick@
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code as well to improve diffability. Changes the types used in the arm64
"struct sigcontext" to avoid having to include <sys/types.h>.
ok deraadt@
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are flushing by using the virtual address.
ok jsg@
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instead of a cpu number.
ok patrick@
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Based on and ok drahn@
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unsigned variables as argument in most places anyway. Decrease the
chance of signedness/range mismatch issues.
ok stefan
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simply hooking up the interrupt handler and returning an MD cookie, we
need to pass back information for the PCI controller to configure its
interrupt correctly. For this, add another establish routine into the
FDT-based interrupt API which looks up msi-controller nodes and calls
their MSI-specific establish function if requested.
ok kettenis@
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of good use for supporting multiple SoCs with each their own interrupt
controllers, but as of now we have replaced it wit the FDT-enabled API.
ok kettenis@
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establish function parses the device tree's interrupt map to discover
the correct interrupt controller node and interrupt cells for the given
PCI node. After retrieving that information we can do the same the
normal FDT establish API already does.
ok kettenis@
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AHCI, PCIe and Ethernet. Since these systems rely on cache snooping,
we must not map pages that are supposed to be coherent as uncacheable.
Instead if we have a cache coherent device, create a bus tag and mark
that tag as coherent. For users of that tag we can simply use normal,
cached memory.
ok kettenis@
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to unsigned long, so explicitly casting the address to unsigned int only
leads to truncation.
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least one regression test and allows processes to be killed using
Ctrl-C. Discussed with Dale Rahn.
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work. Copied from the 32-bit ARM version, with a few minor changes
for arm64.
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inner shareable attributes while there.
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the nocache attribute.
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cache flushing implemented, but apparently we have not yet encountered
a hardware or controller where this was necessary.
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clean up a few address types from int to vaddr_t, implement 8 byte
reads and remove the unused db_fetch_reg() function.
From Dale Rahn
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From Dale Rahn. ok patrick@
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initially copied from armv7 no parallel instructions to ldrbt and strbt
were found, so a different permission model based on the addressing was
assumed. This was incorrect as the AArch64 provides ldtrb and sttrb to
do load/store operations with userland permissions.
From Dale Rahn.
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- FORK_THREAD handling is a totally separate function, thread_fork(),
that is only used by sys___tfork() and which loses the flags, func,
arg, and newprocp parameters and gains tcb parameter to guarantee
the new thread's TCB is set before the creating thread returns
- fork1() loses its stack and tidptr parameters
Common bits factor out:
- struct proc allocation and initialization moves to thread_new()
- maxthread handling moves to fork_check_maxthread()
- setting the new thread running moves to fork_thread_start()
The MD cpu_fork() function swaps its unused stacksize parameter for
a tcb parameter.
luna88k testing by aoyama@, alpha testing by dlg@
ok mpi@
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armv7 we inherited the mechanism to manually modify the kernel symbol
table to change the value of esym. We don't use this, but instead use
the virtual address that is passed to the kernel. This change makes us
only work on and hand out physical addresses. Bump the efiboot version
to make this ABI change more visible.
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we need to make sure to clean the data and invalidate the instruction
cache upon entering a page with pmap_enter(). Since it is possible
that pmap_enter() does not directly enter the page, we need to do the
same dance in the pmap fault fixup code. Every new writeable mapping
or write removes a page's flag to mark it unflushed. The next time
pmap_enter() is called or a fault happens on that VA, it has to be
flushed and invalidated again. This was heavily discussed with Dale
Rahn.
On the Pine64 and Raspberry Pi 3 we have been very lucky to not run
into any cache issues, especially with the instruction cache. The
AMD Seattle seems to be a different kind of beast where we actually
have to care about these things. This finally brings the machine
into userland.
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pagetables as well. Also replace the number for write-back with a proper
define.
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into separate functions. This makes them reusable from other parts in
the kernel. Assembly and header are taken from FreeBSD, but modified
to fit our requirements and with some unnecessary stuff removed. While
there remove micro optimization for uniprocessor kernels.
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other archs.
ok patrick@
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upon free don't try to convert it from virtual to physical again.
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their memory mapped above 39 bits of address space. Since our pmap is
configured to use a 3 level pagetable userland we need to reconfigure
the size back to 39 bits as soon are in virtual address space and have
finished using the FDT via the 1:1 map.
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only need a data cache write-back to PoU (Point of Unification) to
make changes to the pagetables visible. Interestingly enough, this
does not seem to work on the AMD hardware. Instead we need to flush
to PoC (Point of Coherence), which essentially means flush to memory.
Surprisingly even FreeBSD flushes their pagetable changes to PoC, and
they have done that since the code was first imported. Until we find
out whether this is a software bug or just completely expected, switch
us to flushing to PoC as well. This makes my AMD machine behave.
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want to start caching that value somewhere though.
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a L1 pagetable. Needed for machines that need 4 level pagetables
on bootup.
From FreeBSD
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to the physical timers at EL1.
From FreeBSD
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From FreeBSD
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