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path: root/sys/arch/arm64/include
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2023-03-19Aggressively randomize the location of the stack on all 64-bit architecturesMark Kettenis
except alpha. This will put the stack at a random location in the upper 1/4th of the userland virtual address space providing up to 26 additional bits of randomness in the address. Skip alpha for now since it currently puts the stack at a (for a 64-bit architecture) very low address. Skip 32-bit architectures for now as well since those have a much smaller virtual address space and we need more time to figure out what a safe amount of extra randomizations is. These architectures will continue to use a mildly randomized stack address through the existing stackgap random mechanism. We will revisit this after 7.3 is released. This should make it harder for an attacker to find the stack. ok deraadt@, miod@
2023-02-19Add support for deep(er) idle states that can be entered using PSCI. ForMark Kettenis
now this only supports states advertised in device trees, but ACPI support could be added as well. The parsing of the idle states as well as the heuristic to pick the deepest one is probably a bit to simple, but more complex cases can be added later. Worst case cores will use WFI and use more power in suspend. ok phessler@
2023-02-16Remove obsolete __HAVE_VM_PAGE_MD define - all platforms provide vm_page_mdMiod Vallat
those days, and nothing checks for that symbol anymore.
2023-01-22Simplify the (so far unused) apm_record_event() function a bit and use itMark Kettenis
to send a resume event to userland when we come out of suspend. ok deraadt@
2023-01-21Make bus_dmamem_alloc_range(9) API available.Mark Kettenis
ok patrick@, deraadt@, phessler@
2023-01-14Implement access to EFI variables and ESRT through an ioctl(2) interfaceMark Kettenis
that is compatible with what FreeBSD and NetBSD have. Setting EFI variables is only allowed at securelevel 0 and below. Heavily based on work done by Sergii Dmytruk. ok yasuoka@
2023-01-09Allwinner hardware sucks! The ARM generic timer on the A64 has a bugMark Kettenis
where the bottom 9 bits of the counter register can't be trusted if any of the higher bits are rolling over. This is an unpublished errata so the details aren't known. Adopt the same workaround that Linux has. This will disable the userland timecounter support on hardware affected by the hardware. We will need a similar workaround in libc to restore that functionality. tested by semarie@ ok cheloha@
2022-12-31Add machdep.lidaction to machdep names list.Patrick Wildt
ok mpi@
2022-12-23Add detection of EPAN feature bit.Mark Kettenis
ok deraadt@
2022-12-21Pull enabling/disabling wakeup interrupt handling out of the aplintc(4)Mark Kettenis
DVACT_SUSPEND/DVACT_RESUME handling and push it into the MD code that handles "suspend-to-idle". This way a failure in DVACT_SUSPEND handling will not result in hosed interrupts on the primary interrupt controller if we abort the suspend operation. requested by deraadt@ ok patrick@
2022-12-10Mitigate Spectre-BHB by using core-specific trampoline vectors. On some coresPatrick Wildt
Spectre-BHB can be mitigated by using a loop that branches a number of times. For cores where this does not suffice, or where Spectre-V2 needs to be handled as well, try and call into a new PSCI function that mitigates both Spectre-V2 and Spectre-BHB. Some newer machines, which might not be in anyone's hands yet, have an instruction (CLRBHB) that clears the BHB. If ECBHB is set, the BHB isn't vulnerable. If we have CSV2_3/HCXT, it's not vulnerable at all. No visible performance dropoff on a MacchiatoBin (4xA72) or Lenovo x13s (4xA78C+ 4xX1C), but around 2-3% on a LX2K (16xA72) and RK3399 (4xA53+2xA72). ok kettenis@
2022-12-09Add detection for Spectre-BHB related CLRBHB, ECBHB and CSV2_3/HCXTPatrick Wildt
feature bits. ok kettenis@
2022-12-08_C_LABEL() and _ASM_LABEL() are no longer useful in the "everythingPhilip Guenther
is ELF" world. Eliminate use of them in amd64, arm64, armv7, i386, macppc, mips64, and sparc64 code. ok deraadt@ jca@ krw@
2022-11-26Add arm64 lid_action sysctl for Apple Silicon laptops.Tobias Heider
ok kettenis@
2022-11-24Expose the complete set of ID registers as defined in the current versionMark Kettenis
of ARMv8/ARMv9. Make sure we only expose the features that we know about and support in our kernel. This matches what Linux does. For now, mostly restrict ourselves to features defined in ARMv8.5 which means that we only actually implement support for ID_AA64ISAR0_EL1, ID_AA64ISAR1_EL1, ID_AA64PFR0_EL1 and ID_AA64PFR1_EL1. For the other registers we simply always return 0. ok deraadt@
2022-11-24Document a few more ID register bits. This should add most of the stuffMark Kettenis
in ARMv8.5 as far as the ISAR and PFR registers are concerned. ok deraadt@
2022-11-21Get rid of pmap_map_early(). This is part of my crusade against the use ofMark Kettenis
1G mappings for the PA = VA identity mapping used in the early boot phase of the kernel and when spinning up CPUs. The mappings are dangerous since they might (unintentially) covering address ranges that should not be mapped (i.e. secure memory) which is dangerous on arm64 since the architecture allows speculative access to any address for which a valid mapping exists and even speculative access may cause the machine to misbehave. So instead of relying on the PA = VA identity mapping, call pmap_bootstrap() earlier such that we can use pmap_kenter_cache() to enter mappings for the FDT. ok miod@
2022-11-09Implement wakeup interrupt support. For now this is only implemented forMark Kettenis
aplintc(4); other arm64 interrupt controllers will follow. ok patrick@
2022-11-08KNF/whitespace - no code changeMike Larkin
2022-11-08arm64: switch to clockintr(9)Scott Soule Cheloha
Switch arm64 to the clockintr(9) subsystem. - Remove the custom per-CPU clock interrupt schedule from agtimer(4). - Remove the custom randomized statclock() pieces from agtimer(4). - Add agtimer_rearm(), agtimer_trigger(), and wire up agtimer_intrclock. There is one wart: - The AArch64 spec says that a value written to CNTV_TVAL_EL0 is "treated as a signed 32-bit integer" [1]. kettenis@ doesn't know what to make of this. I'm capping the value at INT32_MAX for now. It's possible I am misreading this, though. Tested by kettenis@ on his Apple M1 mini. Tested by me on my Raspberry Pi 4B. Link: https://marc.info/?l=openbsd-tech&m=166776342503304&w=2 [1] "Arm Architecture Reference Manual for A-profile architecture" issue I.a, section D17.11.27 ("CNTV_TVAL_EL0"). ok kettenis@
2022-11-08Move definitions for CNTV_CTL_EL0 to armreg.h.Mark Kettenis
ok mpi@, jsg@, phessler@, patrick@
2022-11-07Implement db_write_text/bytes() which add support for ddb(4)'s breakpoints.Martin Pieuchot
Based on a diff from gerhard@, ok kettenis@
2022-10-04Add a few more PSTATE bits.Mark Kettenis
ok deraadt@
2022-08-30Remove long unused WARN_REFERENCES macro; idea guenther@, ok jsg@ jca@Miod Vallat
2022-08-29use ansi volatile keyword, not __volatileJonathan Gray
ok miod@ guenther@
2022-08-24Add DIT CPU feature.Mark Kettenis
ok beck@
2022-07-13Implement the fundamentals for suspend/resume on arm64. This uses PSCIMark Kettenis
to turn off the secondary CPUs and suspend the primary CPU using the CPU_OFF and SYSTEM_SUSPEND calls. A new "halt" IPI is added to turn off the ssecondary CPUs. This IPI is implemented for the ampintc(4) and agintc(4) interrupt controllers. Fulle suspend/resume support is only implemented for ampintc(4). This is enough to suspend and resume boards based on the Allwinner A64 SoC, provided the necessary wakeup interrupts have been set up (not part of this commit). ok patrick@
2022-07-02remove machine/lock.h where unusedJonathan Gray
Previously for __cpu_simple_lock parts. Now only hppa and m88k use __cpu_simple_lock (and hppa uses atomic.h for it). ok miod@ visa@
2022-06-28Remove unused field d_poll from struct cdevsw.Visa Hankala
OK miod@ mpi@
2022-06-16Bump MAXCPUS to 256, which is the maximum number of cores on a dual socketMark Kettenis
machine with Ampere Altra Max CPUs. OpenBSD should run on such a machine now. ok patrick@, deraadt@
2022-05-24Address the clang 13 "changed binding to STB_WEAK" warning on arm64:Philip Guenther
add _?ENTRY_NB to asm.h, switch libc's asm bits to the generic DEFS.h, and use ENTRY_NB as necessary. Also, give sizes to the htonl/htons symbols and mark them as weak. ok kettenis@ miod@
2022-03-23Export the ID_AA64ISARn_EL1 registers to userspace through sysctl(2) suchMark Kettenis
that we can detect which instruction set extensions are supported without relying in catching SIGILL. ok deraadt@
2022-03-21Remove unused files which serve no purpose in OpenBSD; with and ok jsg@Miod Vallat
(works better with `cvs rm' prior to commit...)
2022-02-24Fix PIC_SYM() macro: it never needs to token paste, so it's notPhilip Guenther
dependent on __STDC__ and doesn't need the ## operator. ok jsg@
2022-02-23unifdef __ELF__Jonathan Gray
ok guenther@
2022-02-04Define __HAVE_PMAP_MPSAFE_ENTER_COW; the ARMv8 architecture requiresMark Kettenis
that we implement proper "break-before-make" semantics and I've stared at the code for long enough that I've convinced myself that we do indeed implement this correctly several times. ok guenther@
2022-01-02slignment -> alignmentJonathan Gray
2022-01-01Rewrite the kernel FPU handling code. The new code saves the FPU stateMark Kettenis
in cpu_switch() instead of at the kernel edge and gets rid of the FPU state tracking in struct cpu_info and struct pcb. This fixes the random crashes seen with SMP kernels on Apple M1. ok patrick@
2021-11-22Hack alert! Apple M1 systems still don't work with an MP kernel.Mark Kettenis
In order to make progress (and protect myself from things dumping cores left and right when I run sysupgrade) abuse the hw.smt mechanism to only schedule processes on the primary CPU. ok deraadt@, patrick@
2021-09-02Fix the TCR_TG0_xxx definitions and add TCR_TG0_4K to the initial settingMark Kettenis
of TCR_EL1 in locore to make clear we use 4K pages for both userland and the kernel. ok patrick@
2021-08-30Remove typedef of db_addr_t; mpi converted the users of it to vaddr_t alreadyJasper Lievisse Adriaanse
back in 2019. ok mpi@
2021-07-06Introduce CPU_IS_RUNNING() and us it in scheduler-related code to preventMark Kettenis
waiting on CPUs that didn't spin up. This will allow us to spin down CPUs in the future to save power as well. ok mpi@
2021-06-11Store the device tree node in the pcitag_t like we do on powerpc64 andiMark Kettenis
sparc64. For now, do this only for aplpcie(4) as we only need this functionality for Apple Silicon systems. ok patrick@
2021-06-02kernel: introduce per-CPU panic(9) message bufferscheloha
Add a 512-byte buffer (ci_panicbuf) to each cpu_info struct on each platform for use by panic(9). The first panic on a given CPU writes its message to this buffer. Subsequent panics on a given CPU print the panic message to the console but do not modify the buffer. This aids debugging in two cases: - If 2+ CPUs panic simultaneously there is no risk of garbled messages in the panic buffer. - If a CPU panics and then the operator causes a second panic while using ddb(4), the operator can still recall the first failure on a particular CPU. Misc. changes to support this bigger change: - Set panicstr atomically to identify the first CPU to reach panic(). - Tweak db_show_panic_cmd() to print all panic messages across all CPUs. Prefix the first panic with an asterisk ('*'). - Prefer db_printf() to printf() during a panic if we have it. Apparently it disturbs less global state. - On amd64, tweak fault() to write the local panic buffer. This needs more work. Prompted by bluhm@ and deraadt@. Mostly written by deraadt@. Discussed with bluhm@, deraadt@ and kettenis@. Borne from a discussion on tech@ about making panic(9) more MP-safe: https://marc.info/?l=openbsd-tech&m=162086462316143&w=2 ok kettenis@, visa@, bluhm@, deraadt@
2021-05-17Rename some MD structs by giving them an architecture-neutral name inMark Kettenis
preparation for sharing PCIe host bridge drivers between arm64 and riscv64. ok mpi@, mlarkin@, patrick@
2021-05-16ansiJonathan Gray
2021-05-15Use intr_enable()/int_disable()/intr_restore() instead ofMark Kettenis
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove the latter interfaces. While there move a few malloc(9) and free(9) calls to run with interrupts enabled. ok patrick@
2021-05-01Remove NetBSDisms that crept into the arm64 version of this file.Mark Kettenis
ok gnezdo@
2021-03-27Make sure that all CPUs end up with the same bits set in SCTLR_EL1.Mark Kettenis
Do this by clearing all the bits marked RES0 and set all the bits marked RES1 for the ARMv8.0. Any optional features introduced in later revisions of the architecture (such as PAN) will be enabled after SCTLR_EL1 is initialized. ok patrick@
2021-03-27Add ARMv8.5 instruction set related CPU features.Mark Kettenis
ok patrick@
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