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AgeCommit message (Collapse)Author
2017-05-21Add dwmmc(4), a driver for the Synopsis Designware SD/MMC controller as foundMark Kettenis
on various Rockchip SoCs. This is still WIP. Next steps will be to get rid of various busy-wait loops and add DMA support.
2017-05-18AAPCS64 requires 16 byte stack alignment. Set the bits in the systemJonathan Gray
control register to enable alignment fault exceptions if the stack pointer is not correctly aligned when used as a base address in load or store instructions. drahn@ pointed out that FreeBSD made this change in svn rev 295270 and believes we should do the same.
2017-05-12Make atomic.h ready to be included in userland.Martin Pieuchot
- keep setbits/clearbits and virtio barriers inside _KERNEL ok dlg@, kettenis@
2017-05-10Remove pmep_pa_is_mem(). Instead create write-back cachable mappings byMark Kettenis
default an require callers of pmap_enter() and require pmap_kenter_pa() to explicitly request uncached mappings by passing the PMAP_NOCACHE flag in the low bits of the physical address like we do on other architectures. ok drahn@, patrick@
2017-05-09Enable dwge(4). If the network hardware is initialized by U-Boot, theMark Kettenis
Gigabit Ethernet port on the FireFly-RK3399 actually works!
2017-05-08add a BUS_DMA_64BIT flag to bus_dma on all our archs.David Gwynne
this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
2017-05-07Pass the address of the EFI system table and the EFI memory map throughMark Kettenis
properties in the /chosen node of the FDT. The properties match the ones used by Linux (see Documentation/arm/uefi.txt in the Linux kernel source tree) but with the "linux," prefix replaced by "openbsd,". ok jmatthew@, tom@
2017-05-06Add rkgpio(4), a driver to handle GPIOs on Rockchip SoCs.Mark Kettenis
2017-05-06Print full MIDR for CPUs that can't be identified.Mark Kettenis
ok jsg@
2017-05-06Now that we have a table of Cavium part numbers add the part number forJonathan Gray
Broadcom's Vulcan design with a Cavium implementer code (ThunderX2 T99/CN99xx). Suggested by kettenis@
2017-05-05Add rkpinctrl(4), a driver to configure pins on Rockchip SoCs. For now,Mark Kettenis
only the RK3399 is supported.
2017-05-05Add glue to attach SDHC compliant controllers using the FDT. This makesMark Kettenis
the eMMC controller on the Rockchip RK3399 work.
2017-05-05Add the missing cache flush operations for non-coherent mappings.Mark Kettenis
ok jsg@, patrick@
2017-05-04Recognize various Cavium ThunderX cores.Mark Kettenis
ok patrick@
2017-05-03Bring boot() in line with our other architectures.Mark Kettenis
ok mpi@, deraadt@
2017-05-02Zap silly diagnostic reboot message.Mark Kettenis
ok bmercer@, deraadt@
2017-05-02The pmap_vp_enter() function should only ever be called for userland mappingsMark Kettenis
with the PMAP_CANFAIL flag set. Use PR_NOWAIT in the pool_get() calls such that we return an error instead of deadlocking if we cannot allocate a pool item. ok drahn@ (who says this is needed for SMP as well)
2017-05-02Remove check for compatible property here as well.Mark Kettenis
2017-04-30Fix priority handling. The interrupt priority registers expose the full rangeMark Kettenis
of priorities available in secure mode (minimally 32). For non-secure interrupts we need to make sure the top bit is set and shift our interrupt priority level into the remaining bits. The priority mask register on the other hand only exposes the priority levels available to the mode from which it is accessed. So when accessed from non-secure mode, we need to shift our interrupt priority level by a different amount. Also set the binary point register to zero to make sure the maximum number of available bits are used for the priority group and priority masking actually works as expected. This makes the FireFly-RK3399 boot multi-user with the root filesystem on USB. ok drahn@
2017-04-30Add rkclock(4), a driver for the Rockchip RK3399 clocks.Mark Kettenis
2017-04-30Rename Debugger() into db_enter().Martin Pieuchot
Using a name with the 'db_' prefix makes it invisible from the dynamic profiler. ok deraadt@, kettenis@, visa@
2017-04-30Add xhci@fdt, and move ehci(4) from the sunxi block to the generic block.Mark Kettenis
2017-04-30Add rkgrf(4), a driver that makes the "generic register file" of the RockchipMark Kettenis
RK3399 available to other drivers through the regmap interface.
2017-04-30Make early attrbute work here as well. Remove unreachable panic while there.Mark Kettenis
ok visa@
2017-04-30Unifdef KGDB.Martin Pieuchot
It doesn't compile und hasn't been working during the last decade. ok kettenis@, deraadt@
2017-04-29Decrement ci_idepth on all returns from agintc_irq_handler().Mark Kettenis
2017-04-29Add agintc(4), a driver for interrupt controllers conforming to ARM'sMark Kettenis
generic interrupt controller architecture specification v3/4. The hard work was done by drahn@, I just cleaned it up a bit and fixed a couple of bugs. ok patrick@, drahn@
2017-04-29Move the userret() call out of data_abort() and simply call it just before weMark Kettenis
return from do_el0_sync(). Prevents future mistakes.
2017-04-29Call refreshcreds() in ast() since we may get there without going throughMark Kettenis
do_el0_sync() or mi_syscall().
2017-04-29store cpu model information in the buffer used by the hw.model sysctlJonathan Gray
ok kettenis@
2017-04-27Use (32-bit) word-sized access in the a4x bus space routine even if onlyMark Kettenis
a byte or a half-word is needed. Certain implementations of the Synopsis Designware copy-and-paste logic blocks don't respond to transactions that are smaller than a word. Fixes the serial console on boards with a Rockchip RK3288.
2017-04-27Add code to identify the CPUs on arm64 systems. The primary CPU is attachedMark Kettenis
and identified early on. For the secondary CPUs this happens late, such that the drivers we need to spin up CPUs, such as psci(4), will be available. This also fixes some code in simplebus(4) where the return value of OF_getprop() was not properly checked. Heavily based on an earlier diff from drahn@. ok drahn@, jsg@
2017-04-24Stop dumping registers on "normal" segmentation faults. Do print the contentsMark Kettenis
of the esr_el1 register for unhandled userland exceptions (and continue to dump the registers in that case). Handle breakpoint traps and make sure we call refreshcreds() on userland traps. ok jsg@
2017-04-20Hook up mutex(9) to witness(4).Visa Hankala
2017-04-16Define EXT_IMPLICIT_NBIT like we do on sparc64 and mips64. Makes vaiousMark Kettenis
long double math stuff (including printf) actually work. While there remove 'struct ieee_ldouble', which isn't defined on other architectures. ok deraadt@
2017-04-15The tlb flushes in pmap_set_{l1,l2,l3} use ranges that don't fully make sense.Mark Kettenis
But those tlb flushes shouldn't be necessary anyway, so simply remove them. Simplify the tlb flushing code now that we no longer flush ranges, and revive the branch that doesn't flush a specific ASID for the kernel pmap since its mappings are global. ok patrick@, visa@
2017-04-13A little bit more trivial cleanup.Mark Kettenis
2017-04-13Use the non-interrupt-safe pool allocator for the vp pool to avoid runninngMark Kettenis
out of kva in the kmem_map. Avoids a hang when spawning a lot of processes.
2017-04-13Provide mips64 with kernel-facing TCB_{GET,SET} macros that store itPhilip Guenther
in struct mdproc. With that, all archs have those and the __HAVE_MD_TCB macro can be unifdef'ed as always defined. ok kettenis@ visa@ jsing@
2017-04-11Recognize break conditions and enter ddb if ddb.console is set.Mark Kettenis
ok visa@, deraadt@
2017-04-11Revise 'struct fpreg' and dump floating-point register in core dumps. AlsoMark Kettenis
reset the floating-point register state upon exec. ok guenther@
2017-04-08For legacy interrupt use the tag of the topmost bridge to establish theMark Kettenis
interrupt. We already correctly swizzle the pin. ok patrick@
2017-04-08Bring over the changes I made to the armv7 version of this driver such thatMark Kettenis
interrupts are correctly routed to the boot cpu if that isn't the one connected to CPU interface zero on the interrupt controller. ok patrick@
2017-04-04Cleanup the code further. Get rid of the remaining C++-style comments,Mark Kettenis
remove some debug printfs, get rid of STATIC and __inline defines and remove a bit more unused code. ok drahn@, visa@
2017-04-02On ARMv8, the translation table walk is fully coherent so there is noMark Kettenis
reason to explicitly flush the cache before invalidating the TLB. The barrier that is included in out TLB flushing code should be enough to guarantee that the TLB walking hardware sees the updated page table contents, so the explicit barriers can go as well. Sanitize the code immediately surrounding the removed bits while I'm there. Tested by jsg@, ok drahn@, visa@
2017-03-28Add an instruction synchronisation barrier instruction after changingJonathan Gray
the vfp state via cpacr_el1. This matches the advice given in the "Synchronization requirements for system registers" section of the ARMv8 ARM. Without this an overdrive 1000 with A1120 (Cortex A57 r1p2) reliably triggers "panic: VFP exception in the kernel" when init(8) is run. ok drahn@ kettenis@
2017-03-28Previous W^X diff only changed the access permissions in the bootstrap pageMark Kettenis
tables. We need to set them in the final kernel page tables as well. ok visa@
2017-03-26Switch arm64 generic timer to use virtual timer instead of physicalDale Rahn
timer. virtual timer will always be present where physical timer may be disabled by hypervisor. Other OSes use virtual timer. ok patrick@
2017-03-24Simplify ASID allocation code considerably by allocating an ASID up frontMark Kettenis
when a pmap is created and freeing it when the pmap is destroyed. This diff relies on the fill 16-bit ASID space being implemented in the processor. While this is documented as an optional feature in the ARMv8 architecture reference manual, all ARMv8 processors seen in the wild so far implement the full 16-bit space. This change incorporates changes by drahn@ to allocate an empty page table for the lower half of the address space for the kernel. ok drahn@, patrick@
2017-03-22Implement kernel W^X for arm64. For this purpose align the different segmentsMark Kettenis
containing .text, .rodata and .data/.bss at 2MB boundaries and set the appropriate access permissions on the block translations. ok patrick@
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