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ok tb@, jca@
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armv7 we inherited the mechanism to manually modify the kernel symbol
table to change the value of esym. We don't use this, but instead use
the virtual address that is passed to the kernel. This change makes us
only work on and hand out physical addresses. Bump the efiboot version
to make this ABI change more visible.
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to make sure to pass the current mapkey to prove EFI that we know the
current memory map and its constraints. Otherwise EFI can choose to
only partially exit until we pass the correct key. As we already use
the memory map to allocate memory for the kernel, split the previous
function into one simply retrieving the table and another one who uses
the map to allocate memory. At some point it would be nice to actually
pass the table to the kernel since its data is more reliable than the
FDT only. While there, sync a bit of style with the amd64 version.
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leaving out the size, so that
ELFNAME2(exec,makecmds)
becomes
exec_elf_makecmds
instead of
exec_elf{32,64}_makecmds
and then delete the ELFNAME2() and ELFNAMEEND() macros.
Move the prototypes for functions local to exec_elf.c to there from
exec_elf.h.
Simplify the SMALL_KERNEL conditionals around the ELF coredump code.
Change exec_conf.c to use the size-generic names and macros
Remove exec_elf{32,64}.c and just build exec_elf.c; delete the
_KERN_DO_ELF and _KERN_DO_ELF64 #defines.
ok jca@, encouragement from deraadt@ and tom@
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we need to make sure to clean the data and invalidate the instruction
cache upon entering a page with pmap_enter(). Since it is possible
that pmap_enter() does not directly enter the page, we need to do the
same dance in the pmap fault fixup code. Every new writeable mapping
or write removes a page's flag to mark it unflushed. The next time
pmap_enter() is called or a fault happens on that VA, it has to be
flushed and invalidated again. This was heavily discussed with Dale
Rahn.
On the Pine64 and Raspberry Pi 3 we have been very lucky to not run
into any cache issues, especially with the instruction cache. The
AMD Seattle seems to be a different kind of beast where we actually
have to care about these things. This finally brings the machine
into userland.
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pagetables as well. Also replace the number for write-back with a proper
define.
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true. Instead, unless overwritten by the device tree, we should ask the
generic timer for its frequency. This fixes time on my AMD Seattle and
should improve time management on QEMU as well.
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these currently to 255. Thus making it impossible to use higher IRQs
than that. The AMD Seattle SoC though seems to provide 448 IRQs, which
is kind of out of bounds, so raise them to the proper values. This
makes interrupts work on that machine.
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into separate functions. This makes them reusable from other parts in
the kernel. Assembly and header are taken from FreeBSD, but modified
to fit our requirements and with some unnecessary stuff removed. While
there remove micro optimization for uniprocessor kernels.
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other archs.
ok patrick@
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upon free don't try to convert it from virtual to physical again.
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for cortex-a57.
ok patrick@
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on the octeon one.
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the caches' contents, we lose data about the freshly copied and
created kernel. This leads to bootup failures. Make sure to
clean the caches to make sure that the data is in memory before
we turn off the MMU.
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their memory mapped above 39 bits of address space. Since our pmap is
configured to use a 3 level pagetable userland we need to reconfigure
the size back to 39 bits as soon are in virtual address space and have
finished using the FDT via the 1:1 map.
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only need a data cache write-back to PoU (Point of Unification) to
make changes to the pagetables visible. Interestingly enough, this
does not seem to work on the AMD hardware. Instead we need to flush
to PoC (Point of Coherence), which essentially means flush to memory.
Surprisingly even FreeBSD flushes their pagetable changes to PoC, and
they have done that since the code was first imported. Until we find
out whether this is a software bug or just completely expected, switch
us to flushing to PoC as well. This makes my AMD machine behave.
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Prompted by jsg@
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but simply at 2M boundary. This might have been a requirement from
armv7, but it's not true for arm64. This also helps reduce memory
holes below the kernel.
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want to start caching that value somewhere though.
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With feedback from Dale Rahn, ok patrick@.
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a L1 pagetable. Needed for machines that need 4 level pagetables
on bootup.
From FreeBSD
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to the physical timers at EL1.
From FreeBSD
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From FreeBSD
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of pagetables to bootstrap machines with physical memory mapped outside
of a 39 bits address space.
From FreeBSD
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it. Otherwise we might truncate physical addresses.
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address. PTE_RPGN only returns the physical bits that can be used,
thus truncating virtual addresses, specifically in kernel address
space.
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kernel in, and not just use some memory address that we found in
the table.
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uneeded include. Remove the include and move to MI fdt directory.
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kernel makefiles, that are using -ffreestanding already, with the amd64 one.
Other architectures will follow later.
ok jca@, visa@
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not only 11 registers.
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kernel. Since those are only used by ddb, guard them with DDB.
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ok patrick@
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ok jsg@
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been removed years ago.
From miod
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ok kettenis@ patrick@
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Based on code written by patrick@
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ok kettenis@ patrick@
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mapping than the kernel.
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ok kettenis@
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function, we need another indirection for esym. The address of
esym is simply the address of the variable. But in the case of
esym we want to read and modify its value.
ok kettenis@
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the end of BSS by 64-bit and not 32-bit.
With and ok kettenis@
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