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AgeCommit message (Collapse)Author
2016-08-19Start using to XN flag to enforce that mappings without PROT_EXEC areMark Kettenis
non-executable. ok visa@, deraadt@
2016-08-19Mark device memory as execute-never to prevent a speculative instruction fetchMark Kettenis
to access it.
2016-08-19Adjust the definitions of L1_S_COHERENT_v7, L2_L_COHERENT_v7 andMark Kettenis
L2_S_COHERENT_v7 such that bus_dmamap_sync(9) avoids unnecessary cache flushes again for DMA'able memory mapped with the BUS_DMA_COHERENT flag. I broke this in pmap7.c rev 1.35. ok tom@
2016-08-19Use Access Flag to do page reference emulation.Mark Kettenis
ok visa@
2016-08-18Separate out the Access Flag bit from the Access Permission bits in theMark Kettenis
armv7 pmap. ok tom@
2016-08-16remove #define for /dev/mem minors. let the raw magic of the hardcodedTed Unangst
numbers serve as a warning not to touch them.
2016-08-16replace hand rolled tsleep physlock with rwlock. ok mlarkinTed Unangst
2016-08-16Fix typo/inconsistensy where L1_S_DOMAIN was used instead of L1_C_DOMAIN.Mark Kettenis
These are functionally equivolent so it didn't matter and the resulting code doesn't change.
2016-08-15normalize some commentsTed Unangst
2016-08-15Don't take shortcuts cleaning/invalidating the caches. The Cortex-A7 and mostMark Kettenis
other ARMv7 CPUs have a L2 cache that is larger than 32KB. And some of those even have L1 caches larger than that. So bailing out after 32KB will leave the cache partially dirty. Fixes the SATA problems on Allwinner A20 based boards. ok patrick@
2016-08-14Remove code for Intel 80219/80321 xscale processors used by armish.Jonathan Gray
Generic xscale support and support for pxa2x0 used by zaurus remains.
2016-08-14Fix setting the SMP bit in the Auxiliary Control Register. The old code wasMark Kettenis
toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP bit is essential since without it the CPU doesn't actually use its caches. The SMP bit supposed to be set before turning on the caches and the MMU, so move the setting of the Auxiliary Control Register before setting the System Control Register. ok jsg@
2016-08-14Allow a bus_dmamap_sync() of length zero.Mark Kettenis
ok tedu@
2016-08-11The ARMv7 ARM says that the TLB may hold translation table entries at anyMark Kettenis
level of the translation table, including entries that point to further levels of the tables. This means that we have to do a TLB flush whenever we invalidate an L1 slot too. Doing so fixes the pmap_fault_fixup issue on Cortex-A7 processors.
2016-08-10Add defines for the Access Flag as found on armv7. Fix definition of theMark Kettenis
non Global bit Small page desciptions. iConsistently name the S-bit Sharable in comments.
2016-08-10Shuffle armv7 access permission bits around to something that is compatibleMark Kettenis
with setting the Access Flag Enable bit in the System Control Register. The new settings mean that read-only userland pages are no longer writable by the kernel, which is a good thing. Set the Access Flag Enable bit. ok patrick@
2016-08-10Dynamically attach agtimer(4). Since agtimer(4) also provides the delay()Mark Kettenis
function for platforms that have it, rework the code a bit such that it can be used before agtimer(4) attaches. Introduce a new agtimer_init() function that checks whether the CPU implements the Generic Timer feature and switches to agtimer_delay() if that feature is present. Call this function from the generic platform initialization code. ok jsg@
2016-08-10On armv7 we put the vector page up high and never have to bother switching it.Mark Kettenis
Remove the code to do so from cpuswitch(). ok guenther@
2016-08-09The page tables are cached now, and given the significant speedup, IMark Kettenis
don't think we'll ever go back. So let's ditch the code that tries to check and patch up incorrect memory attributes. Also realize that pmap_clean_page(pg, FALSE) doesn't do anything anymore so remove those calls and drop the 2nd argument from pmap_clean_page(pg, TRUE) calls. Last but not least, get rid of pmap_pte_init_generic() here. The only useful thing it did was setting pmap_copy_page_func() and pmap_zero_page_func(). This diff should not introduce any change in behaviour. ok visa@
2016-08-08Move the cpu_setup() call to the end of initarm(). On Cortex-A53 processorsMark Kettenis
atomic instructions don't work unless the data cache is enabled. This happens in cpu_setup(), but that gets currently called from cpu_startup() which runs after a number of kernel subsystems have been initialized. Since some of these subsystems use locks, which need atomic instructions, we fault on Cortex-A53. Since at the end of initarm() we're done setting up the pmap and initializing other low-level sense, calling cpu_setup() here makes much more sense. Remove setting up proc0paddr as well from cpu_startup(), since that already happens in initarm(). Tested on zaurus by deraadt@. ok jsg@, patrick@
2016-08-08Mapping non-cachable memory as cachable and subsequently changing the mappingMark Kettenis
to non-cachable is retarded. Fix this by introducing PMAP_NOCACHE and PMAP_DEVICE flags that can be or'ed into the physical address passed to pmap_kenter(9), like we have on many of our other architectures. This way we can also properly distinguish between device memory and normal (non-cachable) memory. ok visa@
2016-08-08ARMv7 data caches are "effectively" PIPT. This means there is in generalMark Kettenis
no need to clean and/or invalidate cached pages. So remove most of the cache cleaning and invalidation from the pmap. We still need to synchronize the instruction cache with the data cache in various places though. And we also need to make sure that we clean and invalidate when we make a page non-cachable. Tested by Daniel Bolgheroni, mglocker@ and jsg@. on Cortex-A8 and myself on Cortex-A9. ok visa@
2016-08-07Add XOR cookies for lr and sp. Stop saving/restoring r12 to/from the jmpbuf.Philip Guenther
Switch from calling obsolete sig{block,setmask} to directly using the sigprocmask syscall. ok deraadt@ kettenis@
2016-08-06Always allocate intrhand with M_WAITOK.Patrick Wildt
Requested by and ok kettenis@
2016-08-06Extend the interrupt controller API with a disestablish functionality.Patrick Wildt
This will be helpful for interrupt combiner that need to re-establish their main interrupt when their interrupt priorities change. ok kettenis@
2016-08-06Build ofw_pinctrl.o and ofw_gpio.o on armv7. The latters here from theMark Kettenis
generic arm files list. There is no point in building it on armish or zaurus. ok patrick@
2016-08-06Put page tables in normal cachable memory on armv7. Check if the MMU walksMark Kettenis
the page tables coherently and also skip flushing modified ptes out of the cache in that case. Speeds up building a kernel with a factor of two on Cortex-A9 (tested by me) and Cortex-A8 (tested by mglocker@). ok patrick@
2016-08-06Rework ampintc's interrupt disestablish code to make it actually doPatrick Wildt
its job. Recalculate the mask after the handler is taken from the list to properly set the new prioritization. ok kettenis@
2016-08-06Set up the fdt attach args for devices that attach directly to mainbusJonathan Gray
the same way as for those that attach to simplebus. ok kettenis@ patrick@
2016-08-05Replace inappropriate use of CP15_CNTPCT with CP_DCCIMVAC.Mark Kettenis
No binary change.
2016-08-05Unmask the timer output signal for real.Mark Kettenis
ok patrick@, jsg@
2016-08-04Dynamically attach ampintc(4) and make it register itself as an interruptMark Kettenis
controller. Switch all i.MX6 devices over to the new FDT-aware interrupt establish API and enable imxgpc(4). This may break other platforms that use ampintc(4) as their interrupt controller. We will fix this as soon as possible by switching them over to the new interrupt establish API as well. This also removes the hack in fec(4) to avoid the gpio-based interrupt workaround. This commit is an essential step on the road to fix that issue properly. ok patrick@, jsg@
2016-08-04Add support for pre-registering interrupts. This allows device drivers toMark Kettenis
establish interrupts before their interrupt controller attaches, solving dependency problems in various device trees. Also add support for handing interrupt handlers over to parent interrupt controllers. ok jsg@ patrick@ (on an earlier diff)
2016-08-03Simplify the way we handle TLB flushes. Since ARMv7 effectively has aMark Kettenis
unified TLB there is not much point in optimizing TLB flushing for pages that have never been executable. The only difference is a flush of the branch predictor and even that isn't necessary anymore on all but the oldest Cortex cores. ok patrick@
2016-08-03The ARMv7 architecture deprecates the separate Instruction and Data TLBMark Kettenis
maintanenance instruction and recommends to only use the instructions that operate on the unified TLB. Those instructions will flush both TLBs on implementations that still have separate Instruction and Data TLBs. Switch the TLB maintenance primitives over to use those. This allows us to reduce the number of primitives on armv7. We still keep separate "ID" and "D" variants as we still have to flush the branch predictor when changing the mappings of pages that contain instructions. ok jsg@
2016-08-01bring the light of ansi to a few more filesTed Unangst
2016-07-31Remove devmap stuff which is unused on armv7.Mark Kettenis
ok patrick@
2016-07-31According to te armv7 ARM TLB entries that caused a Permission fault mightMark Kettenis
be held in the TLB. On top of that valid page table entries might be speculatively loaded into the TLB. As a result we need to flush TLB entries even when the page in question has not been referenced. Fixes pmap_fault_fixup messages on Cortex-A53, and presumably also on Cortex-A7. ok patrick@, guenther@
2016-07-31Use ansi style function declarations. No binary change.Jonathan Gray
From Robert Tate.
2016-07-31Recognise Cortex A35 and Cortex A73.Jonathan Gray
2016-07-31Instead of testing MIDR values for every model of Cortex processor checkJonathan Gray
MMFR0 for an ARMv7 VMSA MMU that can handle short descriptors when setting ARMv7 function pointers. ARMv8 in AArch32 mode is documented to set the same bits. ok patrick@
2016-07-29Only flush the virtual page if it was actually mapped. OtherwisePatrick Wildt
we will run into translation faults. ok tom@
2016-07-27Remove a feature to re-use existing early bootstrap mappings. ThisPatrick Wildt
allowed you to pass a virtual address, which you received from an early bootstrap mapping, as physical address to bus_space_map(9). It breaks bus_space_map(9) for peripherals that are after 0xC0000000, as it assumes that everything after that address cannot be a real peripheral. But that's wrong. It does not make sense to pass a virtual address to bus_space_map(9) anyway, so just get rid of this whole "feature". ok kettenis@
2016-07-27When pmap_page_remove() is called by UVM, a physical page is to bePatrick Wildt
removed from pmaps it currently is in. To check if a virtual address pointing to that physical page has been mapped, the code uses the l2pte_valid() function. Unfortunately there is a difference between being valid and the PTE being zero. If a page is mapped but has never been accessed, it will be non-zero but invalid. In that case the PTE for that virtual address will not be zeroed and the virtual address will be removed from the vm page struct. The next time someone tries to map a page to that virtual address, other pmap code will consider the virtual address to be already mapped, even though that assumption is completely wrong. To make sure this does not happen, check the PTE for zero. This way the PTE will be zeroed correctly. The check for zero is how other ARM pmap code also handles this issue. ok kettenis@ tom@
2016-07-27Instead of passing the raw reg property to simplebus nodes,Patrick Wildt
pass a pre-processed array of fdt_reg structs. This means that the drivers don't have to understand the cell properties themselves but can rely on the 64-bit addr/size pairs. ok kettenis@
2016-07-19Remove what appears to be a copy-paste error setting cur_ttbTom Cosgrove
in pmap_free_l1(). from aalm@ - thanks ok patrick@
2016-07-18Don't need a separate flags variable in armv7 pmap_clean_page() -Tom Cosgrove
just use the pv_flags. ('Twas a copy-paste from arm's pmap_clean_page(), which did need it.) Also remove even less used flags variable from pmap_page_remove(). First part from a diff from aalm@ - thanks ok kettenis@ "looks good" patrick@
2016-07-18Some SoCs have a ranges property set in their device trees. This canPatrick Wildt
be used to translate one memory address to another. Currently we just pass the child's memory address to bus space map. If one of the parent busses implements a ranges property, the child's address property is not the real address. This change hooks up a bus space map function that is aware of the ranges property and translates the addresses if needed. ok kettenis@ looks fine jsg@
2016-07-16Remove unused function process_frame() from arm_machdep.cTom Cosgrove
ok jsg@
2016-07-13The "#address-cells" and "#size-cells" properties define the sizePatrick Wildt
of the memory address and length information. The root node passes this information down to the children and it can be overwritten by other nodes inbetween. Pass these properties as part of the fdt attach args, so that we can grab that information quickly inside the drivers. ok kettenis@
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