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For the possibility of sleeping, the first two flags are UVM_PLA_WAITOK
and UVM_PLA_NOWAIT. It is an error not to show intention, so assert that
one of the two is provided. Switch over every caller in the tree to
using the appropriate flag.
ok art@, ariane@
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addresses against PAGE0 information, instead than only the BAR mapping
sti region #0; on Visualize FXe, PAGE0 will point to another BAR and we would
not recognize the display as the console device.
Tested on Visualize FX4 (on C240), Visualize EG (on B1000) and Visualize FXe
(on B2000).
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MD code would free resources that couldn't be freed until we were no
longer running in that processor. However, it's is unused on all
architectures since mikeb@'s tss changes on x86 earlier in the year.
ok miod@
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levels. This will allow for platforms where soft interrupt levels do not
map to real hardware interrupt levels to have soft ipl values overlapping
hard ipl values without breaking spl asserts.
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ok miod@
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try to be smart for the address range, uvm_pglistalloc() is smart enough
nowadays.
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ok miod@
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corruption on PA-RISC 2.0 systems (and there are very few PA-RISC 1.1
systems that support more than 2GB).
ok miod@
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run(4) has been reported to work on sparc64 by Maxim Belooussov so I'm
pretty confident that it works on all arches.
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already been hit by the running timer; this happens very often on oosiop-based
machines, due to these machines being among the slowest hppa, and oosiop
being interrupt greedy. Unfortunately, when this happened, one had to wait
for the timer to wrap, which would take up to 128 seconds on the 33MHz
machines.
Also, invoke hardclock() as many times as necessary if it turns out that
we had to delay the interrupt 1/hz seconds to avoid the aforementioned
wrap problem.
With help from kettenis@; ok kettenis@
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information. This is preliminary work to help eventually supporting the
dual-head ELK model.
Also split the initialization code in several routines, this makes the
code easier to read, and makes it easier to release resources upon failure.
Finally, don't forget to clear the text planes on non-console displays
when initializing.
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single trap code for alignment and protection faults, so we have to
figure out which kind of problem we are facing.
ok kettenis@
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as PDC will lie to us pretending it did while it didn't.
ok kettenis@
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and allow asp interrupts to pass through even if not revision 0.
ok kettenis@
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reserved memory on alpha and hppa on its own line (as done on sgi).
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more than one flex ``tile'', when the first one is already mapped.
Some sti(4) devices have such requests.
ok kettenis@
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What happened was that the output of mkdep was fed to a sed expression
that trimmed a bit more than required and also failed to work when
attempting to do make depend with pcc.
Example:
genassym_c.o: /tmp/genassym.whatever ../../../../../sys/param.h \
was changed to:
assym.h: \
but what was intended was:
assym.h: ../../../../../sys/param.h \
For the pcc -M output things were a bit different and after the make
depend the genassym entry would still remain and make would fail. This
affected all platforms except amd64 and sgi.
Okay miod@.
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(if the stge(4) entry is commented, so is the ipgphy(4) entry then).
this allows ipgphy0 to attach to my stge0, which has a IC+ 1000A chip
discussed with and ok jsg@, ok dlg@
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and even then it didn't work. we have higher standards than this.
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day when this is useful.
mostly macro magic that does nothing. only actually useful on amd64 for now, compliments of art.
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protected by __ISO_C_VISIBLE > 1999. With a little help from miod@.
ok miod@
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which are uniform for the profclock on each cpu in a SMP system (but using
a different seed for each cpu). on all cpus, avoid seeding with a value out
of the [0, 2^31-1] range (since that is not stable)
ok kettenis drahn
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This should take care of the simpler ones (i.e., timeout values of
integer multiples of hz).
ok krw@, art@
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anything special to prod a cpu to leave the idle loop in signotify.
powerpc, i386, amd64 and sparc64 will follow soon so that everyone has
the same interface to wake an idling cpu.
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For now, sparc64 is arbitrarily set to 256 (only architecture that didn't have
a practical limit in the code on the number of cpus).
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ok miod@
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instruction cache, also purge TLB entries. The PA-RISC 2.0
architecture says that cache lines may be moved in when a translation
exists even if no access is done. This might have been hurting us
badly since we create illegal aliases in pmap_zero_page() and
pmap_copy_page().
Probably not perfect yet, and perhaps a bit of a sledgehammer, but it
makes PA-RISC 2.0 machines stable again.
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for us if needed.
ok art@ kettenis@
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remainder to prevent covering kernel data.
ok miod@
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- provide proper dtoa locks
- use the real strtof implementation
- add strtold, __hdtoa, __hldtoa
- add %a/%A support
- don't lose precision in printf, don't round to double anymore
- implement extended-precision versions of libc functions: fpclassify,
isnan, isinf, signbit, isnormal, isfinite, now that the ieee.h is
fixed
- separate vax versions of strtof, and __hdtoa
- add complex math support. added functions: cacos, casin, catan,
ccos, csin, ctan, cacosh, casinh, catanh, ccosh, csinh, ctanh, cexp,
clog, cabs, cpow, csqrt, carg, cimag, conj, cproj, creal, cacosf,
casinf, catanf, ccosf, csinf, ctanf, cacoshf, casinhf, catanhf,
ccoshf, csinhf, ctanhf, cexpf, clogf, cabsf, cpowf, csqrtf, cargf,
cimagf, conjf, cprojf, crealf
- add fdim, fmax, fmin
- add log2. (adapted implementation e_log.c. could be more acruate
& faster, but it's good enough for now)
- remove wrappers & cruft in libm, supposed to work-around mistakes
in SVID, etc.; use ieee versions. fixes issues in python 2.6 for
djm@
- make _digittoint static
- proper definitions for i386, and amd64 in ieee.h
- sh, powerpc don't really have extended-precision
- add missing definitions for mips64 (quad), m{6,8}k (96-bit) float.h
for LDBL_*
- merge lead to frac for m{6,8}k, for gdtoa to work properly
- add FRAC*BITS & EXT_TO_ARRAY32 definitions in ieee.h, for hdtoa&ldtoa
to use
- add EXT_IMPLICIT_NBIT definition, which indicates implicit
normalization bit
- add regression tests for libc: fpclassify and printf
- arith.h & gd_qnan.h definitions
- update ieee.h: hppa doesn't have quad-precision, hppa64 does
- add missing prototypes to gdtoaimp
- on 64-bit platforms make sure gdtoa doesn't use a long when it
really wants an int
- etc., what i may have forgotten...
- bump libm major, due to removed&changed symbols
- no libc bump, since this is riding on djm's libc major crank from
a day ago
discussed with / requested by / testing theo, sthen@, djm@, jsg@,
merdely@, jsing@, tedu@, brad@, jakemsr@, and others.
looks good to millert@
parts of the diff ok kettenis@
this commit does not include:
- man page changes
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when switching from gcc 2.95, if not forever.
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address space. The space between PAGE_SIZE and the non-pie fixed link
address creates no mmap pressure so use that space for PIE. However on
hppa the non-pie fixed link address is PAGE_SIZE so just use a small range
for PIE to minimize mmap pressure.
okay miod@
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in the MI code.
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dino_intr_map(); rather than adding the missing cast, make the intent of
the code clearer by explicitenly testing for PCI_INTERRUPT_LINE being ff.
While there, enable the out-of-extent-range checks in dino_memmap() and
dino_memalloc() even if no option DEBUG, but return failure instead of
panicing.
discussed with and ok kettenis@ marco@
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after it was published. In particular, they changed the maximum cache
aliasing boundary from 1MB to 16MB.
It turns that on the PA-8700 the aliasing boundary is actually 4MB
(reported as such by the firmware at least). There are some comments
in the Linux code that suggest that HP never actually built PA-RISC
CPUs with an 8MB or 16MB aliasing boundary.
So raise the aliasing boundary to 4MB. This fixes the weird ps(1) problem
where it didn't print its own arguments correctly.
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- math.h shouldn't define FLT_EVAL_METHOD, but float.h should (per
C99). remove from math.h, and add proper definitions in float.h
ok millert@
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ok marco@ no objection miod@ need this for regress djm@ no objection krw@
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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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gsckbd; the former will cause a proper translation page to be selected by
the keyboard.
Because of this, we no longer depend on the page the keyboard is left in
by the PDC (page 2 for all machines but the PrecisionBook, which is in
page 3), and there is no longer any need to use separate keyboard maps.
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and signal handlers.
ok kettenis@
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and signal handlers.
ok kettenis@
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