| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2002-11-19 | a typo; from David Krause | Michael Shalayeff | |
| 2002-11-14 | get more use of the shadowed regs | Michael Shalayeff | |
| 2002-11-12 | build program on hppa only | Theo de Raadt | |
| 2002-11-10 | some creamy filling | Michael Shalayeff | |
| 2002-11-08 | absolutely no need to save the fpu state before rewriting the fpu regs, just ↵ | Michael Shalayeff | |
| reset the curpcb and force a reload | |||
| 2002-11-08 | hmm, todos seem to be unapplicable no more | Michael Shalayeff | |
| 2002-11-08 | only reset the pending fpu exceptions on fork, not the rest of the fpu ↵ | Michael Shalayeff | |
| status reg | |||
| 2002-11-08 | Don't uvm_useracc the user sigcontext in sys_sigreturn and then access | Michael Shalayeff | |
| the user addresses directly from the kernel. copyin is faster and can correctly deal properly with mappings that uvm_useracc thinks are correct but will fault anyway (to figure out how to generate such mappings is left as en excercise for the reader). | |||
| 2002-11-07 | pmap_[de]activate() are not nops; w/ art@'s help | Michael Shalayeff | |
| 2002-11-07 | make pte flushing into a separate function, | Michael Shalayeff | |
| add a missing pte flush in page_remove(), removed a few dead debugs and ifdefs. use local vars inestead of long -> chains./ miod@ ok | |||
| 2002-11-01 | add a missing delay after printf on halt[-p], proper arg for a cold hook | Michael Shalayeff | |
| 2002-10-31 | lasi on j210 is in a strange place, add an exact entry for now, to be maybe ↵ | Michael Shalayeff | |
| rethought later once more such cases pile up; from millert@ | |||
| 2002-10-30 | as found on a 256m machine of millert@'s allocate pdes for the whole kernel ↵ | Michael Shalayeff | |
| virtual and do not bother (just four anyway); as a side work do not adjust addr,size since there is no need | |||
| 2002-10-29 | no need to restore shadowed reg, shaves 10% from runtime for tlb handler on ↵ | Michael Shalayeff | |
| pcxl, more on pcxs/pcxt due to conditional pte ref update; tested on pcxt,pcxl by me on pcxs by miod | |||
| 2002-10-28 | do not use asm for accessing the page tables since they are mapped now. | Michael Shalayeff | |
| fix ptp accounting and move diagnostic check in pmap_destroy() into a DIAGNOSTIC and it has not caught a one problem so far. when random-allocating the space ids use linear rehashing instead of a full new random which produces a better cache locality. miod@ ok | |||
| 2002-10-25 | fake intrcnt (for now) such that vmstat works (; | Michael Shalayeff | |
| 2002-10-25 | allow reading the direct mapped segment through the kmem | Michael Shalayeff | |
| 2002-10-24 | nlist does no aout no more, fuget about som too | Michael Shalayeff | |
| 2002-10-24 | use loadfile | Michael Shalayeff | |
| 2002-10-23 | Add a trivial va_copy() macro to all architectures but powerpc | Todd C. Miller | |
| (which I will leave for Dale since it needs special handling). From NetBSD (and same as sparc64). espie@ OK | |||
| 2002-10-22 | do not force single-user; pt out by fries@ | Michael Shalayeff | |
| 2002-10-21 | make an ieeefp regress pass; miod@ ok | Michael Shalayeff | |
| 2002-10-21 | try harder to sync in dmamap_sync | Michael Shalayeff | |
| 2002-10-18 | this is a precision architecture -- be more precise about fault types and in ↵ | Michael Shalayeff | |
| sigsegv deliveries; vm_ssize is in pages, apparently | |||
| 2002-10-17 | use shadows on fpu cxsw (and fix arg0 trashing), do not restore shadowed ↵ | Michael Shalayeff | |
| regs before rfir | |||
| 2002-10-17 | convert to use vm_page_md instead of pmap_physseg, make code smaller and ↵ | Michael Shalayeff | |
| simpler, indeed; after art's suggestion and by looking into his diffs oneyed | |||
| 2002-10-15 | a few missing options and pseudo-devs, noticed by miod@ and dhartmei@ | Michael Shalayeff | |
| 2002-10-15 | missing initmsgbuf(), noticed by miod@ | Michael Shalayeff | |
| 2002-10-13 | track the end of physmem for use in dmmem_alloc | Michael Shalayeff | |
| 2002-10-13 | split the scp/iscp/scb between the cache lines, make the leds blink better | Michael Shalayeff | |
| 2002-10-07 | this removes the functionality of adding allocated | Michael Shalayeff | |
| pages into the queue already containing allocated pages. breaks i386:setup_buffers() because of this. | |||
| 2002-10-07 | also s/_PSW/_PSL/ | Michael Shalayeff | |
| 2002-10-07 | s/PSW_/PSL_/ to match other archs | Michael Shalayeff | |
| 2002-10-07 | proper terminate the user stack on signal | Michael Shalayeff | |
| 2002-10-07 | on implementations w/ fpu included unimplemented instructions | Michael Shalayeff | |
| are signaled through the exception trap w/ invalid opcode marked instruction in the exception registers, not through the emulation trap (as long as the fpu is enabled, of course). parse emulation from the exception trap as well as the emulation trap and fix the dispatcher into usable condition. parse invalid op exception on trap and signal the user appropriately. reset the exception on exec and for child on fork. the later is appropriate since exceptions are delayed until next fpu instruction, which was in the parent indeed, let him get it. save parent's fpu context on fork before cipying it, if the parent owned the fpu. | |||
| 2002-10-06 | No more need to initialize the result list before uvm_pglistalloc. | Artur Grabowski | |
| 2002-10-01 | need fpemu for the gecko | Michael Shalayeff | |
| 2002-10-01 | a few missing generic devices | Michael Shalayeff | |
| 2002-09-23 | parisc level 0x10 is just an overclocked 0xe | Michael Shalayeff | |
| 2002-09-23 | make the leds blink (on those machines where we have 'em). | Michael Shalayeff | |
| simple logic is to light up the led in the intrhook and dim in the heartbeat always, makes a believable impression. upper four bits represent a cpu usage w/in the last Hz/8 made up from the cp_time[] times. | |||
| 2002-09-20 | this should have a cd@scsi on it | Michael Shalayeff | |
| 2002-09-20 | kill dangling space, line and a space in the tab | Michael Shalayeff | |
| 2002-09-20 | flush cpu state on read/write fpregs, force reload on write | Michael Shalayeff | |
| 2002-09-20 | gonna need cr10, aka ccr from the trapframe | Michael Shalayeff | |
| 2002-09-17 | print out the ccr and rctr | Michael Shalayeff | |
| 2002-09-17 | handle fpu exceptions properly, might use a regress, i guess | Michael Shalayeff | |
| 2002-09-16 | It's more convinient to spell convinient as ``convenient'', actually. | Miod Vallat | |
| 2002-09-15 | check for errors on tod pdc ops. say that bad time is before 82 | Michael Shalayeff | |
| 2002-09-15 | better alias checking, verified w/ the regress | Michael Shalayeff | |
| 2002-09-15 | be more precise on what we save on traps. flush fpu regs in pcb since they ↵ | Michael Shalayeff | |
| are possibly accessed through non-coherent mappings | |||
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