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Intel chips. If the kernel is tricked into running code from a user
page while in supervisor mode we'll now get a page fault and panic
instead of running it.
suggestions and ok guenther@, ok deraadt@
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they can be conditionally called in future.
This makes the i386 speedstep code closer to the amd64 code
(though still with the added complications of VIA support and the
*_update_cpuspeed callbacks)
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Cyrix 3DNOW flag from normal cpuid flags as it will show up in
extended flags.
ok kettenis@
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frequencies on newer AMD systems.
Driver written by Bryan Steele / brynet gmail.com adjusted for i386
by myself. Put it in deraadt@
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ok marco@, deraadt@
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Discussed and okay drahn@. Okay deraadt@.
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ok kettenis
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to complete matthew@'s commit of a few days ago, and drop __HAVE_CPU_MUTEX_LEVEL
define. With help from, and ok deraadt@.
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rwlock misuse. In particular, this commit makes the following
changes:
1. i386 and amd64 now count the number of active mutexes so that
assertwaitok(9) can detect attempts to sleep while holding a mutex.
2. i386 and amd64 check that we actually hold mutexes when passed to
mtx_leave().
3. Calls to rw_exit*() now call rw_assert_{rd,wr}lock() as
appropriate.
ok krw@, oga@; "sounds good to me" deraadt@; assembly bits double
checked by pirofti@
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Dell Inspirion 4150 to wake up immediately even though RTC_EN isn't set
in the PM1 Enable register.
ok deraadt@, mlarkin@
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close causes a suspend. resumes are not tied to this; they happen
unconditionally. this is a temporary knob for the 4.8 release; afterwards
it will move to a more convenient place
much moaning discussing where to put the knob with kettenis
tested by various including phessler
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all jumbled up in the same functions. the rtc (mc chip) and clock (i8243)
startup was also mixed up. they the soft state and hardware state can
be started in the right order, and it is easy to restart just the
neccessary parts upon resume. tested in numerous cases:
(apic, pic) * (GENERIC.MP, GENERIC) * (mp, non-mp) * (i386, amd64)
ok kettenis
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context of some random process that happened to be switched onto the FPU
after the decision was made to send the IPI.
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the cpu.
ok kettenis@ as part of a larger diff.
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is active on, save a curpmap pointer in cpu_info. This lets us simplify
a few things and do lazy context switching from a user process to a
kernel thread. There's a new IPI introduced for forcing a cr3 reload
when we're tearing down a dead pmap.
kettenis@ ok (after I polished a few minor things)
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in seperate variables in struct cpu_info instead
of duplicating the process of extracting it from the signature.
Use this value when determining the bus clock on P6/family 0x6
chips, which fixes speedstep on bernd@'s ThinkPad x200s.
Discussed with several, 'just do it' weingart@, ok mikeb@
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In short, make cpu_unidle do what signotify used to do and
make signotify use cpu_unidle.
Also, include a cpu_unidle in need_resched, it won't change much right now
but will be needed in the future.
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which are uniform for the profclock on each cpu in a SMP system (but using
a different seed for each cpu). on all cpus, avoid seeding with a value out
of the [0, 2^31-1] range (since that is not stable)
ok kettenis drahn
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ok kettenis@
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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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and do an ipi_nop cross-call from signotify() instead.
ok miod@
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pointed out by and ok drahn@, toby@;
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also assume that 386 cpus are really unknown, and promote them to 486
instead of panic.
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uniform. as a result shared code like acpi needs less #ifdef's
ok marco kettenis
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significantly clean up the APM idle loop things. I actually can make
sense of what the APM idle loop is supposed to do.
Ok gwk@, beck@, and theo says ramdisks compile.
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to synchronize the tsc between CPUs anymore. While here, also remove
the slow TLB IPI since it's been dead for a while.
noticed by mickey
toby@ ok
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ok jsg
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from a diff by pierre riteau, but updated to look like the amd64 version
ok deraadt
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debugging by tom@, art@, kettenis@, and others. Testing by many others.
ok art@, kettenis@, tom@
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cores by the same amount, i.e. if you do hw.setperf=50 both cores will
be scaled to the opearting state corresponing to 50%. Tested by many with
est (mainly on core2duo machines like X60 thinkpads). Only enable est
during GENERIC.MP build no one tested powernow.
ok art@
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We need to poke the other CPU so that it processes the AST immediately
and doesn't wait for the next interrupt or syscall.
Since IPIs really shouldn't process ASTs, we need to trigger a soft
interrupt on the destination CPU to process the AST. But since we can't
send soft interrupts to other CPUs, we send an IPI, that triggers a soft
interrupt that in turn processes the AST.
Also, this marks the beginning of moving to slightly better IPI mechanism
of short and optimized IPIs instead of the large and complicated IPI
infrastructure we're using now.
tested by many, ok tholo@
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signal delivery more reliable in some cases when a process switches
cpu.
kettenis@ ok
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The "lapic" timer is ripped out since it wasn't actually a lapic timer,
but a hacked up tsc timer with some synchronization for MP. There is no
tsc timer right now since they are very unreliable on MP systems, systems
with apm, and systems that change the cpu clock. Which basically means
every modern machine out there. We're running with the i8259 timer now.
deraadt@ ok
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it's a good idea to use atomic.h operations on it. This mechanic
change updates all bit operations on p_flag to atomic_{set,clear}bits_int.
Only exception is that P_OWEUPC is set by MI code before calling
need_proftick and it's automatically cleared by ADDUPC. There's
no reason for MD handling of that flag since everyone handles it the
same way.
kettenis@ ok
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the freezes many of us are seeing (especially on amd64 machines running
OpenBSD/i386).
Much testing by nick@ (as always - thanks!), hugh@, ian@, kettenis@
and Sam Smith (s (at) msmith (dot) net).
Requested by, input from, and ok deraadt@ ok art@, kettenis@, miod@
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statclock(), do not bother doing this in userret() anymore. As a result,
userret() does not need its pc and ticks arguments, simplify.
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Rename pentium_mhz to cpuspeed which is consistant with amd64 making
shared ACPI code less nasty.
ok marco, deraadt
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errors to userland: make all cpu_setperf functions return void.
Tested by many, ok gwk@
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stuff in arch/i386/i386. This should prevent more screwups like the
one I did before in ichpcib.c...
ok dlg@ kettenis@
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for cpu_swapin() on hppa* which is kept).
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later for some identifications.
"slap it in" deraadt
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ok deraadt@ and many others.
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- If an unknown EST CPU is encountered, use the known highest and lowest
(and if different, the current) power state to generate a fake power
state table on the fly. Thanks to canacar for the idea.
- Calculate system bus clock speed before calling est_init(); it is
needed to display proper MHz values from MSR values.
- Also use the bus clock to identify EST CPU's, which is needed to
differentiate e.g. Pentium M 715 and 760, which unfortunately have
exactly the same MSR values.
- Store power states directly as MSR values.
Tested by many, "so when does it go in?" deraadt@
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send a bcast ipi from the cpu0 to all others to timestamp tsc
on every clock intr. this way using local tsc provides accurate
microtime() measurements. thus gettimeofday test passes now.
otto@ deraadt@ ok
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quintuplet { vendor, MHz_hi, mV_hi, MHz_lo, mV_lo }, which works much
better than parsing the branding string. It also makes it easier to add
new models later.
Shouldn't break any CPU's which previously worked okay with EST; if
there's any trouble, please let me know!
Also adds quite a number of VIA C7-M models, and a few more Pentium M
models, all from FreeBSD.
"go for it" deraadt@
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this and microtime() to interleave. ok deraadt@ toby@ mickey@
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if supported by the cpu(s). currently not enabled by default and
not compiled into ramdisks. this grows paddr_t to 64bit but yet
leaves bus_addr_t at 32bits. measures are taken to favour dmaable
memory allocation from below 4g line such that buffer cache is
already allocated form below, pool backend allocator prefers lower
memory and then finally bounce buffers are used as last resort.
PAE is engaged only if global variable cpu_pae is manually set
to non-zero and there is physical memory present above 4g.
simplify pcibios address math to use u_long as we always will
be in the 32bit space.
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limit selector, so that the w^x line can float much more dynamically.
Much work done by tom. Tested by various people. Addresses concerns of
(Julien Tinnes) <julien ATHOST cr0.org>
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