summaryrefslogtreecommitdiff
path: root/sys/arch/i386/include/specialreg.h
AgeCommit message (Expand)Author
2018-05-28More steps for i386 Meltdown fix:Alexander Bluhm
2018-02-10Additional AMD CPUID bits documented inJonathan Gray
2017-08-12add some extra comments that got left out of the previous IA32_MISC_ENABLEMike Larkin
2017-08-09Add IA32_MISC_ENABLE MSR and bitfield values, to be used shortly byMike Larkin
2017-08-09reorder some MSRs in the MSR list that were out of order. No functionalMike Larkin
2017-01-24SVM: matching i386 commit (missing host save area pa msr)Mike Larkin
2017-01-19SVM: VMCB intercept definitionsMike Larkin
2017-01-13Disable and lock Silicon Debug feature on modern Intel CPUsMike Belopuhov
2016-10-21vmm(4) for i386. Userland changes forthcoming. Note that for the time being,Mike Larkin
2016-09-03fix typo "mode" -> "model" when referring to "Model specific registers"Mike Larkin
2016-09-03add SDBG to cpuid bits and identcpuMike Larkin
2016-06-22Identify UMIP feature, if available.Mike Larkin
2016-04-26Convert some magic numbers into #defines - this is needed for some MTRRMike Larkin
2015-12-07Add cpuid bits documented in the August 2015 revision ofJonathan Gray
2015-06-07Add CR4_FSGSBASEPhilip Guenther
2015-05-28Save the cpuid(6) eax bits in the cpu_info and report the SENSOR and ARATPhilip Guenther
2015-03-25Mark CPUID_LEAF inline asm as volatile to prevent the compiler from reorderingMark Kettenis
2015-01-19Make use of an msr available on recent Intel processors to obtain theJonathan Gray
2015-01-15Define and print HV cpuid flag on i386.Stefan Fritsch
2014-07-03Add identcpu detection for 1-GByte pagesMatthew Dempsky
2013-08-24Cleanup amd64 and i386 MTRR code -Mike Larkin
2013-05-06the use of modern intel performance counter msrs to measure the number ofDavid Gwynne
2012-11-10Recent x86 CPUs come with a constant time stamp counter. If this isMarcus Glocker
2012-10-09Sync "Structured Extended Feature Flags" cpuid bits withJonathan Gray
2012-08-24Synchronize CR4 and CPUID portions of <machine/specialreg.h> for i386 and amd64Philip Guenthe
2012-03-27Implement the AMD suggested workaround for family 10h & 12h errata 721Jonathan Gray
2011-11-02display AMD/extended (0x80000001) cpuid flags and remove theJonathan Gray
2010-04-29Add the CR_PAT MSR to the list of defined msrs.Owain Ainsworth
2010-03-21Add some additional Intel CPUID values for recent and upcoming processors.Jonathan Gray
2009-10-07add support for the temperature sensor of VIA Nano and C7-M CPUs.Kevin Lo
2009-09-20Back out via nano temperature sensor changes.Jonathan Gray
2009-09-20add support for VIA Nano cpu core temperature sensorKevin Lo
2008-08-13Disable the fantastics mis-feature on some newer Turion CPUs called C1E.Artur Grabowski
2008-06-13Detect if Intel's Safer Mode Extensions (SMX) are present,Jonathan Gray
2007-10-17replacement for the pctr codebase that can handle amd64 processors asTheo de Raadt
2007-05-29add support for core cpu temperature sensors.Ted Unangst
2007-02-17Bring in the AMD errata checks from amd64.Tom Cosgrove
2007-02-13Check for xTPR result of CPUID.Jonathan Gray
2006-06-12Some more improvements to EST:Dimitry Andric
2006-03-07Check for a few additional CPUID flags.Jonathan Gray
2005-08-20PNI was changed to be known as SSE3 by Intel so makeJonathan Gray
2005-06-26cpu0: RNG AES AES-CTR SHA1 SHA256 RSATheo de Raadt
2004-06-25Add extended CPUID flag value for AMD64 LONG identification. Taken fromTom Cosgrove
2004-06-15first parts of how C3 Esther will be handled; ok tomTheo de Raadt
2004-04-02K6-2/3 powernow driver. not without quirks, but mostly working.Ted Unangst
2004-02-19- split intel686_cpu_setup() into two parts: common for familyAlexander Yurchenko
2004-02-052 new cpuid ecx features in prescottTheo de Raadt
2004-02-03move VIA xcrypt-* options to specialreg.hTheo de Raadt
2004-01-31rename SIMD/SIMD2 to SSE/SSE2Theo de Raadt
2003-12-18add new hw sysctls, cpuspeed and setperf to control cpu frequency.Ted Unangst
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-28 04:36:41 +0000