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path: root/sys/arch/i386/include/specialreg.h
AgeCommit message (Expand)Author
2012-11-10Recent x86 CPUs come with a constant time stamp counter. If this isMarcus Glocker
2012-10-09Sync "Structured Extended Feature Flags" cpuid bits withJonathan Gray
2012-08-24Synchronize CR4 and CPUID portions of <machine/specialreg.h> for i386 and amd64Philip Guenthe
2012-03-27Implement the AMD suggested workaround for family 10h & 12h errata 721Jonathan Gray
2011-11-02display AMD/extended (0x80000001) cpuid flags and remove theJonathan Gray
2010-04-29Add the CR_PAT MSR to the list of defined msrs.Owain Ainsworth
2010-03-21Add some additional Intel CPUID values for recent and upcoming processors.Jonathan Gray
2009-10-07add support for the temperature sensor of VIA Nano and C7-M CPUs.Kevin Lo
2009-09-20Back out via nano temperature sensor changes.Jonathan Gray
2009-09-20add support for VIA Nano cpu core temperature sensorKevin Lo
2008-08-13Disable the fantastics mis-feature on some newer Turion CPUs called C1E.Artur Grabowski
2008-06-13Detect if Intel's Safer Mode Extensions (SMX) are present,Jonathan Gray
2007-10-17replacement for the pctr codebase that can handle amd64 processors asTheo de Raadt
2007-05-29add support for core cpu temperature sensors.Ted Unangst
2007-02-17Bring in the AMD errata checks from amd64.Tom Cosgrove
2007-02-13Check for xTPR result of CPUID.Jonathan Gray
2006-06-12Some more improvements to EST:Dimitry Andric
2006-03-07Check for a few additional CPUID flags.Jonathan Gray
2005-08-20PNI was changed to be known as SSE3 by Intel so makeJonathan Gray
2005-06-26cpu0: RNG AES AES-CTR SHA1 SHA256 RSATheo de Raadt
2004-06-25Add extended CPUID flag value for AMD64 LONG identification. Taken fromTom Cosgrove
2004-06-15first parts of how C3 Esther will be handled; ok tomTheo de Raadt
2004-04-02K6-2/3 powernow driver. not without quirks, but mostly working.Ted Unangst
2004-02-19- split intel686_cpu_setup() into two parts: common for familyAlexander Yurchenko
2004-02-052 new cpuid ecx features in prescottTheo de Raadt
2004-02-03move VIA xcrypt-* options to specialreg.hTheo de Raadt
2004-01-31rename SIMD/SIMD2 to SSE/SSE2Theo de Raadt
2003-12-18add new hw sysctls, cpuspeed and setperf to control cpu frequency.Ted Unangst
2003-07-25s/CPUID_SYS2/CPUID_SEP/ to avoid confusionMichael Shalayeff
2003-07-25make sure SYSENTER registers are 0 at boot time. should fix an unusualTed Unangst
2003-06-06Identify Pentium M CPUAndreas Gunnarsson
2003-06-02Remove the advertising clause in the UCB license which BerkeleyTodd C. Miller
2003-03-14Support for the VIA C3 Nehemiah on-cpu random number generator. This chipTheo de Raadt
2001-12-04more bits defs; from netbsdMichael Shalayeff
2001-01-26more special regs definitions; use names from pctr.h for those it usesMichael Shalayeff
2000-11-10seperate -> separate, okay aaron@Niels Provos
1999-11-20add MTRR support from FreeBSDMatthieu Herrb
1999-03-08Add support for CPUID level 2. This is used to determine the L2 cache sizeJason Downs
1999-02-24pIII handling; testing by jdb@layer8.netTheo de Raadt
1998-05-25Add support for feature bit listing; fix #defines.Jason Downs
1997-09-05add full defines for %cr4 bits and cpu_feature bits (names match freebsdchuck
1996-10-16missing */Theo de Raadt
1996-09-16supporting advanced pentium architecture functions.Michael Shalayeff
1995-10-18initial import of NetBSD treeTheo de Raadt
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