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__builtin_next_arg for !GCC until pcc supports it. ok kjell@ miod@
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the holes a MMU may have from a given vm_map. This will be automagically
invoked for newly created vmspaces.
On platforms with MMU holes (e.g. sun4, sun4c and vax), this prevents
mmap(2) hints which would end up being in the hole to be accepted as valid,
causing unexpected signals when the process tries to access the hole
(since pmap can not fill the hole anyway).
Unfortunately, the logic mmap() uses to pick a valid address for anonymous
mappings needs work, as it will only try to find an address higher than the
hint, which causes all mmap() with a hint in the hole to fail on vax. This
will be improved later.
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to synchronize the tsc between CPUs anymore. While here, also remove
the slow TLB IPI since it's been dead for a while.
noticed by mickey
toby@ ok
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version for i386
more architectures and ctob() replacement is being worked on
prodded by and ok miod
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Comments and ok kettenis, art & miod
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cpu_disklabel can go away, since nothing anymore needs to use it; ok miod
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to support hotplug media on most architectures. disklabel setup and
verification done using new helper functions. Disklabels must *always*
have a correct checksum now. Same code paths are used to learn on-disk
location disklabels, to avoid new errors sneaking in. Tested on almost all
cases, testing help from todd, kettenis, krw, otto, dlg, robert, gwk, drahn
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ok jsg
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the commit which enabled DEADBEEF* overrides, then values have been
discussed a bit more and improved; reminded by and ok art@
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pieces. Since this is where the "boot both ELF32 and ELF64" behaviour
is turned on for i386, it is quite important.
Bump version numbers too.
Found by ckuethe@; thanks.
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from a diff by pierre riteau, but updated to look like the amd64 version
ok deraadt
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the rare 80386-bases system with enough memory, a 387 FPU, a useable
disk subsystem, and the patience to wait for it to unpack the
distribution .tgz files.
approval from art@ and many others (esp. nick@); ok deraadt@
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mbuf constants from MD param.h to MI param.h.
Besides being the same on every arch, things will
most probly break if any arch has different values
then the others.
The NMBCLUSTERS constants needs to be MD though;
ok miod@,krw@,claudio@
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with the complicated and expensive macros.
tom@ ok
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debugging by tom@, art@, kettenis@, and others. Testing by many others.
ok art@, kettenis@, tom@
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very simple and dumb fast tlb IPI handlers that have in the order of
the same amount of instructions as the old code had function calls.
All TLB shootdowns are reorganized so that we always shoot the,
without looking at PG_U and when we're shooting a range (primarily in
pmap_remove), we shoot the range when there are 32 or less pages in
it, otherwise we just nuke the whole TLB (this might need tweaking if
someone is interested in micro-optimization). The IPIs are not handled
through the normal interrupt vectoring code, they are not blockable
and they only shoot one page or a range of pages or the whole tlb.
This gives a 15% reduction in system time on my dual-core laptop
during a kernel compile and an 18% reduction in real time on a quad
machine doing bulk ports build.
Tested by many, in snaps for a week, no slowdowns reported (although not
everyone is seeing such huge wins).
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splassert_ctl > 0 in __predict_false().
ok deraadt@
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have cpu_info now, so kill the option.
eyeballed by jsg@ and grange@
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option. Every architecture implements mutexes now.
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It uses a function pointer to choose between the 386 and 486 versions.
The 386 version is not MP safe, but we're not expecting MP support
for 386 cpus.
miod@ ok (and prodding)
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pg_flags, so we actually shave quite a few bytes from the memory
we eat at boot. (a machine with 1GB memory saves 256k).
deraadt@, pedro@, krw@ ok. Lots of testing.
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paddr_t changing from 32 bits.
From mickey's original PAE work of a year ago
Tested by myself and nick@; ok art@
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cores by the same amount, i.e. if you do hw.setperf=50 both cores will
be scaled to the opearting state corresponing to 50%. Tested by many with
est (mainly on core2duo machines like X60 thinkpads). Only enable est
during GENERIC.MP build no one tested powernow.
ok art@
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We need to poke the other CPU so that it processes the AST immediately
and doesn't wait for the next interrupt or syscall.
Since IPIs really shouldn't process ASTs, we need to trigger a soft
interrupt on the destination CPU to process the AST. But since we can't
send soft interrupts to other CPUs, we send an IPI, that triggers a soft
interrupt that in turn processes the AST.
Also, this marks the beginning of moving to slightly better IPI mechanism
of short and optimized IPIs instead of the large and complicated IPI
infrastructure we're using now.
tested by many, ok tholo@
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signal delivery more reliable in some cases when a process switches
cpu.
kettenis@ ok
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seem to have reached this limit.
ok marco@, looks ok ckuethe@
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intrdefs.h that is inlucded first thing in intr.h.
eyeballed for sanity by pedro@
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The "lapic" timer is ripped out since it wasn't actually a lapic timer,
but a hacked up tsc timer with some synchronization for MP. There is no
tsc timer right now since they are very unreliable on MP systems, systems
with apm, and systems that change the cpu clock. Which basically means
every modern machine out there. We're running with the i8259 timer now.
deraadt@ ok
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it's a good idea to use atomic.h operations on it. This mechanic
change updates all bit operations on p_flag to atomic_{set,clear}bits_int.
Only exception is that P_OWEUPC is set by MI code before calling
need_proftick and it's automatically cleared by ADDUPC. There's
no reason for MD handling of that flag since everyone handles it the
same way.
kettenis@ ok
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the freezes many of us are seeing (especially on amd64 machines running
OpenBSD/i386).
Much testing by nick@ (as always - thanks!), hugh@, ian@, kettenis@
and Sam Smith (s (at) msmith (dot) net).
Requested by, input from, and ok deraadt@ ok art@, kettenis@, miod@
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rt and such; tested and ok miod drahn
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Changes to either copy of amd64errata.c must be replicated in the other.
ok deraadt@
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ok tom@
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right now that are supposed to be atomic with respect to interrupts and
SMP: atomic_setbits_int and atomic_clearbits_int.
All architectures other than i386 and amd64 get dummy implementations
since at first we'll be replacing operations that are done with
"a |= bit" and "a &= ~bit" today. More proper implementations will follow
kettenis@, miod@ ok
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statclock(), do not bother doing this in userret() anymore. As a result,
userret() does not need its pc and ticks arguments, simplify.
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Rename pentium_mhz to cpuspeed which is consistant with amd64 making
shared ACPI code less nasty.
ok marco, deraadt
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errors to userland: make all cpu_setperf functions return void.
Tested by many, ok gwk@
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brad, thanks.
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stuff in arch/i386/i386. This should prevent more screwups like the
one I did before in ichpcib.c...
ok dlg@ kettenis@
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for cpu_swapin() on hppa* which is kept).
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ok deraadt, "slap it in" miod@
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later for some identifications.
"slap it in" deraadt
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alternative sources for interrupt information.
ok gwk@, brad@
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"The dosparts member of cpu_disklabel was not used for any persistant
data. Eliminate it, and just use the data being read in while
processing MBR and EBR records.
Should be no functional change.
ok weingart@ deraadt@"
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some architectures (kaboom); that will be fixed in the next iteration
hopefully!
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data. Eliminate it, and just use the data being read in while
processing MBR and EBR records.
Should be no functional change.
ok weingart@ deraadt@
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