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needed (not just for I686_CPU), but it and ichpcib only call the
update_cpuspeed functions for I686_CPU.
ok tedu@ deraadt@
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for PCI-PCI bridges and passing the mapping to the attached bus device.
MD code can use these when mapping PCI device interrupts. This diff adds
such code for amd64 and i386. This fixes interrupt mapping for devices that
sit behind two PCI-PCI bridges where the firmware only provides a mapping
for the first PCI-PCI bridge.
tested by sturm@, krw@, and a few others, ok deraadt@
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parings of the Intel Pentium 3 and the ich southbridges. Written by
Stefan Sperling <stsp AT tsp DOT in-berlin DOT de> based on a driver in
NetBSD and sys/arch/i386/pci/ichpcib.c.
Tested my mpf@ among others,
ok tedu
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Spotted by Stefan Sperling <stsp AT tsp.in-berlin.de> when reviewing
his piix speedstep diff.
ok tedu@
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the freezes many of us are seeing (especially on amd64 machines running
OpenBSD/i386).
Much testing by nick@ (as always - thanks!), hugh@, ian@, kettenis@
and Sam Smith (s (at) msmith (dot) net).
Requested by, input from, and ok deraadt@ ok art@, kettenis@, miod@
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don't support the other required operations in the driver, but will be
used by OpenSSL.
ok deraadt@
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reality, and remove the maxpolls stuff at the same time. Still disabled
in-tree.
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bit (well, uint32 by uint32). Inspired by a claudio commit to malo.c.
Still disabled (awaiting a code review), but works for me here.
ok claudio@
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for a pci device.
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domain number such that we can distinguish between busses with the same bus
number that are behind different host bridges. Domains can be accessed by
using different device nodes.
ok deraadt@
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errors to userland: make all cpu_setperf functions return void.
Tested by many, ok gwk@
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inetrrupt routing information.
ok deraadt@
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stuff in arch/i386/i386. This should prevent more screwups like the
one I did before in ichpcib.c...
ok dlg@ kettenis@
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cannot io map the device. rest of the attach() functionality is still
safely intact. we simply do not have to warn about mapping failing.
ok kettenis
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since Celerons don't support it.
prodded by gwk@
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by processing in a loop. And bump the size of this buffer (32KB
taken by the driver shouldn't be a problem).
Also reduce the places we hard-code the AES block size of 16.
Still disabled (doing more testing), but I want to commit before
the aged hard disk I have in the system here dies.
(This commit from the Geode system with the AES enabled.)
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buffer on attach, and using it for encrypt/decrypt operations. Still
disabled, since the driver cannot currently handle an operation larger
than supported by this buffer. (Interactive ssh does work with this
code, however.)
"commit, of course" deraadt@
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`#undef CRYPTO' since it doesn't work properly yet. Committing in
order to get it into the tree.
"get it in" deraadt@
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alternative sources for interrupt information.
ok gwk@, brad@
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Currently just uses the RNG; AES support to be added later.
ok deraadt@
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rather than when CPUID says we're on any Geode. Should avoid reset
failure on Nokia IP110s and other non-SC1100 Geode-based systems.
Reset should hopefully still work on Soekris Net4801s and PC Engines
WRAP systems, but no-one bothered to test and report back in two days.
"commit" deraadt@
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PowerEdge 2900, 2950) that otherwise lock up at the end of autoconf.
ok dlg@, marco@
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1. Reserve resources for enabled devices.
2. Reserve resources for disabled devices.
3. Allocate resources.
This way we no longer need to enable/disable devices during fixup.
Based on an earlier patch by drahn@.
ok deraadt@, drahn@
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ok toby@
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also needs a X.org update, which will go in later.
Tested by a bunch of people; ok deraadt@
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if supported by the cpu(s). currently not enabled by default and
not compiled into ramdisks. this grows paddr_t to 64bit but yet
leaves bus_addr_t at 32bits. measures are taken to favour dmaable
memory allocation from below 4g line such that buffer cache is
already allocated form below, pool backend allocator prefers lower
memory and then finally bounce buffers are used as last resort.
PAE is engaged only if global variable cpu_pae is manually set
to non-zero and there is physical memory present above 4g.
simplify pcibios address math to use u_long as we always will
be in the 32bit space.
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NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
From NetBSD
ok grange@ kettenis@
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now that kettenis@ has corrected the PCI id entry.
- Add the SiS 962 chipset.
ok kettenis@ mickey@
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HyperTransport configuration on AMD Athlon 64 & Opteron CPU's. This makes us
detect the missing PCI busses on various Opteron systems.
tested by krw@, brad@; ok brad@
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one tweak suggested by miod@.
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at least i810 on x40, but made x41 work. ok matthieu
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From Ian McWilliam ian at dodo.com.au.
ok mickey@
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