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(i.e. with the valid bit set in them). Found the hard way by Anders Gavare
trying his latest gxemul, proves the hardware is more permitting than one
would expect it to be...
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even in non-MP kernels, to avoid unnecessary tlb flushes later when
pmap operates on shared pages.
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other MP platforms.
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protected by __ISO_C_VISIBLE > 1999. With a little help from miod@.
ok miod@
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which are uniform for the profclock on each cpu in a SMP system (but using
a different seed for each cpu). on all cpus, avoid seeding with a value out
of the [0, 2^31-1] range (since that is not stable)
ok kettenis drahn
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anything special to prod a cpu to leave the idle loop in signotify.
powerpc, i386, amd64 and sparc64 will follow soon so that everyone has
the same interface to wake an idling cpu.
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For now, sparc64 is arbitrarily set to 256 (only architecture that didn't have
a practical limit in the code on the number of cpus).
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- provide proper dtoa locks
- use the real strtof implementation
- add strtold, __hdtoa, __hldtoa
- add %a/%A support
- don't lose precision in printf, don't round to double anymore
- implement extended-precision versions of libc functions: fpclassify,
isnan, isinf, signbit, isnormal, isfinite, now that the ieee.h is
fixed
- separate vax versions of strtof, and __hdtoa
- add complex math support. added functions: cacos, casin, catan,
ccos, csin, ctan, cacosh, casinh, catanh, ccosh, csinh, ctanh, cexp,
clog, cabs, cpow, csqrt, carg, cimag, conj, cproj, creal, cacosf,
casinf, catanf, ccosf, csinf, ctanf, cacoshf, casinhf, catanhf,
ccoshf, csinhf, ctanhf, cexpf, clogf, cabsf, cpowf, csqrtf, cargf,
cimagf, conjf, cprojf, crealf
- add fdim, fmax, fmin
- add log2. (adapted implementation e_log.c. could be more acruate
& faster, but it's good enough for now)
- remove wrappers & cruft in libm, supposed to work-around mistakes
in SVID, etc.; use ieee versions. fixes issues in python 2.6 for
djm@
- make _digittoint static
- proper definitions for i386, and amd64 in ieee.h
- sh, powerpc don't really have extended-precision
- add missing definitions for mips64 (quad), m{6,8}k (96-bit) float.h
for LDBL_*
- merge lead to frac for m{6,8}k, for gdtoa to work properly
- add FRAC*BITS & EXT_TO_ARRAY32 definitions in ieee.h, for hdtoa&ldtoa
to use
- add EXT_IMPLICIT_NBIT definition, which indicates implicit
normalization bit
- add regression tests for libc: fpclassify and printf
- arith.h & gd_qnan.h definitions
- update ieee.h: hppa doesn't have quad-precision, hppa64 does
- add missing prototypes to gdtoaimp
- on 64-bit platforms make sure gdtoa doesn't use a long when it
really wants an int
- etc., what i may have forgotten...
- bump libm major, due to removed&changed symbols
- no libc bump, since this is riding on djm's libc major crank from
a day ago
discussed with / requested by / testing theo, sthen@, djm@, jsg@,
merdely@, jsing@, tedu@, brad@, jakemsr@, and others.
looks good to millert@
parts of the diff ok kettenis@
this commit does not include:
- man page changes
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userland is allowed to change in psr.
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so don't use any in the 88110-specific parts of locore.
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- math.h shouldn't define FLT_EVAL_METHOD, but float.h should (per
C99). remove from math.h, and add proper definitions in float.h
ok millert@
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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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conversions that should shave a few bytes off the kernel.
ok henning, krw, jsing, oga, miod, and thib (``even though i usually prefer
FOO|BAR''; thanks for looking.
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spotted by drahn
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shorter code than a conditional ADDCARRY, so use it; inspired by hppa.
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1 for 88110), for userland to have an easy way to figure out.
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on m88k.
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have jumped on it instead of basing the FPU completion work on the sparc
FPU code.
This is now repaired with this commit, and m88110_fp.c changes directory
again, for the last time.
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instructions to be serialized (this defeats the purpose of having a superscalar
processor, and accesses to volatile variables are done with explicit memory
barriers anyway).
This brings a HUGE speedup: openssl speed -elapsed shows AES is 90% faster,
blowfish is 75% faster, and sha1 is 50% faster. Not so bad!
However, doing this increases the pressure on the processor bus, so it is
necessary to increase the processor bus timeout on 40MHz boards again (to 256
usec). ``black cat'' 50MHz boards seem to be unaffected, so they remain at
64 usec.
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forms of fcvt where source and destination precision is the same.
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sparc{,64} floating-point emulator, adapted to the 88110 specifics. Handling
of these traps is now entirely done in C for convenience.
Although there are a few rounding issues to address, and the XRF is ignored,
this allows all the ieee754 regression tests to pass (lib/libc/ieeefp,
sys/kern/signal/fpsig, sys/kern/signal/sigfpe).
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Fits in the brown-paperbag bug category.
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it five times.
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of offsets / sizeof(register_t), and nuke the REG_OFF macro. No functional
change.
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this allows us to get rid of the dependency of asm_macro.h on asm.h, which
was really only there to bring in psl.h.
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in a _KERNEL-only section, and we want to eventually be able to use it from
the bootblocks.
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be necessary, but not doing it appears to break 88204 (not 88200) and
split CMMUs.
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invalidate tlb ipis, and turn them into simple ``handle once'' ipis.
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MVME197DP to serialize 88410 operations.
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out-of-order (superscalar) execution on these processors.
Since OoO brings a nice 50% to 250% speedup (as shown by ``openssl speed''),
it is definitely worth enabling.
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more work in progress to handle these exceptions correctly, and document
a new undocumented and evil chip bug while there.
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is required.
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field from the processor identification register; this allows .S code which
needs to decide on the cpu type at runtime to check quicker, without needing
to access memory. No functional change.
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