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2009-02-21Move part of the mp lock logic into per-cpu callbacks; on MVME197DP we needMiod Vallat
to disable NMI sources in addition to interrupt sources, and we can not use a quick sequence with shadowing frozen as done for atomic ops. This lets GENERIC.MP boot multiuser on MVME197DP boards, and is so far stable enough to be able to recompile a kernel from scratch (with make -j2).
2009-02-21Get rid of 88110 nmi stacks. This was a good idea, but I outsmarted myselfMiod Vallat
since it was intended to service NMI occuring in user mode, and we could end up invoking preempt() and have another cpu start using this stack, with interesting results.
2009-02-20This should get me nominated for the ``stupidest bug of the year'' award.Miod Vallat
2009-02-20atomic_{set,clear}bits_int were not safe enough on 88110 systems, as theyMiod Vallat
can be interrupted by NMI; move the SMP version of these routines from inlines to a separate file (kernel text shrinks 20KB...). Since the implementation for 88110 becomes really hairy, the pre-main() code is responsible for copying the appropriate code over for kernels configured for both 88100 and 88110 cpus, to avoid having to choose the atomicity strategy at runtime. Hairy, I said. This gets GENERIC.MP run much further on 197DP. Not enough to reach multiuser mode, but boots up to starting sshd and then panics.
2009-02-18In __cpu_simple_lock(), do not hog the bus with exclusive accesses; ifMiod Vallat
xmem didn't return the expected value, spin doing regular loads until it appears we have a chance to grab the lock again.
2009-02-18typoMiod Vallat
2009-02-17Pass a cpu_info * to setsoftipi() so it does not need to curcpu(), whichMiod Vallat
synchronizes the pipeline on 88110.
2009-02-16More 88110 SMP work. Contains, horribly entangled:Miod Vallat
- dma_cachectl() split into a ``local cpu only'' and ``all cpus'', and an ipi to broadcast ``local dma_cachectl'' is added. - cpu_info fields are rearranged, to have the 88100-specific information and the 88110-specific information overlap, and has many more 88110 ugly things. - more ipi handling in the 197-specific area. Since it is not possible to have the second processor receive any hardware interrupt (selection is done on a level basis via ISEL, and we definitely do not want the main cpu to lose interrupts), the best we can do is to inflict ourselves a soft interrupt for late ipi processing. It gets used for softclock and hardclock on the secondary processor, but since the soft interrupt dispatcher doesn't have an exception frame, we have to remember parts of it to build a fake clockframe from the soft ipi handler (ugly but works). This now lets GENERIC.MP run a few userland binaries before bugs trigger.
2009-02-16Since NMI are now handled separately, remove the ``interrupt type'' argumentMiod Vallat
from interrupt() and related function pointers.
2009-02-16Rewrite the way the initial processing of exceptions is done on 88110 - weMiod Vallat
now set up both the exception frame structure and the exception stack as soon as possible, so that we can safely get interrupted by an NMI as soon as we reenable shadowing.
2009-02-15If we are on the NMI stack, do not switch to the curpcb stack moments later,Miod Vallat
this defeats the purpose of having a separate stack at this point... Oopsie
2009-02-13Use a different dispatcher for the NMI traps on 88110, these are tooMiod Vallat
different from regular hardware interrupts to be worth handling the same way. Disable IPI reception while we are handling pending IPIs. And do not reenable them by mistake if we need to send an IPI in return. This lets GENERIC.MP boot single user on a MVME197DP. There are still many bugs to fix.
2009-02-13When switching processes, do not reenable interrupts until pmap_activate()Miod Vallat
has been invoked on the new process.
2009-02-08On 88110 processors, use a separate stack to handle NMI; these can occurMiod Vallat
while we are switching pcbs and all sort of bad things could happen.
2009-02-08Don't bother trying to recover from DSR_WE data faults in kernel mode,Miod Vallat
pmap makes sure these can't happen.
2009-02-01Remove dma_cachectl() and rename dma_cachectl_pa() to dma_cachectl() now thatMiod Vallat
the old vs(4) code is gone.
2008-12-21Proper cpu_unidle() function for MP kernels. ok art@ long agoMiod Vallat
2008-11-27On 88100 cpus, make sure userland processes start with SNIP and SFIP validMiod Vallat
(i.e. with the valid bit set in them). Found the hard way by Anders Gavare trying his latest gxemul, proves the hardware is more permitting than one would expect it to be...
2008-10-30In cpu_switchto(), always pmap_deactivate() the process being switched out,Miod Vallat
even in non-MP kernels, to avoid unnecessary tlb flushes later when pmap operates on shared pages.
2008-10-27Rename "machine cpu" to "machine ddbcpu" in MP kernels, for consistency withMiod Vallat
other MP platforms.
2008-10-23Move the va_copy define to <sys/stdrag.h> making sure it is uniformalyMark Kettenis
protected by __ISO_C_VISIBLE > 1999. With a little help from miod@. ok miod@
2008-10-15make random(9) return per-cpu values (by saving the seed in the cpuinfo),Theo de Raadt
which are uniform for the profclock on each cpu in a SMP system (but using a different seed for each cpu). on all cpus, avoid seeding with a value out of the [0, 2^31-1] range (since that is not stable) ok kettenis drahn
2008-10-10Add empty cpu_unidle() macros for architectures that currently don't doArtur Grabowski
anything special to prod a cpu to leave the idle loop in signotify. powerpc, i386, amd64 and sparc64 will follow soon so that everyone has the same interface to wake an idling cpu.
2008-10-10Define MAXCPUS on all architectures.Artur Grabowski
For now, sparc64 is arbitrarily set to 256 (only architecture that didn't have a practical limit in the code on the number of cpus).
2008-09-07- replace dtoa w/ David's gdtoa, version 2008-03-15Martynas Venckus
- provide proper dtoa locks - use the real strtof implementation - add strtold, __hdtoa, __hldtoa - add %a/%A support - don't lose precision in printf, don't round to double anymore - implement extended-precision versions of libc functions: fpclassify, isnan, isinf, signbit, isnormal, isfinite, now that the ieee.h is fixed - separate vax versions of strtof, and __hdtoa - add complex math support. added functions: cacos, casin, catan, ccos, csin, ctan, cacosh, casinh, catanh, ccosh, csinh, ctanh, cexp, clog, cabs, cpow, csqrt, carg, cimag, conj, cproj, creal, cacosf, casinf, catanf, ccosf, csinf, ctanf, cacoshf, casinhf, catanhf, ccoshf, csinhf, ctanhf, cexpf, clogf, cabsf, cpowf, csqrtf, cargf, cimagf, conjf, cprojf, crealf - add fdim, fmax, fmin - add log2. (adapted implementation e_log.c. could be more acruate & faster, but it's good enough for now) - remove wrappers & cruft in libm, supposed to work-around mistakes in SVID, etc.; use ieee versions. fixes issues in python 2.6 for djm@ - make _digittoint static - proper definitions for i386, and amd64 in ieee.h - sh, powerpc don't really have extended-precision - add missing definitions for mips64 (quad), m{6,8}k (96-bit) float.h for LDBL_* - merge lead to frac for m{6,8}k, for gdtoa to work properly - add FRAC*BITS & EXT_TO_ARRAY32 definitions in ieee.h, for hdtoa&ldtoa to use - add EXT_IMPLICIT_NBIT definition, which indicates implicit normalization bit - add regression tests for libc: fpclassify and printf - arith.h & gd_qnan.h definitions - update ieee.h: hppa doesn't have quad-precision, hppa64 does - add missing prototypes to gdtoaimp - on 64-bit platforms make sure gdtoa doesn't use a long when it really wants an int - etc., what i may have forgotten... - bump libm major, due to removed&changed symbols - no libc bump, since this is riding on djm's libc major crank from a day ago discussed with / requested by / testing theo, sthen@, djm@, jsg@, merdely@, jsing@, tedu@, brad@, jakemsr@, and others. looks good to millert@ parts of the diff ok kettenis@ this commit does not include: - man page changes
2008-07-28Remove dead code.Miod Vallat
2008-07-28In process_write_regs() and sigreturn(), be more strict about the bitsMiod Vallat
userland is allowed to change in psr.
2008-07-28According to the manual, delay slot kill the benefits of being superscalar,Miod Vallat
so don't use any in the 88110-specific parts of locore.
2008-07-21- add proper double_t and float_t definitions for each archMartynas Venckus
- math.h shouldn't define FLT_EVAL_METHOD, but float.h should (per C99). remove from math.h, and add proper definitions in float.h ok millert@
2008-07-18Add a macro that clears the want_resched flag that need_resched sets.Artur Grabowski
Right now when mi_switch picks up the same proc, we didn't clear the flag which would mean that every time we service an AST we would attempt a context switch. For some architectures, amd64 being probably the most extreme, that meant attempting to context switch for every trap and interrupt. Now we clear_resched explicitly after every context switch, even if it didn't do anything. Which also allows us to remove some more code in cpu_switchto (not done yet). miod@ ok
2008-06-14A bunch of pool_get() + bzero() -> pool_get(..., .. | PR_ZERO)Michael Knudsen
conversions that should shave a few bytes off the kernel. ok henning, krw, jsing, oga, miod, and thib (``even though i usually prefer FOO|BAR''; thanks for looking.
2008-06-10Rename pmap_remove_all() to pmap_remove_page().Miod Vallat
2008-05-02Check for a disabled FPU before attempting to emulate the instruction.Miod Vallat
2008-05-02Grab the biglock unconditionnaly when system calls go through systrace;Miod Vallat
spotted by drahn
2008-04-25neccessary -> necessary; from Pierre RiteauJason McIntyre
2008-04-01typoMiod Vallat
2008-02-20Preserve pcb_onfault within kcopy(), as expected and as all other platforms do.Miod Vallat
2008-02-16On these platforms, REDUCEing unconditionnaly a second time is faster andMiod Vallat
shorter code than a conditional ADDCARRY, so use it; inspired by hppa.
2008-01-13Add a machdep.cputype sysctl, which returns the processor type (0 for 88100,Miod Vallat
1 for 88110), for userland to have an easy way to figure out.
2007-12-31replace ctob/btoc by ptoa/atop as done for other architecturesMartin Reindl
2007-12-29Override SoftFloat's countLeadingZeros32() with a faster, ff1-based, versionMiod Vallat
on m88k.
2007-12-29Had I known we had a kernel version of John Hauser's SoftFloat code, I wouldMiod Vallat
have jumped on it instead of basing the FPU completion work on the sparc FPU code. This is now repaired with this commit, and m88110_fp.c changes directory again, for the last time.
2007-12-26Remove the last debug bit from the PSR on 88110: do not force memory accessesMiod Vallat
instructions to be serialized (this defeats the purpose of having a superscalar processor, and accesses to volatile variables are done with explicit memory barriers anyway). This brings a HUGE speedup: openssl speed -elapsed shows AES is 90% faster, blowfish is 75% faster, and sha1 is 50% faster. Not so bad! However, doing this increases the pressure on the processor bus, so it is necessary to increase the processor bus timeout on 40MHz boards again (to 256 usec). ``black cat'' 50MHz boards seem to be unaffected, so they remain at 64 usec.
2007-12-26Honour the rounding mode in fpu_ftoi().Miod Vallat
2007-12-26First try at getting the interval bits filled in fcmp{,u} results.Miod Vallat
2007-12-26Fix FPU_SET_CARRY()Miod Vallat
2007-12-25A few fixes in the exception bits reporting, spotted by John Hauser's TestFloat.Miod Vallat
2007-12-25Zero / Num should return a zero with the same sign as the divider.Miod Vallat
2007-12-25Accept valid forms of double-precision fmul/fadd/fsub/fdiv and reject invalidMiod Vallat
forms of fcvt where source and destination precision is the same.
2007-12-25Missing pointer initialization for int/nint/trnc exceptions.Miod Vallat