| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-02-16 | On these platforms, REDUCEing unconditionnaly a second time is faster and | Miod Vallat | |
| shorter code than a conditional ADDCARRY, so use it; inspired by hppa. | |||
| 2008-01-13 | Add a machdep.cputype sysctl, which returns the processor type (0 for 88100, | Miod Vallat | |
| 1 for 88110), for userland to have an easy way to figure out. | |||
| 2007-12-31 | replace ctob/btoc by ptoa/atop as done for other architectures | Martin Reindl | |
| 2007-12-29 | Override SoftFloat's countLeadingZeros32() with a faster, ff1-based, version | Miod Vallat | |
| on m88k. | |||
| 2007-12-29 | Had I known we had a kernel version of John Hauser's SoftFloat code, I would | Miod Vallat | |
| have jumped on it instead of basing the FPU completion work on the sparc FPU code. This is now repaired with this commit, and m88110_fp.c changes directory again, for the last time. | |||
| 2007-12-26 | Remove the last debug bit from the PSR on 88110: do not force memory accesses | Miod Vallat | |
| instructions to be serialized (this defeats the purpose of having a superscalar processor, and accesses to volatile variables are done with explicit memory barriers anyway). This brings a HUGE speedup: openssl speed -elapsed shows AES is 90% faster, blowfish is 75% faster, and sha1 is 50% faster. Not so bad! However, doing this increases the pressure on the processor bus, so it is necessary to increase the processor bus timeout on 40MHz boards again (to 256 usec). ``black cat'' 50MHz boards seem to be unaffected, so they remain at 64 usec. | |||
| 2007-12-26 | Honour the rounding mode in fpu_ftoi(). | Miod Vallat | |
| 2007-12-26 | First try at getting the interval bits filled in fcmp{,u} results. | Miod Vallat | |
| 2007-12-26 | Fix FPU_SET_CARRY() | Miod Vallat | |
| 2007-12-25 | A few fixes in the exception bits reporting, spotted by John Hauser's TestFloat. | Miod Vallat | |
| 2007-12-25 | Zero / Num should return a zero with the same sign as the divider. | Miod Vallat | |
| 2007-12-25 | Accept valid forms of double-precision fmul/fadd/fsub/fdiv and reject invalid | Miod Vallat | |
| forms of fcvt where source and destination precision is the same. | |||
| 2007-12-25 | Missing pointer initialization for int/nint/trnc exceptions. | Miod Vallat | |
| 2007-12-25 | Never write boolean expressions which do not fit in one line, after midnight. | Miod Vallat | |
| 2007-12-25 | Do not make struct pmap visible unless _KERNEL. | Miod Vallat | |
| 2007-12-25 | Restart the m88110 floating-point trap code from scratch, basing it on the | Miod Vallat | |
| sparc{,64} floating-point emulator, adapted to the 88110 specifics. Handling of these traps is now entirely done in C for convenience. Although there are a few rounding issues to address, and the XRF is ignored, this allows all the ieee754 regression tests to pass (lib/libc/ieeefp, sys/kern/signal/fpsig, sys/kern/signal/sigfpe). | |||
| 2007-12-22 | Make sure we have a real stack when invoking getipl() during exceptions. | Miod Vallat | |
| Fits in the brown-paperbag bug category. | |||
| 2007-12-22 | Move initial PSR initialization to a separate routine, instead of duplicating | Miod Vallat | |
| it five times. | |||
| 2007-12-21 | Change the EF_xxx constants to be real offsets within the trapframe, instead | Miod Vallat | |
| of offsets / sizeof(register_t), and nuke the REG_OFF macro. No functional change. | |||
| 2007-12-20 | Get rid of disable_interrupt() and have caller use get_psr() and set_psr(); | Miod Vallat | |
| this allows us to get rid of the dependency of asm_macro.h on asm.h, which was really only there to bring in psl.h. | |||
| 2007-12-20 | Do not protect this file with _KERNEL; other header files which include it do it | Miod Vallat | |
| in a _KERNEL-only section, and we want to eventually be able to use it from the bootblocks. | |||
| 2007-12-20 | Flush the source page before copying in pmap_copy_page(). This should not | Miod Vallat | |
| be necessary, but not doing it appears to break 88204 (not 88200) and split CMMUs. | |||
| 2007-12-15 | Since the 88110 can not invalidate a particular tlb entry, do not stack | Miod Vallat | |
| invalidate tlb ipis, and turn them into simple ``handle once'' ipis. | |||
| 2007-12-15 | Move the cmmu lock back from 8820x-specific code to global, and use it on | Miod Vallat | |
| MVME197DP to serialize 88410 operations. | |||
| 2007-12-12 | Make non-88110 kernels (aviion, luna88k) kernels compile again. | Miod Vallat | |
| 2007-12-09 | I honestly do not remember what 88110 errata convinced me to disable | Miod Vallat | |
| out-of-order (superscalar) execution on these processors. Since OoO brings a nice 50% to 250% speedup (as shown by ``openssl speed''), it is definitely worth enabling. | |||
| 2007-12-08 | Better siginfo fault codes for floating point exceptions on 88110, with | Miod Vallat | |
| more work in progress to handle these exceptions correctly, and document a new undocumented and evil chip bug while there. | |||
| 2007-12-08 | Do not pass a siginfo_t * pointer to the signal handler if no siginfo | Miod Vallat | |
| is required. | |||
| 2007-12-05 | Make the CPU_88100 and CPU_88110 constants match the architectural number | Miod Vallat | |
| field from the processor identification register; this allows .S code which needs to decide on the cpu type at runtime to check quicker, without needing to access memory. No functional change. | |||
| 2007-12-05 | In dma_cachectl(), when flushing line by line, only invoke pmap_extract() | Miod Vallat | |
| once per page and cache the result. | |||
| 2007-12-05 | xmem can not be used as a reliable atomic operation, they way we do them, | Miod Vallat | |
| so do the naive operations with interrupts disabled, and an interlock held if MULTIPROCESSOR. | |||
| 2007-12-04 | Work in progress SMP code for 88110 processor using the BusSwitch chip as | Miod Vallat | |
| an IPI facility, for MVME197DP. It's still missing a few remote cache IPIs and IPI do not seem to be reliably triggered on remote processors at the moment (but this could be a problem on the board I am currently testing on), at least it will boot multiuser using only cpu0 to schedule processes. | |||
| 2007-12-04 | In double_reg_fixup(), do not rely on tf_r[0] being zero. | Miod Vallat | |
| 2007-12-04 | Improve setregs() so that it performs the equivalent of the first two | Miod Vallat | |
| instructions of the new binary, which allows them to be skipped unconditionaly. | |||
| 2007-12-04 | Faster splassert_check() | Miod Vallat | |
| 2007-12-04 | Fix userland vs system test in errata #16 handling. | Miod Vallat | |
| 2007-12-02 | Do not take biglock for NOLOCK system calls. | Miod Vallat | |
| 2007-12-02 | Only check for errata #16 for instruction faults. | Miod Vallat | |
| 2007-12-02 | Remove 88110 control registers accessors which are never used anywhere. | Miod Vallat | |
| 2007-12-02 | The beginning of a real floating-point exception handler for the 88110. The | Miod Vallat | |
| existing code to enable TCFP was broken, as it was not setting the TCFP bit in the right register. So far, the exception handler will deliver SIGFPE in all cases. It will eventually do the necessary rounding, and handle the odd-numbered register pair operation, as I get time to write this (or see how much can be lifted from the 88100 floating-point exception code). | |||
| 2007-12-02 | Do not pass UPAGES and USPACE (under the name USIZE) in assym.h, code which | Miod Vallat | |
| needs it includes <machine/param.h> already. | |||
| 2007-12-02 | Since the 88110 doesn't disable the FPU when handling an exception (and does | Miod Vallat | |
| not need to), do not try to handle exceptions occuring when we re-enable shadowing as special - these are just nested exceptions. While there, add a workaround for the 88110 rte errata (#18). | |||
| 2007-12-02 | Sort and clean definitions. No functional changes. | Miod Vallat | |
| 2007-12-02 | When setting up the vectors page, do not put a nop as the first instruction | Miod Vallat | |
| if the processor is a 88110, since only the 88100 suffers from the ``will fetch one instruction too far'' bug. | |||
| 2007-12-02 | Provide faster bcopy() and bzero() routines for pmap_copy_page() and | Miod Vallat | |
| pmap_zero_page(). | |||
| 2007-12-02 | Provide a specific rw_cas() function for MP kernels, simulating a really | Miod Vallat | |
| atomic compare-and-swap operation. | |||
| 2007-12-02 | Rework the __mp_lock code to not spin at spllock(), kinda similar to the | Miod Vallat | |
| x86 __mp_lock changes, but keeping the internal __cpu_simplelock_t to guarantee atomic access to the __mp_lock fields. | |||
| 2007-12-02 | Change DAE processing so that the C code no longer needs the EF_xxx defines | Miod Vallat | |
| from assym.h. | |||
| 2007-11-25 | libkern, begone. Move to a new mechanism where config(8)'s "file" | Theo de Raadt | |
| directive can select between MI and MD versions of these files. At the same time, adjust the boot programs to pick exactly what they need, instead of the 7 or 8 mechanisms previously used. There will be some fallout from this, but testing it all by myself is a ridiculously slow process; it will be finished in-tree. Various developers were very nice and avoided making fun of me when I was gibbering in the corner.. | |||
| 2007-11-25 | spelling fixes, from Martynas Venckus; | Jason McIntyre | |
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