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completed; this used to be the case, but revision 1.25 of this file, close
to four years ago, changed this behaviour by mistake. The side effects of this
mishandling of the cache did not show up until the kernel memory allocation
strategy moved towards fast reuse of freed pages.
Took me a while to track this down, maybe I'm getting too old to write code,
I probably should write backdoors instead.
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a physical address [more precisely, something suitable to pass to pmap_enter()'sphysical address argument].
This allows MI drivers to implement mmap() routines without having to know
about the pmap_phys_address() implementation and #ifdef obfuscation.
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the one used by the firmware, which (at least on mvme88k) is at address zero.
This is unfortunate, since this means that NULL pointer dereferences in the
kernel are not caught, and writes cause havoc.
This behaviour was necessary to be able to use the PROM system call interface
during early bootstrap, without having to disassemble the VBR page and
update branches - which use pc-relative displacement - if we were to use
a different VBR address.
On mvme88k, change this and actually set up two VBR pages: one, over the PROM
page (except for the system call vectors), and another one in the kernel
image (which will be mapped read-only). We'll run with the PROM page until
the end of autoconf, and then switch to the kernel one, and unmap all the
PROM below it.
As a bonus, the final kernel page can use optimized data access fault
handlers, which do not have to check for faults caused by badaddr(), since
badaddr() is only used during device probe on buses which do not support
hotplug.
There are a few infrastructure collateral damage on aviion and luna88k, but
these ports do not change their behaviour yet.
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may be invoked with an address under the kernel text and we're about to
stop having such pages always mapped.
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statistics. This allows these mappings to be removed with pmap_kremove()
without messing with accounting.
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for it. This makes the netisr a real C function which will help further
development. No noticable performance change on i386 and amd64.
With input from kettenis@ and miod@ additional OKs mikeb@ and henning@
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``invalid opcode'' in kernel mode after being idle for a few hours, since
many months already. This panic does not make sense.
Recently, I've been able to gather enough samples and, looking at the
instructions surrounding the panic location, I have narrowed a pattern,
and I'll conveniently blame these panics upon a (to the best of my
knowledge) new genuine 88110 bug.
The exception handler will now recognize this situation and apply a large
hammer of workaround - probably not the best workaround that could be devised,
but it's short, easy to implement, and works 100% of the time so far. Besides,
since the machine is idle, who cares as long as it keeps running?
(the curious reader will find more information in the trap.c comments)
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its better as a per arch MD define anyway. all default to MAXDSIZ as before.
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implement them, and they are of questionable usefulness.
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provides an inline version of it.
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to complete matthew@'s commit of a few days ago, and drop __HAVE_CPU_MUTEX_LEVEL
define. With help from, and ok deraadt@.
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it defines. In some cases, this means pulling in uvm.h or pcb.h
instead, but most of the inclusions were just noise. Tested on
alpha, amd64, armish, hppa, i386, macpcc, sgi, sparc64, and vax,
mostly by krw and naddy.
ok krw@
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This is a leftover from a very old workaround for a very old and long gone
pmap_enter() bug.
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on 88110 designs. Brings a ~8% speedup on GENERIC.MP on 197DP.
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ok miod@
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On AViiON systems with the 6:1 CMMU:CPU configuration, force cached
mappings to be writethrough - this probably hides a bug in the code, but
that's the only way so far to get such a system running stably.
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Also features support for {awkw,bast}ard 6:1 CMMU:CPU configurations (4I2D).
Tested on model 4605, which runs up to cpu_initclocks(), which is not written
for this system family yet. No regression on model 4300.
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ok miod@
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rather than defining it separately for each architecture.
Also set it to 4, to accommodate for future UTF-8 support (rfc3629).
Diff by stsp, committing to catch the libc major bump
ok kettenis@, guenther@
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ok jsing@, miod@
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processor, since caches are physically addressed and we are working on physical
addresses.
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Ok oga@, "the time is now" deraadt@.
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currently active userland pmap in each processors struct cpu_info.
This thus skips the complete tlb flush if idle switches back to
the proc previously running on this processor.
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landisk, and the sparc implementation is obviously wrong. That's where I
stopped looking, so who knows what else was broken. A simple comparison of
the existing mtx_enter with the new mtx_enter_try would have told anybody.
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using this soon(ish). Ok oga@, sorta yes kettenis@.
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MULTIPROCESSOR.
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MD code would free resources that couldn't be freed until we were no
longer running in that processor. However, it's is unused on all
architectures since mikeb@'s tss changes on x86 earlier in the year.
ok miod@
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with different locking mechanism. 88110 soft ipi are replaced with an
ipi callback which is checked upon return from exception (it can not be kept
as a softintr, as the generic softinterrupt code doesn't have per-cpu
pending softintr queues).
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levels. This will allow for platforms where soft interrupt levels do not
map to real hardware interrupt levels to have soft ipl values overlapping
hard ipl values without breaking spl asserts.
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flushing the whole TLB block every time a pte is modified, store a bitmask
of pending flushes and do them at pmap_update() time. 88100 behaviour is
unchanged.
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exchange with zero; use it in the soft interrupt code to make it simpler
and faster.
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Rework nmi handling to handle ``complex'' NMI faster, and return as fast as
possible from the exception, without doing the AST and softintr dance.
This should avoid too much stack usage under load.
ok deraadt@
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to disable NMI sources in addition to interrupt sources, and we can not
use a quick sequence with shadowing frozen as done for atomic ops.
This lets GENERIC.MP boot multiuser on MVME197DP boards, and is so far stable
enough to be able to recompile a kernel from scratch (with make -j2).
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since it was intended to service NMI occuring in user mode, and we could
end up invoking preempt() and have another cpu start using this stack,
with interesting results.
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can be interrupted by NMI; move the SMP version of these routines from
inlines to a separate file (kernel text shrinks 20KB...).
Since the implementation for 88110 becomes really hairy, the pre-main() code
is responsible for copying the appropriate code over for kernels configured
for both 88100 and 88110 cpus, to avoid having to choose the atomicity
strategy at runtime. Hairy, I said.
This gets GENERIC.MP run much further on 197DP. Not enough to reach multiuser
mode, but boots up to starting sshd and then panics.
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xmem didn't return the expected value, spin doing regular loads until it
appears we have a chance to grab the lock again.
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synchronizes the pipeline on 88110.
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- dma_cachectl() split into a ``local cpu only'' and ``all cpus'', and an ipi
to broadcast ``local dma_cachectl'' is added.
- cpu_info fields are rearranged, to have the 88100-specific information
and the 88110-specific information overlap, and has many more 88110
ugly things.
- more ipi handling in the 197-specific area. Since it is not possible to
have the second processor receive any hardware interrupt (selection
is done on a level basis via ISEL, and we definitely do not want the
main cpu to lose interrupts), the best we can do is to inflict ourselves
a soft interrupt for late ipi processing. It gets used for softclock and
hardclock on the secondary processor, but since the soft interrupt
dispatcher doesn't have an exception frame, we have to remember parts
of it to build a fake clockframe from the soft ipi handler (ugly but
works).
This now lets GENERIC.MP run a few userland binaries before bugs trigger.
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from interrupt() and related function pointers.
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now set up both the exception frame structure and the exception stack as
soon as possible, so that we can safely get interrupted by an NMI as soon
as we reenable shadowing.
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this defeats the purpose of having a separate stack at this point... Oopsie
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