src - OpenBSD base system

Age	Commit message (Collapse)	Author
2012-09-29	Basic R8000 processor support. R8000 processors require MMU-specific code,	Miod Vallat
	exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split.
2012-04-21	Correct a wrong comment.	Miod Vallat

2011-03-23	Normalize sentinel. Use _MACHINE__H_ and _<ARCH>__H_ properly and consitently.	Paul Irofti
	Discussed and okay drahn@. Okay deraadt@.
2010-09-19	Overhaul ddb disassembler to recognize all MIPS IV instructions, as well as	Miod Vallat
	some mips64r2 instructions. Various bugfixes all over as well (conditional trap instructions do not have a delay slot, for instance).
2010-09-17	Recognize MIPS IV extra FPU condition codes in MipsEmulateBranch().	Miod Vallat

2010-09-17	There is only one code for coprocessor BC opcodes, so don't bother to handle	Miod Vallat
	a second (invalid) opcode; confirmed by all mips core documentation.
2005-08-07	Remove advertising clause from UCB licenses; ok deraad@	Miod Vallat

2004-08-06	initial mips64	Per Fogelstrom