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path: root/sys/arch/mips64/include
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2018-04-09Add a driver for the OCTEON cryptographic unit. It providesVisa Hankala
a hardware-accelerated implementation of several encryption and authentication algorithms for ipsec(4): AES-CBC AES-CTR AES-GCM AES-GMAC HMAC-MD5 HMAC-SHA1 HMAC-SHA2-256 HMAC-SHA2-384 HMAC-SHA2-512 Please note that the driver is currently disabled. OK deraadt@
2018-03-05#define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archTheo de Raadt
needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
2018-02-24Declare ci_ipl volatile to prevent the compiler from optimizingVisa Hankala
or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
2018-01-29Drop unused field `ci_ipiih'.Visa Hankala
2018-01-25Move common mutex implementations to a MI place.Martin Pieuchot
Archs not yet converted can to the jump by defining __USE_MI_MUTEX. ok visa@
2018-01-12Unify <machine/mutex.h> a bit further.Martin Pieuchot
`mtx_owner' becomes the first field of 'struct mutex' on i386/amd64/arm64. ok visa@
2018-01-08Move SC_* defines into <machine/setjmp.h>, and rename them,Visa Hankala
so that <machine/signal.h> is not needed in setjmp.S. Suggested by kettenis@ long ago, OK deraadt@
2018-01-04Unify <machine/mutex.h> a bit further.Martin Pieuchot
Remove `mtx_lock' from i386, add volatile before `mtx_owner' where it was missing. Inputs from kettenis@, ok visa@
2017-10-21Use MI mplock on mips64.Visa Hankala
OK mpi@
2017-09-05Move mutex, condvar, and thread-specific data routes, pthread_once, andPhilip Guenther
pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
2017-09-02Let the kernel utilize the FPU if one is available, even when theVisa Hankala
FPUEMUL option is enabled. This benefits OCTEON III systems which can run floating-point operations natively. Feedback from and OK miod@; he also helped with testing. Tested on octeon without FPU (CN5020, CN6120) and with FPU (CN7130), as well as on sgi/IP27 (MP R16000), sgi/IP32 (R5000), and loongson (3A1000).
2017-08-27Rely on the hardware to clear hazards on octeon.Visa Hankala
2017-08-26Use macros for Config1 bits.Visa Hankala
2017-08-13Make R_MIPS_* defines available via <machine/reloc.h>.Visa Hankala
OK guenther@
2017-08-12Add a dummy (for now) <machine/reloc.h> for mips64 to fix build.Visa Hankala
OK guenther@
2017-07-30Define MAXCPUS per mips64 port.Visa Hankala
2017-07-12remove CPU_LIDSUSPEND/machdep.lidsuspendMartin Natano
"fire away!" tedu
2017-06-29kill RCSID macros; discussed with millertTheo de Raadt
2017-06-11Fix TLB size computation on OCTEON II and III. The CPUs have utilizedVisa Hankala
the whole TLB space even before this. However, TLB initialization on boot and TLB flush on ASID wraparound have been incomplete. These have caused crashes of processes.
2017-06-08Move loongson/octeon/sgi unmap_startup() under arch/mips64.Visa Hankala
2017-05-24Add an idle cycle implementation for R4600/R5000/RM7000 CPUs and theirVisa Hankala
derivatives. This lets the kernel utilize the CPUs' Standby Mode to reduce the power consumption of an idle system. Suggested by and input from miod@. He also tested this patch on an RM7000 O2.
2017-05-19Replace __cpu_cas() with atomic_cas_ulong().Visa Hankala
OK kettenis@
2017-05-15Make atomic.h ready to be included in userland.Martin Pieuchot
- keep setbits/clearbits inside _KERNEL ok visa@
2017-05-10Hook up HPET as a timecounter.Visa Hankala
2017-04-20Get TCB address using the RDHWR instruction instead of __get_tcb().Visa Hankala
This gives fast access to the address on systems that implement the UserLocal register. TCB caching is still used when running in the single-threaded mode in order not to penalize old systems. The kernel counterpart of this change must be in place before using this diff! With guenther@
2017-04-20Make TCB address available to userspace via the UserLocal register.Visa Hankala
This lets programs get the address without a system call on OCTEON II and later. Add UserLocal load emulation for systems that do not implement the RDHWR instruction or the UserLocal register. OK guenther@
2017-04-20Hook up mutex(9) to witness(4).Visa Hankala
2017-04-13Provide mips64 with kernel-facing TCB_{GET,SET} macros that store itPhilip Guenther
in struct mdproc. With that, all archs have those and the __HAVE_MD_TCB macro can be unifdef'ed as always defined. ok kettenis@ visa@ jsing@
2017-04-10Use __ASSEMBLER__ instead of __LANGUAGE_ASSEMBLY.Visa Hankala
The latter is not defined by clang. OK guenther@, kettenis@
2017-04-07Add prid for CN72xx/CN73xx.Visa Hankala
2017-03-02Add a new sysctl machdep.lidaction. The sysctl works as follows:Martin Natano
machdep.lidaction=0 # do nothing machdep.lidaction=1 # suspend machdep.lidaction=2 # hibernate lidsuspend is just an alias for lidaction, so if you change one, the other one will have the same value. The plan is to remove machdep.lidsuspend eventually when people have upgraded their /ets/sysctl.conf. discussed with deraadt, who came up with the new MIB name no objections mlarkin ok stsp halex jcs
2017-02-08In exec_elf.c: expand ELFNAME(), ELFNAME2(), and ELFNAMEEND() exceptPhilip Guenther
leaving out the size, so that ELFNAME2(exec,makecmds) becomes exec_elf_makecmds instead of exec_elf{32,64}_makecmds and then delete the ELFNAME2() and ELFNAMEEND() macros. Move the prototypes for functions local to exec_elf.c to there from exec_elf.h. Simplify the SMALL_KERNEL conditionals around the ELF coredump code. Change exec_conf.c to use the size-generic names and macros Remove exec_elf{32,64}.c and just build exec_elf.c; delete the _KERN_DO_ELF and _KERN_DO_ELF64 #defines. ok jca@, encouragement from deraadt@ and tom@
2017-01-21Add _MIPS_ISA_MIPS32 and _MIPS_ISA_MIPS64 defines for clang.Visa Hankala
OK deraadt@ phessler@ mpi@
2017-01-03Remove #define __SWAP_BROKEN from mips64. The architecture nowVisa Hankala
has a proper pmap_collect() implementation, and the current uvm_swapout_threads() code does not need other MD interfaces. OK miod@
2016-12-23Tweaks suggested by miod@Visa Hankala
2016-12-22Extend the size of user virtual address space from 2GB to 1TB on mips64Visa Hankala
by adding another level to page directories. This improves ASLR and complements W^X added earlier on some systems, giving a notable update to the architecture's security. Besides, there is now more room for running tasks that hog memory. Testing help from deraadt@ and fcambus@. Platforms tested: loongson, octeon, sgi/IP27 and sgi/IP30 (IP30 also with 4KB pages).
2016-12-21Add a driver for OCTEON MMC host controller.Visa Hankala
Tested on EdgeRouter Pro, and Shasta. OK mpi@
2016-12-17Make Octeon model strings a bit more specific. While there,Visa Hankala
add CN70xx/CN71xx.
2016-12-16Provide the "machdep.lidsuspend" sysctl on Loongson.Frederic Cambus
OK visa@
2016-12-12Tweak IPI register definitions.Visa Hankala
2016-12-06Get PTE shift using PTE_LOG.Visa Hankala
2016-11-06Add interrupt handling routines for Loongson 3A.Visa Hankala
Feedback from miod@
2016-10-09Do not use MIPS64r2 instructions on Loongson 2. Now, a generic loongsonVisa Hankala
kernel has to learn a new trick in order to use TLB RI/XI on 3A2000.
2016-09-06Define PTE_* macros in one place. Use the lwu instruction for 32-bit PTEVisa Hankala
loads on all systems as the TLB code does not need sign extension.
2016-09-03Increase the number of mbufs on most architectures. This is basedAlexander Bluhm
on a guess how much memory a typical machine has. If the value is too high, users may run out of kernel memory. Then we will have to adjust this again. OK claudio@ deraadt@
2016-08-16Remove RM7000/RM9000-specific performance counter code. It originatesVisa Hankala
from PMON2000 and has not been enabled on OpenBSD. Suggested by and ok miod@ (after seeing a quad_t cleanup patch of mine)
2016-08-14Utilize the TLB Execute-Inhibit bit with non-executable mappings on CPUsVisa Hankala
that support the Execute-Inhibit exception. This makes user space W^X effective on Octeon Plus and later Octeon versions. Feedback from miod@, thanks! No objection from deraadt@
2016-08-06Add PageGrain bits.Visa Hankala
2016-05-11Another attempt to make the mips64 pmap MP-safe. Now at leastVisa Hankala
pmap_enter(9), pmap_remove(9) and pmap_page_protect(9) should be safe to use without the kernel lock. No objection from deraadt@
2016-05-10SROP mitigation. sendsig() stores a (per-process ^ &sigcontext) cookieTheo de Raadt
inside the sigcontext. sigreturn(2) checks syscall entry was from the exact PC addr in the (per-process ASLR) sigtramp, verifies the cookie, and clears it to prevent sigcontext reuse. not yet tested on landisk, sparc, *88k, socppc. ok kettenis
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