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path: root/sys/arch/mips64/include
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2014-01-30Move declaration of struct vm_page_md from <machine/vmparam.h> toMiod Vallat
<machine/pmap.h> where it belongs, and compensate in <uvm/uvm_extern.h> by including <uvm/uvm_pmap.h> before <uvm/uvm_page.h>. Tested on all MACHINE_ARCH but amd64 and i386 (and hppa64).
2014-01-24Do not protect struct vm_page_md with defined(_KERNEL), for userland uvmMiod Vallat
grovellers need to know it to be able to get the right size for struct vm_page.
2014-01-23unifdef -D__HAVE_VM_PAGE_MD - no functional change.Miod Vallat
2013-12-19recognize octeon 2 cpus; as found in the lanner mr326Jasper Lievisse Adriaanse
ok miod@
2013-12-18Provide MI symbol _STACKALIGNBYTESTheo de Raadt
2013-07-13unify register_t to long on all platformsTheo de Raadt
ok miod kettenis
2013-07-05Take II, this time without flubbing off_t: : move several internalPhilip Guenther
type definitions that are the same across all archs from <machine/_types.h> to <sys/_types.h> ok deraadt@ kettenis@ otto@
2013-07-04backout previous; off_t must be signed and there might be other C++ APIOtto Moerbeek
breakage lurking; ok kettenis@
2013-07-04To ease future changes, move several internal type definitions that arePhilip Guenther
the same across all archs from <machine/_types.h> to <sys/_types.h> ok deraadt@
2013-06-01cleanup and consolidate the spinlock_lock (what a name!) code.Ted Unangst
it's now atomic_lock to better reflect its usage, and librthread now features a new spinlock that's really a ticket lock. thrlseep can handle both types of lock via a flag in the clock arg. (temp back compat hack) remove some old stuff that's accumulated along the way and no longer used. some feedback from dlg, who is concerned with all things ticket lock. (you need to boot a new kernel before installing librthread)
2013-05-29Add PMAP_PA_MASK to mips64. Needed for loongson hibernate.Paul Irofti
Okay miod@.
2013-05-21remove unused cpu_lock code (where it is truly unused). it is notTed Unangst
part of the future we have planned. middling ok from a few
2013-03-28Add STRONG_ALIAS macros to be used from assembly code in libc andMartynas Venckus
libm. While at it, remove now unused workarounds for lint. Agreed by kettenis@, guenther@, matthew@.
2013-03-28Add __strong_alias macros for all architectures to be able to aliasMartynas Venckus
another symbol without weak attribute. To be used in libc and libm soon. Agreed by kettenis@, guenther@, matthew@.
2013-03-26PGSHIFT and PGOFSET are now contained inside the kernel namespace.Theo de Raadt
2013-03-25PGSHIFT -> PAGE_SHIFTTheo de Raadt
2013-03-25ALIGNBYTES/ALIGN/ALIGNED_POINTER can move to the MI file.Theo de Raadt
2013-03-23refactor sys/param.h and machine/param.h. A lot of #ifdef _KERNEL is addedTheo de Raadt
to keep definitions our of user space. The MD files now follow a consistant order -- all namespace intrusion is at the tail can be cleaned up independently. locore, bootblocks, and libkvm still see enough visibility to build. Checked on 90% of platforms...
2013-03-12Fix kernel profiling on MP systems by using per-CPU buffers and teachMartin Pieuchot
kgmon(8) to deal with them, this time without public header changes. Previously various CPUs were iterating over the same global buffer at the same time to modify it and never ended. This diff includes some ideas submited by Thor Simon to NetBSD via miod@. ok deraadt@, mikeb@, haesbaert@
2013-02-12Back out per-CPU kernel profiling, it shouldn't modify a public headerMartin Pieuchot
at this moment.
2013-02-11Fix kernel profiling on MP systems by using per-CPU buffer. PreviouslyMartin Pieuchot
various CPUs were iterating over the same global buffer at the same time to modify it and never ended. This diff includes some ideas submited by Thor Simon to NetBSD via miod@. ok mikeb@, haesbaert@
2013-02-09No longer define EXEC_SCRIPT (probably coming from old PefoBSD). Also,Miod Vallat
DB_ELFSIZE ought to be defined in <machine/db_machdep.h>, not <machine/exec.h>
2013-01-16On second thought, do not unconditionnaly register the cpu throttling codeMiod Vallat
on all Loongson2F systems yet; Gdium does not have a separate scheduling clock yet and can't afford throttling until then.
2012-12-05Remove excessive sys/cdefs.h inclusionTheo de Raadt
ok guenther millert kettenis
2012-12-04Only pull in sys/cdefs.h if neededTheo de Raadt
ok miod
2012-12-02Determine whether we're currently on the alternative signal stackPhilip Guenthe
dynamically, by comparing the stack pointer against the altstack base and size, so that you get the correct answer if you longjmp out of the signal handler, as tested by regress/sys/kern/stackjmp/. Also, fix alt stack handling on vax, where it was completely broken. Testing and corrections by miod@, krw@, tobiasu@, pirofti@
2012-11-05unifdef -D __HAVE_TIMECOUNTERMiod Vallat
2012-10-03Do not use <mips64/archtype.h> for loongson model numbers, but rather put theMiod Vallat
list in loongson's <machine/autoconf.h> directly. <mips64/archtype.h> is intended to be only used on ARCBios-like platforms.
2012-10-03Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,Miod Vallat
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interest to a handful set of files; this is similar in spirit to what alpha does, but here <machine/cpu.h> does not include the new file.
2012-09-29Do not hardcode ARCBios vector base, but rather compute it at runtime.Miod Vallat
This allows MI code to support both 32-bit ARCS systems, as well as 64-bit R8000 and R1x000 systems. While there, #if 0 out ARCBios routines currently not used by the kernel.
2012-09-29Basic R8000 processor support. R8000 processors require MMU-specific code,Miod Vallat
exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split.
2012-09-29Forgot this in previous commitMiod Vallat
2012-09-29Handle the coprocessor 0 cause and status registers as a 64 bit value now,Miod Vallat
as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used.
2012-09-29Add a few more coprocessor 0 cause and config registers defines.Miod Vallat
2012-09-29Kill the mostly unused VMTLB_xxx and VMNUM_xxx defines. Move all tlbMiod Vallat
knowledge to <machine/pte.h>. Add specific routines for tlb handling setup (at cpu initialization time) and tlb ASID wrap.
2012-09-29Introduce assembly macros for specific processor hazards: tlb update, statusMiod Vallat
register update, status register update causing a change to the interrupt enable flag, and a few other arcane ones. <mips64/asm.h> will provide (supposedly sane) defaults, and <machine/asm.h> may override these with better tuned versions. Use these macros instead of random strings of nop in the various .S files requiring hazard workarounds.
2012-09-29Provide a few more macros in <machine/asm.h> to wrap coprocessor 0Miod Vallat
move from/to register instructions, as well as a NOP macro. These will be used in a later diff to allow specific processors to use slightly different instructions or encodings.
2012-09-29Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofMiod Vallat
such statements with it.
2012-09-11Remove the 'OLF method' used for the transition from a.out to ELF andTheo de Raadt
for all the compat layers which are now gone. Linux compat still works because it always used another method in any case, and nothing looks at p_os anymore. ok jsing
2012-07-14Split the existing mips64 clock code into time-of-day and generic duties inMiod Vallat
machdep.c, and internal clock interrupting on level 5, still in clock.c; this will allow other clock sources to be used in the near future. (delay() will remain tied to the internal clock)
2012-06-26create new machine/_float.h which is namespace clean. create a newTheo de Raadt
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-24Do not output unnecessary semicolons when expanding macros. No functional changeMiod Vallat
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousMiod Vallat
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-23Fix ITLBNOPFIX macro definition on RM7000-capable kernels, and use itMiod Vallat
in cp0_set_config() for consistency.
2012-05-27Add a `L2 cache line size' member to struct cpu_info. This allows R4k code toMiod Vallat
stop abusing another field, and will be used by more routines RSN. No functional change.
2012-05-10The uvm_map() changes introduced about two months ago yield a differentMiod Vallat
memory allocation pattern, exposing aliasing bugs in the mips64 pmap, on kernels where virtual aliasing may happen (that is, IP32 kernels on R5000, R10000 and R12000 O2). Fix these (or at least, sweep them better under the rug) by: - always flush caches in pmap_copy_page() and pmap_zero_page(), if the destination page is mapped uncached. - when removing a mapping of a managed page which has been forced uncached due to virtual aliasing conflict, map it back cached as soon as the remaining mappings are non conflicting. - writeback, instead of simply invalidating, pool pages and page table pages, upon release, for there might be stale data in the cache. While these, apply more paranoia and only perform cache operations on pages which have been mapped with the cache enabled. Initially reported by mikeb@ on an R12k O2 (that will teach me to use an RM7000-powered O2, without virtual aliasing, to test IP32 kernels). Verified on an R5k O2, as well as a custom IP30 kernel with page size forced to 4KB (to introduce virtual aliasing). This diff tested on O2 (R5k, RM7k, R12k), IP30, IP35, as well as on Loongson (no aliasing) by mikeb@ and I.
2012-04-24Add support for wired mappings, using the last unused bit in the PTE.Miod Vallat
2012-04-24Introduce a #define for the number of PFN bits in a pte, to be used in theMiod Vallat
.S code when masking the upper bits, instead of hardcoding them. Makes code easier to understand (and also I might have a need to reduce PFN width on some particular CPU models in the future). No change in generated code.
2012-04-21Correct a wrong comment.Miod Vallat
2012-04-21Rework the signature of the cache handling routines again. It makes more senseMiod Vallat
to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.
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