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2012-12-05Remove excessive sys/cdefs.h inclusionTheo de Raadt
ok guenther millert kettenis
2012-12-04Only pull in sys/cdefs.h if neededTheo de Raadt
ok miod
2012-12-02Determine whether we're currently on the alternative signal stackPhilip Guenthe
dynamically, by comparing the stack pointer against the altstack base and size, so that you get the correct answer if you longjmp out of the signal handler, as tested by regress/sys/kern/stackjmp/. Also, fix alt stack handling on vax, where it was completely broken. Testing and corrections by miod@, krw@, tobiasu@, pirofti@
2012-11-05unifdef -D __HAVE_TIMECOUNTERMiod Vallat
2012-10-03Do not use <mips64/archtype.h> for loongson model numbers, but rather put theMiod Vallat
list in loongson's <machine/autoconf.h> directly. <mips64/archtype.h> is intended to be only used on ARCBios-like platforms.
2012-10-03Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,Miod Vallat
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interest to a handful set of files; this is similar in spirit to what alpha does, but here <machine/cpu.h> does not include the new file.
2012-09-29Do not hardcode ARCBios vector base, but rather compute it at runtime.Miod Vallat
This allows MI code to support both 32-bit ARCS systems, as well as 64-bit R8000 and R1x000 systems. While there, #if 0 out ARCBios routines currently not used by the kernel.
2012-09-29Basic R8000 processor support. R8000 processors require MMU-specific code,Miod Vallat
exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split.
2012-09-29Forgot this in previous commitMiod Vallat
2012-09-29Handle the coprocessor 0 cause and status registers as a 64 bit value now,Miod Vallat
as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used.
2012-09-29Add a few more coprocessor 0 cause and config registers defines.Miod Vallat
2012-09-29Kill the mostly unused VMTLB_xxx and VMNUM_xxx defines. Move all tlbMiod Vallat
knowledge to <machine/pte.h>. Add specific routines for tlb handling setup (at cpu initialization time) and tlb ASID wrap.
2012-09-29Introduce assembly macros for specific processor hazards: tlb update, statusMiod Vallat
register update, status register update causing a change to the interrupt enable flag, and a few other arcane ones. <mips64/asm.h> will provide (supposedly sane) defaults, and <machine/asm.h> may override these with better tuned versions. Use these macros instead of random strings of nop in the various .S files requiring hazard workarounds.
2012-09-29Provide a few more macros in <machine/asm.h> to wrap coprocessor 0Miod Vallat
move from/to register instructions, as well as a NOP macro. These will be used in a later diff to allow specific processors to use slightly different instructions or encodings.
2012-09-29Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofMiod Vallat
such statements with it.
2012-09-11Remove the 'OLF method' used for the transition from a.out to ELF andTheo de Raadt
for all the compat layers which are now gone. Linux compat still works because it always used another method in any case, and nothing looks at p_os anymore. ok jsing
2012-07-14Split the existing mips64 clock code into time-of-day and generic duties inMiod Vallat
machdep.c, and internal clock interrupting on level 5, still in clock.c; this will allow other clock sources to be used in the near future. (delay() will remain tied to the internal clock)
2012-06-26create new machine/_float.h which is namespace clean. create a newTheo de Raadt
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-24Do not output unnecessary semicolons when expanding macros. No functional changeMiod Vallat
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousMiod Vallat
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-23Fix ITLBNOPFIX macro definition on RM7000-capable kernels, and use itMiod Vallat
in cp0_set_config() for consistency.
2012-05-27Add a `L2 cache line size' member to struct cpu_info. This allows R4k code toMiod Vallat
stop abusing another field, and will be used by more routines RSN. No functional change.
2012-05-10The uvm_map() changes introduced about two months ago yield a differentMiod Vallat
memory allocation pattern, exposing aliasing bugs in the mips64 pmap, on kernels where virtual aliasing may happen (that is, IP32 kernels on R5000, R10000 and R12000 O2). Fix these (or at least, sweep them better under the rug) by: - always flush caches in pmap_copy_page() and pmap_zero_page(), if the destination page is mapped uncached. - when removing a mapping of a managed page which has been forced uncached due to virtual aliasing conflict, map it back cached as soon as the remaining mappings are non conflicting. - writeback, instead of simply invalidating, pool pages and page table pages, upon release, for there might be stale data in the cache. While these, apply more paranoia and only perform cache operations on pages which have been mapped with the cache enabled. Initially reported by mikeb@ on an R12k O2 (that will teach me to use an RM7000-powered O2, without virtual aliasing, to test IP32 kernels). Verified on an R5k O2, as well as a custom IP30 kernel with page size forced to 4KB (to introduce virtual aliasing). This diff tested on O2 (R5k, RM7k, R12k), IP30, IP35, as well as on Loongson (no aliasing) by mikeb@ and I.
2012-04-24Add support for wired mappings, using the last unused bit in the PTE.Miod Vallat
2012-04-24Introduce a #define for the number of PFN bits in a pte, to be used in theMiod Vallat
.S code when masking the upper bits, instead of hardcoding them. Makes code easier to understand (and also I might have a need to reduce PFN width on some particular CPU models in the future). No change in generated code.
2012-04-21Correct a wrong comment.Miod Vallat
2012-04-21Rework the signature of the cache handling routines again. It makes more senseMiod Vallat
to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.
2012-04-19Print the currently active ASID in `machine tlb' ddb command.Miod Vallat
2012-04-16Fix struct arc_param_blk_* layout to not embed pointers, as this messes theMiod Vallat
layout in 64-bit mode. Found the hard way, of course.
2012-04-15Tell Indy and Challenge S apart.Miod Vallat
2012-04-06Make the logic for PMAP_PREFER() and the logic, inside pmap, to do theMiod Vallat
necessary cache coherency work wrt similar virtual indexes of different physical pages, depending upon two distinct global variables, instead of a shared one. R4000/R4400 VCE requires a 32KB mask for PMAP_PREFER, which is otherwise not necessary for pmap coherency (especially since, on these processors, only L1 uses virtual indexes, and the L1 size is not greater than the page size, as we are using 16KB pages).
2012-04-06Rework IP22 RTC year base computation, again. It turns out that differentMiod Vallat
Indy PROM versions use different year bases - after all, using 1970 instead of the previously used value of 1940 smelled like a bug, and probably was, so this eventually got fixed in later PROM versions. Instead of hardcoding a year base depending upon the system, we will now ask ARCBios for its current year, and compare it to what can be read from the RTC registers to figure out what year base is in use by the PROM.
2012-03-28Work in progress support for the SGI Indigo, Indigo 2 and Indy systemsMiod Vallat
(IP20, IP22, IP24) in 64-bit mode, adapated from NetBSD. Currently limited to headless operation, input and video drivers will get ported soon. Should work on all R4000, R4440 and R5000 based systems. L2 cache on R5000SC Indy not supported yet (coming soon), R4600 not supported yet either (coming soon as well). Tested to boot multiuser on: Indigo2 R4000SC, Indy R4000PC, Indy R4000SC, Indy R5000SC, Indigo2 R4400SC. There are still glitches in the Ethernet driver which are being looked at. Expansion support is limited to the GIO E++ board; GIO boards with PCI-GIO bridges not ported yet due to the lack of hardware, and this kind of driver does not port blindly. Most of this work comes from NetBSD, polishing and integration work, as well as putting as many ``R4x00 in 64-bit mode'' erratas as necessary, by yours truly. More work is coming, as well as trying to get some easy way to boot install kernels (as older PROM can only boot ECOFF binaries, which won't do for the kernel).
2012-03-25Move cache handling routines related definitions to a dedicated header file,Miod Vallat
rather than abusing <machine/cpu.h>.
2012-03-24The various ConfigCache() functions actually return void, not int.Miod Vallat
2012-03-24Rename the various SGI_xxx constants from machine names to their IP numbers,Miod Vallat
for IP numbers under 30 (Octane), and add a few interesting ones. No functional change, except making my life easier for upcoming work.
2012-03-24Add a few trivial routines to get mips64r2 specific config registers. Not usedMiod Vallat
by anything yet, but has been lying in one of my trees for too long.
2012-03-19Use uncached addresses for all exception vectors, when copying our code (orMiod Vallat
trampolines) to them; this makes sure there is no risk of pending writes being lost when we clear the caches. Of course, this would be a bug in the cache handling routines, but having our vectors correctly set will help debugging the issue. Tested on sgi and loongson.
2012-03-15uncached_base was introduced early in IP27 support, since these designs useMiod Vallat
subspaces in the CCA_NC uncached memory space. However, being coherent, there was never a need for bus_dma to use uncached addresses. This means that, on the only systems where uncached_base was not set to PHYS_TO_XKPHYS(0, CCA_NC), it was never used. Remove the variable, and replace PHYS_TO_UNCACHED() with PHYS_TO_XKPHYS(, CCA_NC). No functional change.
2011-11-15label_t is the kernel setjmp buffer. It should simply be an array ofTheo de Raadt
the right type, noone will ever fiddle with the internals. discussed with jsing
2011-10-27Specify the TLS variant for each platform.Philip Guenthe
2011-09-08Provide namespace-safe alignment macros in <machine/_types.h>, withPhilip Guenthe
compat names kept in <machine/param.h>. In <sys/socket.h>, pull in <sys/_types.h> instead of the namespace polluting <machine/param.h> and completely eliminate __CMSG_ALIGN, replaced by _ALIGN ok deraadt@
2011-09-08Make the INT_FAST*_{MIN,MAX} macros match the types they're defined to.Philip Guenthe
Since the underlying types of the int_fast types are set by machine/_types.h, put internal macros in that same file and define the exposed INT_FAST*_{MIN,MAX} macros from those. ok millert@, kettenis@
2011-08-29Only provide FLT_EVAL_METHOD for C99. Add missing DECIMAL_DIG for C99.Mark Kettenis
ok guenther@
2011-07-21Support for the eBenton EBT-700 netbook, which is similar to the LemoteMiod Vallat
Yeeloong, but with a 7" display with a 800x480 resolution, and no webcam. There are still problems to get it booting from disk from PMON (colour me unsurprised), which are being looked at. Loading the boot blocks from a FAT USB stick, to then boot the kernel from the disk, is a reliable workaround in the meantime. Tested by Ban Keong Yee (bankeong dot yee on gmail) who is the ``lucky'' owner of such a machine, thanks for your time!
2011-06-24machdep.kbdreset enables a shutdown by Ctrl-Alt-Del on amd64 andChristian Weisgerber
i386. Stop abusing it on other archs for controling a shutdown by pressing the soft power button: * Add a MI sysctl hw.allowpowerdown; if set to 1 (the default) it allows a power button shutdown. * Make acpi(4)/acpibtn(4) honor hw.allowpowerdown. * Switch the various power button intercepts on landisk, sgi, sparc64 and zaurus over to hw.allowpowerdown. * Garbage collect the machdep.kbdreset sysctl on all archs other than amd64 and i386. ok miod@
2011-06-05Prefer __LP64__ to _LP64; pointed out by bradMiod Vallat
2011-05-30Remove the freelist member from vm_physsegOwain Ainsworth
The new world order of pmemrange makes this data completely redundant (being dealt with by the pmemrange constraints instead). Remove all code that messes with the freelist. While touching every caller of uvm_page_physload() anyway, add the flags argument to all callers (all but one is 0 and that one already used PHYSLOAD_DEVICE) and remove the macro magic to allow callers to continue without it. Should shrink the code a bit, as well. matthew@ pointed out some mistakes i'd made. ``freelist death, I like. Ok.' ariane@ `I agree with the general direction, go ahead and i'll fix any fallout shortly'' miod@ (68k 88k and vax i could not check would build)
2011-05-25Also enclose variable names with external linkage in __BEGIN_DECLS.Martynas Venckus
Doesn't matter much since C++ ABI used by GCC doesn't mangle variable names; however technically is required by Section 7.5 of the C++ spec. Discussed with/OK guenther@, matthew@.
2011-04-28Expose pmap_prefer parameters.Ariane van der Steldt
This will enable future uvm_map code to make intelligent decisions during allocation.
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