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2010-10-02Added octeon specific cop0 registers. ok miod@Takuya ASADA
2010-10-01Provide a WEAK_ALIAS macro in <machine/asm.h> for the few platformsPhilip Guenthe
that didn't already have one, and then immediately use it in libc's SYS.h ok miod@
2010-09-28Implement a per-cpu held mutex counter if DIAGNOSTIC on all non-x86 platforms,Miod Vallat
to complete matthew@'s commit of a few days ago, and drop __HAVE_CPU_MUTEX_LEVEL define. With help from, and ok deraadt@.
2010-09-21Replace the old floating point completion code with a C interface to theMiod Vallat
MI softfloat code, implementing all MIPS IV specified floating point operations. Tested on R5000, R10000, R14000 and Loongson2F.
2010-09-20Make md_printins() get the printf-like function as an extra parameter, andMiod Vallat
make it visible so that md parts of the kernel can use it for debug messages.
2010-09-20cache operations for octeon. ok miod@Takuya ASADA
2010-09-19Overhaul ddb disassembler to recognize all MIPS IV instructions, as well asMiod Vallat
some mips64r2 instructions. Various bugfixes all over as well (conditional trap instructions do not have a delay slot, for instance).
2010-09-17Recognize MIPS IV extra FPU condition codes in MipsEmulateBranch().Miod Vallat
2010-09-17Protect a few more defines with _KERNEL checks, and also allow some of themMiod Vallat
to be visible if _STANDALONE. This will eventually be used by the upcoming new-and-improved loongson bootblocks (in the works).
2010-09-17FPU control/status register defines, and upcoming userland functionMiod Vallat
prototypes to allow control of the FPU c/sr FS field.
2010-09-17There is only one code for coprocessor BC opcodes, so don't bother to handleMiod Vallat
a second (invalid) opcode; confirmed by all mips core documentation.
2010-09-13Added OCTEON in cpu type. ok miod@Takuya ASADA
2010-09-12Stricter types in MipsEmulateBranch(), and related cleanups.Miod Vallat
No functional change.
2010-09-12Use __dead instead of volatile to mark functions that don't return. MakesMark Kettenis
it possible to compile sgi kernels with gcc4. ok miod@ (who pointed out what volatile was used for in this case)
2010-09-11move machine dependent GET_CPU_INFO(), getcurcpu(), setcurcpu() to arch/sgi. ↵Takuya ASADA
ok miod@
2010-08-30ddbcpu for sgi. ok miod@Takuya ASADA
2010-07-17Correct value of DBL_MIN and DBL_MAX to match <sys/limits.h>Miod Vallat
2010-05-23#ifdef arc is just too common, but I don't know how to extract this correctlyTheo de Raadt
so make that __arc__ for now, to avoid collisions ok miod
2010-05-08Huge work-in-progress commit to support Loongson 2E-based evaluation boardsMiod Vallat
with a VIA 686 southbridge. Features: - 686 setup code (no thanks to PMON for not initializing the beast). - work in progress ISA interrupt handling code. - support for vga(4) compatible devices as console, in PC-compatible text mode. - move legacy (ISA) support code out of bonito(4) to make things clearer. - support more than 256MB on 2E-based systems. Tested on a generic 2E-based evaluation board by someone who wishes to remain anonymous; you know who you are, thank you very much for testing.
2010-04-28Storeing current cpu_info address into LLAddr register, for curcpu().Takuya ASADA
Instead of previous implementation, we won't use physical cpuid to fetch curcpu(). This requires to implement IP27/35 SMP. Implemented getcurcpu() and setcurcpu() for it, smp_malloc() renamed alloc_contiguous_pages() because now it only allocate by page. ok miod@
2010-04-21more cleanup to cope with the change that tries to make proc.h not actTheo de Raadt
like it is everything.h ok tedu
2010-03-07Correct layout of arc_config{,64} and order of items in enum arc_config_type.Miod Vallat
ok deraadt@
2010-03-03Store ARCBios variables before machine specific setup is performed andJoel Sing
make console selection on a per machine basis. Whilst here store the keyboard layout ('keybd') and graphics state ('gfx') variables for future use. ok miod@
2010-03-02Add support for the Lemote Lynloong all-in-one PC (basically a Fuloong withoutMiod Vallat
the serial and IR ports, built into a mac-like case). At least PMON initializes the frame buffer in a much friendlier video mode (1360x768x16), but there is still no frame buffer acceleration yet. Tested by wvdputte.
2010-03-01- properly spell 'exception' in commentsJasper Lievisse Adriaanse
- properly spell 'usefulness'
2010-02-28Pass L2 cache size in struct cpu_hwinfo, so that bootstrap of secondaryMiod Vallat
processors can display correct data. Now cpu1 on octane is correctly reported in dmesg.
2010-02-28Add an explicit `delay constant' member to struct cpu_info, so that it canMiod Vallat
be decoupled from the nominal processor speed. While there, make sure delay() gets a proper delay constant if invoked before cpu0 attaches (how could I miss that when introducing struct cpu_hwinfo?!?)
2010-02-13Since we don't use the saved ipl in pcb anymore, remove it from the structMiod Vallat
layout.
2010-02-11fuloong model defineOtto Moerbeek
2010-02-05Blind support for the EMTEC Gdium Liberty netbook. Per-platform configurationMiod Vallat
is moved to specific files, and a pointer to the key configuration structure is now kept in struct sys_config. bonito(4) interrupt handling is split, to allow PCI+Legacy interrupt systems (Lemote Yeelong) and PCI-only Legacy-free systems (Gdium) to coexist peacefully.
2010-02-02Skip calling smp_rendezvous if it's not necessary.Takuya ASADA
ok miod@
2010-01-28The RA stack control bit on the loongson2 diagnostic register is not a clearMiod Vallat
but a disable bit; rename the define and keep the RA stack disabled at all times - I blame the few remaining hard freezes on it.
2010-01-23Give little-endian fp on mips a change to be handled correctly.Miod Vallat
2010-01-18Define IPL_SCHED as IPL_CLOCK, not IPL_HIGH.Miod Vallat
2010-01-18Make trapdebug code MP-safe.Miod Vallat
2010-01-09Make interrupt depth counters per-cpu.Miod Vallat
2010-01-09Move cache information from global variables to per-cpu_info fields; thisMiod Vallat
allows processors with different cache sizes to be used. Cache management routines now take a struct cpu_info * as first parameter.
2010-01-09Define struct cpu_hwinfo, to hold hardware specific information about eachMiod Vallat
processor (instead of sys_config.cpu[]), and pass it in the attach_args when attaching cpu devices. This allows per-cpu information to be gathered late in the bootstrap process, and not be limited by an arbitrary MAX_CPUS limit; this will suit IP27 and IP35 systems better. While there, use this information to make sure delay() uses the speed information from the cpu it is invoked on.
2010-01-08MP-safe FPU handling. ok miod@Takuya ASADA
2010-01-05Dynamic allocation for ASID and ASID generation number on struct pmap. ok miod@Takuya ASADA
2009-12-30curcpu()->ci_curpmap added. ok miod@Takuya ASADA
2009-12-28MP-safe pmap implemented, enable IPI in interrupt handler to avoid deadlock.Takuya ASADA
ok miod@
2009-12-25Pass both the virtual address and the physical address of the memory rangeMiod Vallat
when invoking the cache functions. The physical address is needed when operating on physically-indexed caches, such as the L2 cache on Loongson processors. Preprocessor abuse makes sure that the physical address computation gets compiled out when running on a kernel compiled for virtually-indexed caches only, such as the sgi kernel.
2009-12-13bit less aggressive about hiding; ok miodTheo de Raadt
2009-12-12Protect more definitions userland doesn't need to care about with _KERNELMiod Vallat
2009-12-12Switch page size from 4KB to 16KB on R10k kernels without R5k supportMiod Vallat
(i.e. IP27 and IP30 sgi kernels).
2009-12-12unifdef -D__LP64__Miod Vallat
2009-12-11More changes to avoid truncating 64 bit pointers to 32 bits and sign-extendingMiod Vallat
them; allows userland with stack beyond 2GB to run.
2009-12-08Unconditionnaly move kernel virtual memory space to XKSEG, now that previousMiod Vallat
context.S fixes allows these settings to work for kernels linked in CKSEG0.
2009-12-08Use a whole page for msgbuf if page size is larger than 4KB, instead ofMiod Vallat
the current 8KB.