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2020-05-23Use a distinct trap code with retguard on mips64.Visa Hankala
This lets the kernel detect retguard traps and send SIGABRT instead of SIGEMT. SIGEMT does not indicate correctly the nature of the error (stack overflow, violation of control flow). It can confuse the user to restart the program without further investigation. Prompted by and OK deraadt@ OK mortimer@
2020-05-16Make inittodr() and resettodr() MI.Mark Kettenis
ok deraadt@, mpi@, visa@ ok cheloha@ as well (would have preferred in new file for this code)
2020-05-16Use todr_gettime() in cp0_calibrate() on mips64.Visa Hankala
This allows changing RTC drivers from <mips64/dev/clockvar.h> to <dev/clock_subr.h> API. OK kettenis@
2020-05-11Initialize the timeval passed to todr_gettime() with the base time fromMark Kettenis
the file system such that implementations can use it to guess the right century. ok mpi@
2020-05-09Use the same inittodr()/resettodr() implementation as onMark Kettenis
amd64/arm64/armv7/hppa/i386/macppc/sparc64 and move it to the end of mips64_machdep.c. Wrap the existing tod_get and tod_set hooks into something that can be used as a todr_handle. ok visa@
2020-04-18Sync existing stacktrace_save() implementationsVisa Hankala
Upgrade stacktrace_save() to stacktrace_save_at() on architectures where the latter is missing. Define stacktrace_save() as an inline function in header <sys/stacktrace.h> to reduce duplication of code. OK mpi@
2020-01-20Separate the stack trace saving interface from ddb. The saving does notVisa Hankala
require the debugger on most architectures, and the separation makes the code easier to use from other subsystems. The function definitions are still conditional to DDB. However, that should not matter for now. OK deraadt@, mpi@
2020-01-02Use newabi register names in disassembly.Visa Hankala
OK miod@
2019-12-20Convert various boolean_t/TRUE/FALSE to int/1/0 in mips64 memory code.Visa Hankala
OK mpi@
2019-12-20Convert boolean_t/TRUE/FALSE to int/1/0 in mips64 pmap.Visa Hankala
Rename variables for clarity while here. OK mpi@
2019-11-20Ensure that the kernel stack is properly aligned on mips64. This fixesVisa Hankala
a panic related to vararg function sppp_auth_send(). The vararg code generated by clang assumes 16-byte stack alignment. pppoe(4)-induced panic seen by many on octeon Fix from miod@
2019-11-07Convert db_addr_t -> vaddr_t but leave the typedef for now.Martin Pieuchot
2019-11-07Substitute boolean_t/TRUE/FALSE by int/1/0.Martin Pieuchot
ok dlg@, jasper@
2019-10-28Fix atomic_sub_long_nv() on mips64. The negation should useVisa Hankala
64-bit unsigned arithmetic.
2019-09-06Do not stop prologue scan at branch instructions. This lets stack traceVisa Hankala
saving work with the twisted code that clang occasionally emits; stack frame setup can happen very late after blocks of conditional code.
2019-09-06Stop stack trace saving if the current subroutine is u_general or u_intrVisa Hankala
because the next frame is in userspace.
2019-09-06If uvm_map_inentry returns false then a signal has been delivered, andTheo de Raadt
userret() must be called on trap() exit to deliver it, rather than repeating the same cause infinitely. discovered by George Koehler ok kettenis bluhm visa
2019-09-05Implement splassert() on mips64.Visa Hankala
2019-09-05Adjust interrupt priority levels on mips64 so that prioritiesVisa Hankala
of soft interrupts are lower than priorities of hard interrupts. This allows the delivery of hard interrupts while soft interrupts are masked.
2019-09-02cpu number is unsigned (does not really matter)Theo de Raadt
2019-09-02in non-MP, cpu_number() the #define should be 0UL; ok visaTheo de Raadt
2019-08-21Fix a race in invalidation of remote TLB entries.Visa Hankala
If a CPU updates a pmap concurrently with the activation of that pmap on another CPU, invalidation of TLB entries might be incomplete. It is also possible that a CPU altogether stops updating its TLB. Prevent the race by synchronizing pmap activations and logic that determines where to send TLB invalidation IPIs. To avoid mutex wait without ability to process IPIs, the context switch code is adjusted to call pmap_activate() with interrupts enabled. In practice, interrupts up to IPL_SCHED are still disabled on context switch.
2019-08-02Avoid repeated invocation of curcpu().Visa Hankala
2019-08-02Call refreshcreds() from ast() on mips64. This ensures that credentialsVisa Hankala
get updated when handling an AST after an interrupt. OK deraadt@
2019-07-09I wrote the pc-page-writeable and sp-not-MAP_STACK code to be shared, andTheo de Raadt
then ran into the messaging being poor. Then I fixed the messages. But there are two sub-cases of sp-not-MAP_STACK -- one at syscall time, and another at regular userland trap (on some architectures), and I bungled that messaging. Correct that now, while I look for yet another better way... discovered by millert, who ran an pre-MAP_STACK binary.
2019-06-30Ansify function definitions.Visa Hankala
2019-06-23Invalidate icache when changing mappingVisa Hankala
On octeon, the instruction cache appears to fulfill instruction fetches on icache hit even if the virtual address mapping no longer exists or does not allow execution. Prevent running of lingering instructions by invalidating the icache when changing a mapping that has previously been executable. This fix is somewhat rough and relies on the availability of the XI bit.
2019-06-01Refactor the MAP_STACK feature, and introduce another similar variation:Theo de Raadt
Lookup the address that a syscall instruction is executed from, and kill the process if that page is writeable. This brings an aspect of W^X behaviour to W|X mappings (in JITs not yet adapted to W^X). The goal is to remove simple attack methods and force use of ret2libc or other more complicated means. ok kettenis stefan visa
2019-05-15Reduce branch emulation page access protection during setup. The setupVisa Hankala
stage does not need execute access, so map the page initially with read-write protection. OK miod@
2019-05-15Drop redundant pmap_proc_iflush() call. The needed instruction cacheVisa Hankala
invalidation is done by mips64 pmap when the branch emulation page is made executable. Originally, the pmap_proc_iflush() call was necessary. The instruction cache invalidation was added in pmap_protect() after the FPU emulation was introduced. OK miod@
2019-05-08Print the current ASID in hex instead of decimal, to match the formatVisa Hankala
with the ASID format on TLB entry lines.
2019-05-06Enforce store/load order when setting or clearing AST flag on mips64Visa Hankala
Make sure that any preceding stores become visible to other CPUs before setting the AST flag in need_resched() and signotify(). This should prevent a very unlikely case with inter-CPU ASTs where the receiving CPU uses stale state. When clearing the AST flag in ast(), ensure that the clearing store is performed before any other memory accesses in the AST handler. Otherwise, there is a slight risk of losing an AST request that gets posted while the handler is running. OK guenther@
2019-05-06Issue write-write barrier before sending IPI on mips64Visa Hankala
The barrier ensures that any lockless state changes become visible to other CPUs before the IPI is sent. Otherwise, a receiving CPU might still observe an old state when it processes the interrupt. OK guenther@
2019-05-06Fix unintentional delay of ASTs on MP mips64Visa Hankala
Make the interrupt and trap return paths check for ASTs with interrupts disabled. If there is no pending request, interrupts are kept disabled until return to userspace. This fixes delayed processing of an AST request that arrives from another CPU after the AST flag has been checked but before the CPU has finished the return path. The IPI that follows the setting of the AST flag forces kernel re-entry and recheck of AST. Noticed by guenther@
2019-05-05Call cpu_unidle() from need_resched() on mips64 like mostVisa Hankala
other architectures.
2019-05-05Turn need_resched() and signotify() into proper functions on mips64.Visa Hankala
2019-04-26Guard against repeated inclusion of <mips64/pte.h>. This fixes drm buildVisa Hankala
on loongson.
2019-04-23Call exit(2) if sigreturn(2) fails on mips64. This is what otherVisa Hankala
architectures do. Noticed by deraadt@
2019-04-19Work around a limitation of clang integrated assembler on mips64.Visa Hankala
The assembler does not handle undeclared local symbols properly and generates R_MIPS_CALL16 relocations where it should generate local GOT references. For now, get along with the problem by declaring local symbols where necessary. OK kettenis@ guenther@
2019-03-23Use the debugger mutex for `ddb_mp_mutex'. This should prevent a raceVisa Hankala
that could leave `ddb_mp_mutex' locked if one CPU incremented `db_active' while another CPU was in the critical section. When the race hit, the debugger was unable to resume execution or switch between CPUs. Race analyzed by patrick@ OK mpi@ patrick@
2019-03-17Move intr_barrier(9) to the platform level so that it can be customized.Visa Hankala
2019-03-16Include header <sys/evcount.h> where event counters are used, so thatVisa Hankala
header <machine/intr.h> can eventually stop including it on octeon.
2019-01-14Wrap floating point instructions with .set hardfloat to make clang'sVisa Hankala
integrated assembler accept them in the kernel. Move fsr access code into dedicated inline functions to improve readability.
2019-01-05Expand a macro instruction for clang. Unlike gas, the integratedVisa Hankala
assembler does not handle the large immediate value automatically.
2019-01-05Replace two-operand instruction aliases that clang does notVisa Hankala
understand with the three-operand instructions. No binary change with gas.
2018-12-31Set floating point condition code even if the result of an emulatedVisa Hankala
floating point comparison is unordered. The setting should be skipped only if an invalid operation exception is taken. This fixes incorrect emulated compare behaviour with NaN values. NaN issue on octeon reported by afresh1@; OK miod@
2018-12-13Use a faster, more reliable way to figure out how many TLB entries areVisa Hankala
available on RM7000 processors. From miod@
2018-12-05Include srp.h where struct cpu_info uses srp to avoid erroring out whenJonathan Gray
including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
2018-12-04Add processor IDs for several OCTEON II and III SoCs.Visa Hankala
2018-10-22More "explicitely" -> "explicitly" in various comments.Kenneth R Westerback
ok guenther@ tb@ deraadt@
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