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AgeCommit message (Collapse)Author
2014-12-17pretty easy removal of simplelocksTheo de Raadt
ok miod (a while back)
2014-12-16primary change: move uvm_vnode out of vnode, keeping only a pointer.Ted Unangst
objective: vnode.h doesn't include uvm_extern.h anymore. followup changes: include uvm_extern.h or lock.h where necessary. ok and help from deraadt
2014-12-15Use MAP_INHERIT_* for the 'inh' argument to the UMV_MAPFLAG() macro,Philip Guenther
eliminating the must-be-kept-in-sync UVM_INH_* macros ok deraadt@ tedu@
2014-12-13An UVM_ADV_NORMAL -> MADV_NORMAL was missed herePhilip Guenther
2014-11-16Replace a plethora of historical protection options with justTheo de Raadt
PROT_NONE, PROT_READ, PROT_WRITE, and PROT_EXEC from mman.h. PROT_MASK is introduced as the one true way of extracting those bits. Remove UVM_ADV_* wrapper, using the standard names. ok doug guenther kettenis
2014-09-30implement atomic operations using ll/sc, and convert rw_cas and callers of theJonathan Matthew
pre-existing atomics to match. tested on sgi (octane) and octeon (erl) ok miod@ dlg@
2014-08-18Sigh, ignoring instruction fetch bus errors for the kernel code should notMiod Vallat
depend upon the address being at the beginning of a cache line, for we may arrive in the middle of a line thanks to a branch. Noticed the hard way...
2014-08-17On kernels compiled with R10000 support, ignore (by simply returning)Miod Vallat
`bus error upon instruction fetch' exceptions where the faulting address is in the kernel, and at the very beginning of an I$ cache line. (I've experienced these on an R16000 Fuel since several months already)
2014-08-14fixed overrid(d)en typoTobias Stoeckmann
millert@ and jmc@ agree that "overriden" is wrong
2014-08-12addu -> PTR_ADDU when doing address arithmetic in the octeon-specific code path.Miod Vallat
2014-08-12Better cache information gathering. Only affects information put in dmesg.Miod Vallat
2014-08-12Pass 0 instead of uvm_map_hint() to uvm_map() in exec_md_map() to figure outMiod Vallat
where to put the fpu assist page, for uvm_map_hint() may return an address outside userland bounds due to aggressive randomization. Passing zero will still get a random address, but correctly bounded.
2014-07-13use nitems() instead of handrolling something identicalJasper Lievisse Adriaanse
ok mpi@ sthen@
2014-07-12add a size argument to free. will be used soon, but for now default to 0.Ted Unangst
after discussions with beck deraadt kettenis.
2014-07-12Tackle the endian.h mess. Make it so that:Philip Guenther
* you can #include <sys/endian.h> instead of <machine/endian.h>, and ditto <endian.h> (fixes code that pulls in <sys/endian.h> first) * those will always export the symbols that POSIX specified for <endian.h>, including the new {be,le}{16,32,64}toh() set. c.f. http://austingroupbugs.net/view.php?id=162 if __BSD_VISIBLE then you also get the symbols that our <machine/endian.h> currently exports (ntohs, NTOHS, dlg's bemtoh*, etc) * when doing POSIX compiles (not __BSD_VISIBLE), then <netinet/in.h> and <arpa/inet.h> will *stop* exporting the extra symbols like BYTE_ORDER and betoh* ok deraadt@
2014-07-11CPU_BUSY_CYCLE(): A new MI statement for busy loop power reductionMasao Uebayashi
The new CPU_BUSY_CYCLE() may be put in a busy loop body so that CPU can reduce power consumption, as Linux's cpu_relax() and FreeBSD's cpu_spinwait(). To start minimally, use PAUSE on i386/amd64 and empty on others. The name is chosen following the existing cpu_idle_*() functions. Naming and API may be polished later. OK kettenis@
2014-07-09Do the way long overdue renaming of register names from o32 to n64 ABI.Miod Vallat
In other words, ta0-ta3 are now a4-a7 instead of t0-t3; and the former t4-t7 are now t0-t3.
2014-07-09need uvm/uvm_extern.h since no longer supplied below user.hTheo de Raadt
2014-07-08decouple struct uvmexp into a new file, so that uvm_extern.h and sysctl.hTheo de Raadt
don't need to be married. ok guenther miod beck jsing kettenis
2014-06-18fix format string if DEBUGMiod Vallat
2014-06-17We need to be more aggressive flushing L2 entries on RM7000 systems.Miod Vallat
2014-06-12Grab the kernel lock before cleaning up single-step breakpoints. ShouldMark Kettenis
prevent mips64 from hitting the same problem as found by tobiasu@ on hppa. ok miod@
2014-05-19Format string fixes and removal of -Wno-format for sgi. Based upon anMiod Vallat
initial diff from jasper@
2014-05-11Move the increment of uvmexp.softs back to the caller of mi_ast():Philip Guenther
it needs to be done atomicly on some MP archs and we don't have atomic_add_int() everywhere yet. Also, mi_ast() was meant to be inline. noted by miod@
2014-05-11Pull in <sys/user.h> before <sys/syscall*.h>Philip Guenther
2014-05-10various format string fixes and remove -Wno-format from octeonJasper Lievisse Adriaanse
feedback/ok miod@
2014-05-10Factor out the common ast bits into mi_ast()Philip Guenther
ok deraadt@
2014-04-18Have each thread keeps its own (counted!) reference to the process's ucredsPhilip Guenther
to avoid possible use-after-free references when swapping ids in threaded processes. "Do I have the right creds?" checks are always made with the threads creds. Inspired by FreeBSD and NetBSD "right time" deraadt@
2014-04-09Make trapDump() take the printf-like function as a 2nd parameter.Miod Vallat
No functional change; helps non-released kernels with extra debugging code (-:
2014-04-04Second step of the R4000 EOP errata WAR: when pmap invalidates a page whichMiod Vallat
is currently being covered by the wired TLB entries, flush them, so that, if the process' pc is still running in a vulnerable page, the WAR will reapply immediately and fault the next page.
2014-04-03Do not keep the EOP check bits in PGF_PRESERVE.Miod Vallat
2014-04-03Moar <uvm/uvm.h> -> <uvm/uvm_extern.h> love.Martin Pieuchot
2014-03-31Due the virtually indexed nature of the L1 instruction cache on most mipsMiod Vallat
processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.
2014-03-29Update the loongson codebase to recognize the so-called `EFI-like' interfaceMiod Vallat
supposedly provided by newer PMON firmware (on Loongson 2Gq and Loongson 3A systems).
2014-03-29It's been a quarter century: we can assume volatile is present with that name.Philip Guenther
ok dlg@ mpi@ deraadt@
2014-03-26Service R4[04]00SC-specific virtual coherency exceptions directly from theMiod Vallat
lowest bowels of the exception handling code, rather than in trap(). They won't get recorded in the trap history, but there is a measurable speedup. No change for non-CPU_R4000 kernels.
2014-03-26Move p_emul and p_sigcode from proc to process.Philip Guenther
Tweak the handling of ktrace EMUL when changing ktracing: only generate one per process (not one per thread) and pass the correct proc pointer down to the VFS layer. Permit generating of NAMI and CSW records inside ktrace(2) itself. ok deraadt@ millert@
2014-03-24Only need to call tlb_probe() once per pair, instead of once per page.Miod Vallat
2014-03-24Make sure tlb_probe() reads the probe result before reenabling interruptsMiod Vallat
(egads!). While there, remove leftover instructions from an early flavour of tlb_update_indexed(), which crept in by accident.
2014-03-22Move p_sigacts from struct proc to struct process.Philip Guenther
testing help mpi@
2014-03-22Second draft of my attempt to workaround the infamous R4000 end-of-page errata,Miod Vallat
affecting R4000 processors revision 2.x and below (found on most R4000 Indigo and a few R4000 Indy). Since this errata gets triggered by TLB misses when the code flow crosses a page boundary, this code attempts to identify code pages prone to trigger the errata, and force the next page to be mapped for at least as long as the current pc lies in the troublesome page, by creating wiring extra TLB entries. These entries get recycled in a lazy-but-aggressive-enough way, either because of context switches, or because of further tlb exceptions reaching trap(). The errata workaround code is only compiled on R4000-capable kernels (i.e. sgi GENERIC-IP22 and nothing else), and only enabled on affected processors (i.e. not on R4000 revision 3, or on R4400). There is still room for improvemnt in unlucky cases, but in this simple enough incarnation, this allows my R4000 2.2 Indigo to finally reliably boot multiuser, even though both /sbin/init and /bin/sh contain code pages which can trigger the errata.
2014-03-22Shuffle tlblo-related defines, to better show which bits are software only,Miod Vallat
and which bits end up in the actual tlb registers. On non-R8000 kernels, shrink the actual physical address bits to add a new software bit, PG_SP (for `special'), which will be used shortly. This halves the physical memory addressable by non-MIPS_PTE64 kernels, which should not be a problem anyway.
2014-03-21Rename db_inst_type() into classify_insn() and make that function availableMiod Vallat
outside of ddb. It will be used by regular kernel code shortly.
2014-03-21Rename the symbolic constants for the pmap-specific vm_pag pg_flags fromMiod Vallat
PV_xxx to PGF_xxx for consistency (these are not stored in pvlist entries anymore since years). The PG_ prefix can't be used here because of name conflicts with <machine/pte.h> names, and I'd rather not rename the pte constants. No functional change. But it makes my life easier.
2014-03-21Allow for two more pmap-specific bits in vm_page pg_flags. DefineMiod Vallat
PG_PMAPMASK as all the possible pmap-specific bits (similar to the other PG_fooMASK) to make sure MI code does not need to be updated, the next time more bits are allocated to greedy pmaps. No functional change, soon to be used by the (greedy) mips64 pmap.
2014-03-19It's safe to assumed 'signed' existsPhilip Guenther
2014-03-16DDB supports ELF symbols are all archs, and it's always the same as thePhilip Guenther
native size, so eliminate the #defines. ok miod@
2014-03-14Revert previous; turns out to be necessary to build the 32-bit boot blocksMiod Vallat
on sgi.
2014-03-11Simpler RM7000 L2 cache initialization code (no longer matches what pmon2000Miod Vallat
did, but less awkward). Also make sure that the code changing the K0SEG CCA value has enough nops, before returning to cached space, to match the recommended procedure in the RM52xx and RM7000 erratas.
2014-03-11lint is gone, and the 'lint' conditional was never in the implementationPhilip Guenther
namespace, so stop changing behavior when it's #defined ok beck@ krw@
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