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2012-04-21Rework the signature of the cache handling routines again. It makes more senseMiod Vallat
to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.
2012-04-19Print the currently active ASID in `machine tlb' ddb command.Miod Vallat
2012-04-19Be sure to update the currently active ASID in pmap_activate() if invoked onMiod Vallat
behalf of curproc.
2012-04-16Move proc0 and trap handler setup before consinit(), but still wait for theMiod Vallat
initial setup to be complete before switching to our trap handlers. However, change guarded_{read,write}_* to clear BEV in the coprocessor 0 status register, and restore it afterwards, to use our fault handlers within these functions. This makes these functions usable from consinit().
2012-04-16Fix struct arc_param_blk_* layout to not embed pointers, as this messes theMiod Vallat
layout in 64-bit mode. Found the hard way, of course.
2012-04-15Tell Indy and Challenge S apart.Miod Vallat
2012-04-11The first ktrace record for a newly spawned thread is a returnMike Belopuhov
from a fork syscall done by the parent. Use __tfork, not rfork here to match the ktrace records for the parent (CALL __tfork, RET __tfork). ok guenther
2012-04-10Count traps and fpu context switches.Miod Vallat
2012-04-09No need to round VCEI addresses, and VCED addresses only need to be roundedMiod Vallat
to a word boundary.
2012-04-09More errata bandaid for the R4000SC is necessary in the tlb handlers.Miod Vallat
2012-04-06Make the logic for PMAP_PREFER() and the logic, inside pmap, to do theMiod Vallat
necessary cache coherency work wrt similar virtual indexes of different physical pages, depending upon two distinct global variables, instead of a shared one. R4000/R4400 VCE requires a 32KB mask for PMAP_PREFER, which is otherwise not necessary for pmap coherency (especially since, on these processors, only L1 uses virtual indexes, and the L1 size is not greater than the page size, as we are using 16KB pages).
2012-04-06Rework IP22 RTC year base computation, again. It turns out that differentMiod Vallat
Indy PROM versions use different year bases - after all, using 1970 instead of the previously used value of 1940 smelled like a bug, and probably was, so this eventually got fixed in later PROM versions. Instead of hardcoding a year base depending upon the system, we will now ask ARCBios for its current year, and compare it to what can be read from the RTC registers to figure out what year base is in use by the PROM.
2012-03-28Work in progress support for the SGI Indigo, Indigo 2 and Indy systemsMiod Vallat
(IP20, IP22, IP24) in 64-bit mode, adapated from NetBSD. Currently limited to headless operation, input and video drivers will get ported soon. Should work on all R4000, R4440 and R5000 based systems. L2 cache on R5000SC Indy not supported yet (coming soon), R4600 not supported yet either (coming soon as well). Tested to boot multiuser on: Indigo2 R4000SC, Indy R4000PC, Indy R4000SC, Indy R5000SC, Indigo2 R4400SC. There are still glitches in the Ethernet driver which are being looked at. Expansion support is limited to the GIO E++ board; GIO boards with PCI-GIO bridges not ported yet due to the lack of hardware, and this kind of driver does not port blindly. Most of this work comes from NetBSD, polishing and integration work, as well as putting as many ``R4x00 in 64-bit mode'' erratas as necessary, by yours truly. More work is coming, as well as trying to get some easy way to boot install kernels (as older PROM can only boot ECOFF binaries, which won't do for the kernel).
2012-03-25Move cache handling routines related definitions to a dedicated header file,Miod Vallat
rather than abusing <machine/cpu.h>.
2012-03-25Only set the low order bits of CpuCacheAliasMask if it is nonzero, regressionMiod Vallat
of previous computation fix.
2012-03-24Fix fallback of uvm_map_hint() argument changes.Miod Vallat
2012-03-24Oops, forgot this file in the SGI_<model> -> SGI_IP## change.Miod Vallat
2012-03-24The various ConfigCache() functions actually return void, not int.Miod Vallat
2012-03-24Rename the various SGI_xxx constants from machine names to their IP numbers,Miod Vallat
for IP numbers under 30 (Octane), and add a few interesting ones. No functional change, except making my life easier for upcoming work.
2012-03-24Add a few trivial routines to get mips64r2 specific config registers. Not usedMiod Vallat
by anything yet, but has been lying in one of my trees for too long.
2012-03-19On sgi, use CKSEG0 addresses whenever possible for pmap_map_direct and u areaMiod Vallat
pages. This will allow R5000-based systems with physical memory fitting in CKSEG0 to use 16KB pages and direct maps (since only XKPHYS accesses trigger the XKPHYS coherency errata on these processors). Tested on IP32, IP30 and IP27 (and loongson too as well).
2012-03-19Recent uvm code (and maybe not-so-recent, but it did not explode^WKASSERT atMiod Vallat
my face then...) depends upon PMAP_PREFER_ALIGN to be a power of two, minus one. On mips64 with 4KB pages, the runtime variable used to compute PMAP_PREFER_ALIGN had the low PAGE_SHIFT bits zeroed (for no good reason I'd say). Don't bother zeroing them anymore.
2012-03-19Use uncached addresses for all exception vectors, when copying our code (orMiod Vallat
trampolines) to them; this makes sure there is no risk of pending writes being lost when we clear the caches. Of course, this would be a bug in the cache handling routines, but having our vectors correctly set will help debugging the issue. Tested on sgi and loongson.
2012-03-15uncached_base was introduced early in IP27 support, since these designs useMiod Vallat
subspaces in the CCA_NC uncached memory space. However, being coherent, there was never a need for bus_dma to use uncached addresses. This means that, on the only systems where uncached_base was not set to PHYS_TO_XKPHYS(0, CCA_NC), it was never used. Remove the variable, and replace PHYS_TO_UNCACHED() with PHYS_TO_XKPHYS(, CCA_NC). No functional change.
2012-02-16Do an explicit `sync' instruction before returning from cache routines; this isMiod Vallat
a nop on R5k and RM52xx, but actually required on RM7k.
2012-02-16Be sure to reset coprocessor 0 TAG_LO register to zero before attemptingMiod Vallat
InvalidatePage_* cache operations on RM52xx and RM7k, as strongly recommended by the manual.
2012-02-16Use abbreviated mnemonics whenever possible (e.g. beqz instead of beq ...,zero),Miod Vallat
fix various typos in comments, harmonize a few of them, and rename the internal InvalidateSecondaryPage define to InvalidatePage_S for consistency. No change in generated code.
2011-11-16Make userret() MI. On architectures which jammed stuff into it in theTheo de Raadt
past, pull that code out seperately. ok guenther miod
2011-11-15label_t is the kernel setjmp buffer. It should simply be an array ofTheo de Raadt
the right type, noone will ever fiddle with the internals. discussed with jsing
2011-10-27Specify the TLS variant for each platform.Philip Guenthe
2011-09-22nowadays uvm_init() calls pmap_init(), not vm_init(); so update the comments.Jasper Lievisse Adriaanse
ok ariane@
2011-09-08Provide namespace-safe alignment macros in <machine/_types.h>, withPhilip Guenthe
compat names kept in <machine/param.h>. In <sys/socket.h>, pull in <sys/_types.h> instead of the namespace polluting <machine/param.h> and completely eliminate __CMSG_ALIGN, replaced by _ALIGN ok deraadt@
2011-09-08Make the INT_FAST*_{MIN,MAX} macros match the types they're defined to.Philip Guenthe
Since the underlying types of the int_fast types are set by machine/_types.h, put internal macros in that same file and define the exposed INT_FAST*_{MIN,MAX} macros from those. ok millert@, kettenis@
2011-08-29Only provide FLT_EVAL_METHOD for C99. Add missing DECIMAL_DIG for C99.Mark Kettenis
ok guenther@
2011-07-21Support for the eBenton EBT-700 netbook, which is similar to the LemoteMiod Vallat
Yeeloong, but with a 7" display with a 800x480 resolution, and no webcam. There are still problems to get it booting from disk from PMON (colour me unsurprised), which are being looked at. Loading the boot blocks from a FAT USB stick, to then boot the kernel from the disk, is a reliable workaround in the meantime. Tested by Ban Keong Yee (bankeong dot yee on gmail) who is the ``lucky'' owner of such a machine, thanks for your time!
2011-07-11Revert art@'s moving around of the KERNEL_LOCK()/KERNEL_UNLOCK() calls,Philip Guenthe
as it causes hangs in some ports, including libsigsegv's configure script confirmed by krw@, landry@
2011-07-10Do not register the per-cpu counter as a system timecounter on MULTIPROCESSORMiod Vallat
kernels, as there is no way to sync the counters between all processors.
2011-07-07There is a bunch of places in the kernel entry points where we don'tArtur Grabowski
hold the kernel lock, but still need call one function that needs it. Instead of grabbing the lock all over the place, move the locks into the affected functions: trapsignal, scdebug*, ktrsyscall, ktrsysret, systrace_redirect and ADDUPROF. In the cases we already hold the biglock we'll just recurse. kettenis@, beck@ ok
2011-07-06Clean up after P_BIGLOCK removal.Artur Grabowski
KERNEL_PROC_LOCK -> KERNEL_LOCK KERNEL_PROC_UNLOCK -> KERNEL_UNLOCK oga@ ok
2011-07-05Recommit the reverted sigacts change now that the NFS use-after-freePhilip Guenthe
problem has been tracked down. This fixes the sharing of the signal handling state: shared bits go in sigacts, per-rthread bits goes in struct proc. ok deraadt@
2011-06-24machdep.kbdreset enables a shutdown by Ctrl-Alt-Del on amd64 andChristian Weisgerber
i386. Stop abusing it on other archs for controling a shutdown by pressing the soft power button: * Add a MI sysctl hw.allowpowerdown; if set to 1 (the default) it allows a power button shutdown. * Make acpi(4)/acpibtn(4) honor hw.allowpowerdown. * Switch the various power button intercepts on landisk, sgi, sparc64 and zaurus over to hw.allowpowerdown. * Garbage collect the machdep.kbdreset sysctl on all archs other than amd64 and i386. ok miod@
2011-06-05Prefer __LP64__ to _LP64; pointed out by bradMiod Vallat
2011-05-30Remove the freelist member from vm_physsegOwain Ainsworth
The new world order of pmemrange makes this data completely redundant (being dealt with by the pmemrange constraints instead). Remove all code that messes with the freelist. While touching every caller of uvm_page_physload() anyway, add the flags argument to all callers (all but one is 0 and that one already used PHYSLOAD_DEVICE) and remove the macro magic to allow callers to continue without it. Should shrink the code a bit, as well. matthew@ pointed out some mistakes i'd made. ``freelist death, I like. Ok.' ariane@ `I agree with the general direction, go ahead and i'll fix any fallout shortly'' miod@ (68k 88k and vax i could not check would build)
2011-05-25Also enclose variable names with external linkage in __BEGIN_DECLS.Martynas Venckus
Doesn't matter much since C++ ABI used by GCC doesn't mangle variable names; however technically is required by Section 7.5 of the C++ spec. Discussed with/OK guenther@, matthew@.
2011-05-10revert a mistake commitTakuya ASADA
2011-05-10octeon's internal counter clock speed is same as the processor clock. ok miod@Takuya ASADA
2011-05-01Be sure to cast physmem to a 64-bit type before passing it to ptoa().Miod Vallat
2011-04-28Expose pmap_prefer parameters.Ariane van der Steldt
This will enable future uvm_map code to make intelligent decisions during allocation.
2011-04-28fenv improvements and cleanupsMartynas Venckus
2011-04-26fenv for mips64Martynas Venckus
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