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confusion. Make sure this function is invoked with interrupts enabled now.
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a chip bug, which was supposed to be fixed in that particular revision of
the die but wasn't (tlbhandler.S 1.16).
Being lazy, I did not write a runtime selection of the appropriate TLB
handler code, although this was on my list.
It turns out that this fix confuses the hell of R10000 processors revision 3
(but not earlier 2.x revisions), to the point of making the Origin 200 here
hang so hard it would not even enter the NMI handler (don't ask me how I
figured this was the cause).
So it's time to choose the appropriate TLB handling flavour at runtime,
building the trampoline code from the fixed exception handler location
jumping to the handler address at runtime. As a bonus, kernels linked in
KSEG0 get the address computation optimized and thus a smaller trampoline
than before.
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there to trap.c which is its only user. This also cleans up multiple
inclusion of <machine/cpu.h> (because <machine/psl.h> includes it) in many
places.
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is bandaid until interrupt handling is made more sane.
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interrupt masks.
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any such interrupts marked as pending.
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only once.
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loader image (which we can safely overwrite) or the kernel image itself (in
case of netboot) and there is already code to move the kernel image out
of the free memory later on.
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must have been on drugs when thinking otherwise.
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necessary, to allow the same C code to be used against 32 bit ARCBios, when
compiled in 32 bit mode, or against 64 bit ARCBios, when compiled in native
mode.
Soon to be used by the boot blocks; this commit doesn't introduce any
functional change yet.
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for now, as we get this information from elsewhere and bad things would
happen if arcbios memory walk causes more memory segment entries to be
populated than the KL memory walk will, later on.
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MACHINE_NONCONTIG (not even MACHINE_NEWNONCONTIG!)
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the next scheduled clock interrupt; the comparison would before always be
true, causing the clock to really run at hz/2.
While there, remove unused nanodelay() and attempt to clean clock
initialization a bit.
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KSEG0 addresses.
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differently at times.
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MD code would free resources that couldn't be freed until we were no
longer running in that processor. However, it's is unused on all
architectures since mikeb@'s tss changes on x86 earlier in the year.
ok miod@
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string length exceeds maxlength.
ok miod@
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others, these are the ones from code unlikely to be re-merged with
upstream sources).
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protected by __ISO_C_VISIBLE > 1999. With a little help from miod@.
ok miod@
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which are uniform for the profclock on each cpu in a SMP system (but using
a different seed for each cpu). on all cpus, avoid seeding with a value out
of the [0, 2^31-1] range (since that is not stable)
ok kettenis drahn
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anything special to prod a cpu to leave the idle loop in signotify.
powerpc, i386, amd64 and sparc64 will follow soon so that everyone has
the same interface to wake an idling cpu.
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For now, sparc64 is arbitrarily set to 256 (only architecture that didn't have
a practical limit in the code on the number of cpus).
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ok miod@
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remove it correctly from the array.
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- provide proper dtoa locks
- use the real strtof implementation
- add strtold, __hdtoa, __hldtoa
- add %a/%A support
- don't lose precision in printf, don't round to double anymore
- implement extended-precision versions of libc functions: fpclassify,
isnan, isinf, signbit, isnormal, isfinite, now that the ieee.h is
fixed
- separate vax versions of strtof, and __hdtoa
- add complex math support. added functions: cacos, casin, catan,
ccos, csin, ctan, cacosh, casinh, catanh, ccosh, csinh, ctanh, cexp,
clog, cabs, cpow, csqrt, carg, cimag, conj, cproj, creal, cacosf,
casinf, catanf, ccosf, csinf, ctanf, cacoshf, casinhf, catanhf,
ccoshf, csinhf, ctanhf, cexpf, clogf, cabsf, cpowf, csqrtf, cargf,
cimagf, conjf, cprojf, crealf
- add fdim, fmax, fmin
- add log2. (adapted implementation e_log.c. could be more acruate
& faster, but it's good enough for now)
- remove wrappers & cruft in libm, supposed to work-around mistakes
in SVID, etc.; use ieee versions. fixes issues in python 2.6 for
djm@
- make _digittoint static
- proper definitions for i386, and amd64 in ieee.h
- sh, powerpc don't really have extended-precision
- add missing definitions for mips64 (quad), m{6,8}k (96-bit) float.h
for LDBL_*
- merge lead to frac for m{6,8}k, for gdtoa to work properly
- add FRAC*BITS & EXT_TO_ARRAY32 definitions in ieee.h, for hdtoa&ldtoa
to use
- add EXT_IMPLICIT_NBIT definition, which indicates implicit
normalization bit
- add regression tests for libc: fpclassify and printf
- arith.h & gd_qnan.h definitions
- update ieee.h: hppa doesn't have quad-precision, hppa64 does
- add missing prototypes to gdtoaimp
- on 64-bit platforms make sure gdtoa doesn't use a long when it
really wants an int
- etc., what i may have forgotten...
- bump libm major, due to removed&changed symbols
- no libc bump, since this is riding on djm's libc major crank from
a day ago
discussed with / requested by / testing theo, sthen@, djm@, jsg@,
merdely@, jsing@, tedu@, brad@, jakemsr@, and others.
looks good to millert@
parts of the diff ok kettenis@
this commit does not include:
- man page changes
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address space. The space between PAGE_SIZE and the non-pie fixed link
address creates no mmap pressure so use that space for PIE. However on
hppa the non-pie fixed link address is PAGE_SIZE so just use a small range
for PIE to minimize mmap pressure.
okay miod@
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in the MI code.
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process_write_regs().
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- math.h shouldn't define FLT_EVAL_METHOD, but float.h should (per
C99). remove from math.h, and add proper definitions in float.h
ok millert@
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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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and can not work from a stack address only. Mention this and abort instead of
printing a wrong trace. (prefer kern.splassert=3 to =2 on these platforms)
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conversions that should shave a few bytes off the kernel.
ok henning, krw, jsing, oga, miod, and thib (``even though i usually prefer
FOO|BAR''; thanks for looking.
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tested by maja@
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available memory regions will be reported to be in VM_FREELIST_DEFAULT.
Add a few quirks to cope with (some) IP27 and IP30 weirdness.
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code soon. Similar to what ddb does, but does not need ddb to be compiled in.
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and a time-of-day chip (wherever it gets found).
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Define a symbolic ``cached'' attribute, to be used for cached mappings
regardless of the system's cache coherency.
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segments and the number of freelists.
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reason this would have been blatant on sparc on motorola, one more proof
mips is the ante${DEITY} yet fun to live with.
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