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2010-12-06Change the signature of PMAP_PREFER from void PMAP_PREFER(..., vaddr_t *) toMiod Vallat
vaddr_t PMAP_PREFER(..., vaddr_t). This allows better compiler optimization when the function is inlined, and avoids accessing memory on architectures when we can pass function arguments in registers.
2010-11-28Update comment to no longer mention a page is 4KB, since this may not be theMiod Vallat
case.
2010-11-28Enable __HAVE_PMAP_DIRECT on mips64, unless the kernel is configured toMiod Vallat
run on R5000 family processors (e.g. sgi GENERIC-IP32), where direct XKPHYS mappings hit a silicon bug.
2010-11-28Allow mips64-based ports to override the default mips64 VM_PHYSSEG_STRATMiod Vallat
strategy value (BSEARCH); use BIGFIRST on loongson since there are only up to two memory segments.
2010-11-27Remove ddb single-step load and store counters. Most platforms do notMiod Vallat
implement them, and they are of questionable usefulness.
2010-11-24Floating-point emulation code for systems lacking proper FPU (i.e. Octeon),Miod Vallat
enabled by option FPUEMUL. This is pretty straightforward, except for conditional branch on FPU condition codes emulation (bc1f/bc1fl/bc1t/bc1tl instructions): unlike most RISC-with-delay-slots designs (m88k, sparc), the branch pipeline is not exposed to the kernel on Mips, therefore we can not resume a branch without losing the delay slot instruction. Some other operating systems work around this issue by emulating the delay slot instruction, but this is error-prone (and requires the kernel code to be aware of all supported instructions of the processor it is currently running on), some use dedicated breakpoints to single-step through the delay slot and then resume the branch as expected, but this causes a lot of copy-on-write allocations. This code chooses a third path, of copying the delay slot instructions to run toa special `magic' page, followed by a special trap instruction to give control back to the kernel. This makes sure the instruction will actually be run by the processor, and that no more than one page per process is wasted, regardless of the number of branches to emulate. Tested on octeon (big-endian) by syuu@ and on loongson (little-endian) by me. Note that enabling option FPUEMUL in the kernel will completely disable the hardware FPU, if there is one; there is currently no way to build a kernel supporting both hardware and software FPU, and there is no reason to change this until there is a strong need to support both.
2010-11-24Make sure ptrace_sstep(,0) actually clears breakpoints, by replacing theMiod Vallat
ptrace guts with a logic similar to what the alpha port does.
2010-11-24Implement a real pmap_proc_iflush() instead of relying on trap.c to performMiod Vallat
copious cache flushes behind our back.
2010-11-11Correctly disassemble ssnop.Miod Vallat
2010-10-27Fix a few logic errors in comparison instruction emulation: make sure theMiod Vallat
less than relation is correctly computed, and check for both operands being signaling NaNs, instead of only the first NaN found, to decide whether to raise an invalid exception or not.
2010-10-24Move build_trampoline() and setregs() to a common location for all mips ports.Miod Vallat
2010-10-24Don't short-circuit userret() when returning from trap() in the rm7000Miod Vallat
performance counter code path (which is not enabled at the moment).
2010-10-02Added octeon specific cop0 registers. ok miod@Takuya ASADA
2010-10-01Provide a WEAK_ALIAS macro in <machine/asm.h> for the few platformsPhilip Guenthe
that didn't already have one, and then immediately use it in libc's SYS.h ok miod@
2010-09-28Implement a per-cpu held mutex counter if DIAGNOSTIC on all non-x86 platforms,Miod Vallat
to complete matthew@'s commit of a few days ago, and drop __HAVE_CPU_MUTEX_LEVEL define. With help from, and ok deraadt@.
2010-09-21Better not panic in MipsEmulateBranch() if the instruction is an unspecifiedMiod Vallat
OP_BCOND subfunction.
2010-09-21Replace the old floating point completion code with a C interface to theMiod Vallat
MI softfloat code, implementing all MIPS IV specified floating point operations. Tested on R5000, R10000, R14000 and Loongson2F.
2010-09-20Make md_printins() get the printf-like function as an extra parameter, andMiod Vallat
make it visible so that md parts of the kernel can use it for debug messages.
2010-09-20cache operations for octeon. ok miod@Takuya ASADA
2010-09-20Get rid of evcount's support for arranging counters in a treeMatthew Dempsky
hierarchy. Everything attached to a single root node anyway, so at best we had a bush. "i think it is good" deraadt@
2010-09-19Overhaul ddb disassembler to recognize all MIPS IV instructions, as well asMiod Vallat
some mips64r2 instructions. Various bugfixes all over as well (conditional trap instructions do not have a delay slot, for instance).
2010-09-17Recognize MIPS IV extra FPU condition codes in MipsEmulateBranch().Miod Vallat
2010-09-17Protect a few more defines with _KERNEL checks, and also allow some of themMiod Vallat
to be visible if _STANDALONE. This will eventually be used by the upcoming new-and-improved loongson bootblocks (in the works).
2010-09-17FPU control/status register defines, and upcoming userland functionMiod Vallat
prototypes to allow control of the FPU c/sr FS field.
2010-09-17Correctly disassemble `branch likely' instructions.Miod Vallat
2010-09-17There is only one code for coprocessor BC opcodes, so don't bother to handleMiod Vallat
a second (invalid) opcode; confirmed by all mips core documentation.
2010-09-14Recognize the new sequence gcc4 uses to trap on divide by zero.Miod Vallat
2010-09-13Added OCTEON in cpu type. ok miod@Takuya ASADA
2010-09-12Stricter types in MipsEmulateBranch(), and related cleanups.Miod Vallat
No functional change.
2010-09-12Use __dead instead of volatile to mark functions that don't return. MakesMark Kettenis
it possible to compile sgi kernels with gcc4. ok miod@ (who pointed out what volatile was used for in this case)
2010-09-12Avoid machine-check exception on OCTEON. ok miod@Takuya ASADA
2010-09-11move machine dependent GET_CPU_INFO(), getcurcpu(), setcurcpu() to arch/sgi. ↵Takuya ASADA
ok miod@
2010-09-09Move cache settings into hw_cpu_init_secondary() ok miod@Takuya ASADA
2010-09-09Fix compile error on option DEBUG ok miod@Takuya ASADA
2010-08-30ddbcpu for sgi. ok miod@Takuya ASADA
2010-08-07No "\n" needed at the end of panic() strings.Kenneth R Westerback
Bogus chunks pointed out by matthew@ and miod@. No cookies for marco@ and jasper@. ok deraadt@ miod@ matthew@ jasper@ macro@
2010-07-17Correct value of DBL_MIN and DBL_MAX to match <sys/limits.h>Miod Vallat
2010-06-26Don't #include <sys/user.h> into files that don't need the stuffPhilip Guenthe
it defines. In some cases, this means pulling in uvm.h or pcb.h instead, but most of the inclusions were just noise. Tested on alpha, amd64, armish, hppa, i386, macpcc, sgi, sparc64, and vax, mostly by krw and naddy. ok krw@
2010-05-23#ifdef arc is just too common, but I don't know how to extract this correctlyTheo de Raadt
so make that __arc__ for now, to avoid collisions ok miod
2010-05-10Don't postincrement a casted pointer; split into multiple statements instead.Mark Kettenis
Makes gcc4 happy. ok miod@
2010-05-08Huge work-in-progress commit to support Loongson 2E-based evaluation boardsMiod Vallat
with a VIA 686 southbridge. Features: - 686 setup code (no thanks to PMON for not initializing the beast). - work in progress ISA interrupt handling code. - support for vga(4) compatible devices as console, in PC-compatible text mode. - move legacy (ISA) support code out of bonito(4) to make things clearer. - support more than 256MB on 2E-based systems. Tested on a generic 2E-based evaluation board by someone who wishes to remain anonymous; you know who you are, thank you very much for testing.
2010-04-28Storeing current cpu_info address into LLAddr register, for curcpu().Takuya ASADA
Instead of previous implementation, we won't use physical cpuid to fetch curcpu(). This requires to implement IP27/35 SMP. Implemented getcurcpu() and setcurcpu() for it, smp_malloc() renamed alloc_contiguous_pages() because now it only allocate by page. ok miod@
2010-04-21two more proc.h neededTheo de Raadt
2010-04-21more cleanup to cope with the change that tries to make proc.h not actTheo de Raadt
like it is everything.h ok tedu
2010-03-28Correctly report the R16010 version.Miod Vallat
2010-03-07Correct layout of arc_config{,64} and order of items in enum arc_config_type.Miod Vallat
ok deraadt@
2010-03-03Store ARCBios variables before machine specific setup is performed andJoel Sing
make console selection on a per machine basis. Whilst here store the keyboard layout ('keybd') and graphics state ('gfx') variables for future use. ok miod@
2010-03-02Add support for the Lemote Lynloong all-in-one PC (basically a Fuloong withoutMiod Vallat
the serial and IR ports, built into a mac-like case). At least PMON initializes the frame buffer in a much friendlier video mode (1360x768x16), but there is still no frame buffer acceleration yet. Tested by wvdputte.
2010-03-01- properly spell 'exception' in commentsJasper Lievisse Adriaanse
- properly spell 'usefulness'
2010-02-28Pass L2 cache size in struct cpu_hwinfo, so that bootstrap of secondaryMiod Vallat
processors can display correct data. Now cpu1 on octane is correctly reported in dmesg.
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