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path: root/sys/arch/mips64
AgeCommit message (Collapse)Author
2011-05-10revert a mistake commitTakuya ASADA
2011-05-10octeon's internal counter clock speed is same as the processor clock. ok miod@Takuya ASADA
2011-05-01Be sure to cast physmem to a 64-bit type before passing it to ptoa().Miod Vallat
2011-04-28Expose pmap_prefer parameters.Ariane van der Steldt
This will enable future uvm_map code to make intelligent decisions during allocation.
2011-04-28fenv improvements and cleanupsMartynas Venckus
2011-04-26fenv for mips64Martynas Venckus
2011-04-18Revert the sigacts diff: NFS can apparently retain pointers to processesPhilip Guenthe
until they're zombies and then send them signals (for intr mounts). Until that is untangled, the sigacts change is unsafe. sthen@ was the victim for this one
2011-04-15Correct the sharing of the signal handling state: stuff that shouldPhilip Guenthe
be shared (p_sigignore, p_sigcatch, P_NOCLDSTOP, P_NOCLDWAIT) moves to struct sigacts, wihle stuff that should be per rthread (ps_oldmask, SAS_OLDMASK, ps_sigstk) moves to struct proc. Treat the coredumping state bits (ps_sig, ps_code, ps_type, ps_sigval) as per-rthread until our locking around coredumping is better. Oh, and remove the old SunOS-compat ps_usertramp member. "I like the sound of this" tedu@
2011-04-10A last few NULL -> 0 corrections.Miod Vallat
2011-04-09repair a 32-bit truncation in paddr_t calculation, allowing my 8GBTheo de Raadt
o350 to boot once again ok miod
2011-04-07%x->%p in various format strings, to avoid truncating values.Miod Vallat
2011-04-07Make sure the ALIGN() macro uses u_long on all platforms for consistency, andMiod Vallat
update the comment block accordingly.
2011-04-07Do not use NULL in integer comparisons. No functional change.Miod Vallat
ok matthew@ tedu@, also eyeballed by at least krw@ oga@ kettenis@ jsg@
2011-04-04Correctly disassemble triadic version of {d,}m[ft]c instructions found onMiod Vallat
more and more mips64 processors.
2011-04-03Move PPWAIT flag from struct proc to process, so that rthreads inPhilip Guenthe
a vforked child behave correctly. Have the parent in a vfork() wait on a (different) flag in *its* process instead of the child to prevent a possible use-after-free. When ktracing the child return from a fork, call it rfork if an rthread was created. ok blambert@
2011-03-31Recognize Loongson 3A processors, but don't accept to run on them yet, theMiod Vallat
cache routines are not ready. This is mostly low-hanging fruit.
2011-03-23Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.Paul Irofti
Discussed and okay drahn@. Okay deraadt@.
2011-03-11Use _MACHINE_ENDIAN_H_ for this is The Right Thing To Do.Paul Irofti
Okay guenther@, millert@.
2010-12-28Previous diff had a buglet, found the hard way by pea@Miod Vallat
2010-12-26Kill pmap_phys_address(), and force every driver's mmap() routine to returnMiod Vallat
a physical address [more precisely, something suitable to pass to pmap_enter()'sphysical address argument]. This allows MI drivers to implement mmap() routines without having to know about the pmap_phys_address() implementation and #ifdef obfuscation.
2010-12-21Convert netisr to a normal soft interrupt instead of hanving MD codeClaudio Jeker
for it. This makes the netisr a real C function which will help further development. No noticable performance change on i386 and amd64. With input from kettenis@ and miod@ additional OKs mikeb@ and henning@
2010-12-15oops, i forgot to check in the BRKSIZ define in uvm, but deraadt thinksTed Unangst
its better as a per arch MD define anyway. all default to MAXDSIZ as before.
2010-12-13Remove superfluous SAVE_CPU_SREG()/RESTORE_CPU_SREG() around ast() call inMark Kettenis
u_general exception handler. The SAVE_CPU_SREG() is actually harmful, since it overwrites any changes made to to s0-s8 in the trapframe by ptrace(2). Fixes some issues with GDB. ok miod@
2010-12-06Change the signature of PMAP_PREFER from void PMAP_PREFER(..., vaddr_t *) toMiod Vallat
vaddr_t PMAP_PREFER(..., vaddr_t). This allows better compiler optimization when the function is inlined, and avoids accessing memory on architectures when we can pass function arguments in registers.
2010-11-28Update comment to no longer mention a page is 4KB, since this may not be theMiod Vallat
case.
2010-11-28Enable __HAVE_PMAP_DIRECT on mips64, unless the kernel is configured toMiod Vallat
run on R5000 family processors (e.g. sgi GENERIC-IP32), where direct XKPHYS mappings hit a silicon bug.
2010-11-28Allow mips64-based ports to override the default mips64 VM_PHYSSEG_STRATMiod Vallat
strategy value (BSEARCH); use BIGFIRST on loongson since there are only up to two memory segments.
2010-11-27Remove ddb single-step load and store counters. Most platforms do notMiod Vallat
implement them, and they are of questionable usefulness.
2010-11-24Floating-point emulation code for systems lacking proper FPU (i.e. Octeon),Miod Vallat
enabled by option FPUEMUL. This is pretty straightforward, except for conditional branch on FPU condition codes emulation (bc1f/bc1fl/bc1t/bc1tl instructions): unlike most RISC-with-delay-slots designs (m88k, sparc), the branch pipeline is not exposed to the kernel on Mips, therefore we can not resume a branch without losing the delay slot instruction. Some other operating systems work around this issue by emulating the delay slot instruction, but this is error-prone (and requires the kernel code to be aware of all supported instructions of the processor it is currently running on), some use dedicated breakpoints to single-step through the delay slot and then resume the branch as expected, but this causes a lot of copy-on-write allocations. This code chooses a third path, of copying the delay slot instructions to run toa special `magic' page, followed by a special trap instruction to give control back to the kernel. This makes sure the instruction will actually be run by the processor, and that no more than one page per process is wasted, regardless of the number of branches to emulate. Tested on octeon (big-endian) by syuu@ and on loongson (little-endian) by me. Note that enabling option FPUEMUL in the kernel will completely disable the hardware FPU, if there is one; there is currently no way to build a kernel supporting both hardware and software FPU, and there is no reason to change this until there is a strong need to support both.
2010-11-24Make sure ptrace_sstep(,0) actually clears breakpoints, by replacing theMiod Vallat
ptrace guts with a logic similar to what the alpha port does.
2010-11-24Implement a real pmap_proc_iflush() instead of relying on trap.c to performMiod Vallat
copious cache flushes behind our back.
2010-11-11Correctly disassemble ssnop.Miod Vallat
2010-10-27Fix a few logic errors in comparison instruction emulation: make sure theMiod Vallat
less than relation is correctly computed, and check for both operands being signaling NaNs, instead of only the first NaN found, to decide whether to raise an invalid exception or not.
2010-10-24Move build_trampoline() and setregs() to a common location for all mips ports.Miod Vallat
2010-10-24Don't short-circuit userret() when returning from trap() in the rm7000Miod Vallat
performance counter code path (which is not enabled at the moment).
2010-10-02Added octeon specific cop0 registers. ok miod@Takuya ASADA
2010-10-01Provide a WEAK_ALIAS macro in <machine/asm.h> for the few platformsPhilip Guenthe
that didn't already have one, and then immediately use it in libc's SYS.h ok miod@
2010-09-28Implement a per-cpu held mutex counter if DIAGNOSTIC on all non-x86 platforms,Miod Vallat
to complete matthew@'s commit of a few days ago, and drop __HAVE_CPU_MUTEX_LEVEL define. With help from, and ok deraadt@.
2010-09-21Better not panic in MipsEmulateBranch() if the instruction is an unspecifiedMiod Vallat
OP_BCOND subfunction.
2010-09-21Replace the old floating point completion code with a C interface to theMiod Vallat
MI softfloat code, implementing all MIPS IV specified floating point operations. Tested on R5000, R10000, R14000 and Loongson2F.
2010-09-20Make md_printins() get the printf-like function as an extra parameter, andMiod Vallat
make it visible so that md parts of the kernel can use it for debug messages.
2010-09-20cache operations for octeon. ok miod@Takuya ASADA
2010-09-20Get rid of evcount's support for arranging counters in a treeMatthew Dempsky
hierarchy. Everything attached to a single root node anyway, so at best we had a bush. "i think it is good" deraadt@
2010-09-19Overhaul ddb disassembler to recognize all MIPS IV instructions, as well asMiod Vallat
some mips64r2 instructions. Various bugfixes all over as well (conditional trap instructions do not have a delay slot, for instance).
2010-09-17Recognize MIPS IV extra FPU condition codes in MipsEmulateBranch().Miod Vallat
2010-09-17Protect a few more defines with _KERNEL checks, and also allow some of themMiod Vallat
to be visible if _STANDALONE. This will eventually be used by the upcoming new-and-improved loongson bootblocks (in the works).
2010-09-17FPU control/status register defines, and upcoming userland functionMiod Vallat
prototypes to allow control of the FPU c/sr FS field.
2010-09-17Correctly disassemble `branch likely' instructions.Miod Vallat
2010-09-17There is only one code for coprocessor BC opcodes, so don't bother to handleMiod Vallat
a second (invalid) opcode; confirmed by all mips core documentation.
2010-09-14Recognize the new sequence gcc4 uses to trap on divide by zero.Miod Vallat
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