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2010-02-13Since the TLB handler exception code is now always a trampoline to branchMiod Vallat
to the handler code in the kernel, we can use relative branches in it to make it a bit faster. Also, get rid of the tlbmiss handler and have both the tlb and xtlb refill exceptions branch to the xtlbmiss handler.
2010-02-13Since we don't use the saved ipl in pcb anymore, remove it from the structMiod Vallat
layout.
2010-02-11fuloong model defineOtto Moerbeek
2010-02-08Minimal completion support for .l.s and .l.d routines, necessary for atMiod Vallat
least the R5k and R10k family FPU which trap if the operands are too large (i.e. positive unbiased exponent > fracbits). This is quick and dirty band aid until that code is replaced with interface code to the MI kernel softfloat code.
2010-02-05Blind support for the EMTEC Gdium Liberty netbook. Per-platform configurationMiod Vallat
is moved to specific files, and a pointer to the key configuration structure is now kept in struct sys_config. bonito(4) interrupt handling is split, to allow PCI+Legacy interrupt systems (Lemote Yeelong) and PCI-only Legacy-free systems (Gdium) to coexist peacefully.
2010-02-02Skip calling smp_rendezvous if it's not necessary.Takuya ASADA
ok miod@
2010-02-02lazy FP saving on uniprocessor, just like macppc.Takuya ASADA
ok miod@
2010-02-01On Loongson 2 processors, clear the branch target buffer on userland->kernelMiod Vallat
transitions, to work around an evil horde of evil bugs in the processor's branch prediction logic. This finally makes the Lemote Yeeloong stable, and I can now spend my time looking for hair implants resellers.
2010-01-31Remove !__LP64__ bits and __LP64__ tests.Miod Vallat
2010-01-28The RA stack control bit on the loongson2 diagnostic register is not a clearMiod Vallat
but a disable bit; rename the define and keep the RA stack disabled at all times - I blame the few remaining hard freezes on it.
2010-01-28Make sure we also cause an iTLB and BTB flush on loongson processors duringMiod Vallat
regular tlb replacement, as well. Helps stability a lot, still not perfect.
2010-01-23Give little-endian fp on mips a change to be handled correctly.Miod Vallat
2010-01-22Move is_memory_range() from mips64 mem.c to a per-architecture location; thisMiod Vallat
allows /dev/kmem to access the 256MB alias of the low memory on loongson, which in turns makes procmap(8) happy.
2010-01-21*Write* to the magic Loongson2 register to invalidate iTLB and branchMiod Vallat
prediction caches, instead of *reading* it. Ahem. Blush. Yeelong lemote now run single user.
2010-01-21Use db_printf() instead of printf() in db_dump_tlb_cmd() and trapDump(), soMiod Vallat
that the output can be paused by ddb if it spans too many lines.
2010-01-18In stacktrace(), when aborting a traceback because of nonsensical pc or spMiod Vallat
value, don't print a final bogus traceback line.
2010-01-18Do not call splx() from cpu_switchto(), we are at IPL_SCHED anyway and ipl willMiod Vallat
be lowered later, by the caller. This was supposed to be harmless, but newly created processes inherit a bogus level from proc0, which in turn causes a race on MULTIPROCESSOR kernel.
2010-01-18dosoftint() being invoked at IPL_SOFTINT, don't bother checking the ipl beforeMiod Vallat
grabbing the kernel lock.
2010-01-18Define IPL_SCHED as IPL_CLOCK, not IPL_HIGH.Miod Vallat
2010-01-18In proc_trampoline(), don't spl0() if option MULTIPROCESSOR; this is alreadyMiod Vallat
done for us by proc_trampoline_mp().
2010-01-18Make trapdebug code MP-safe.Miod Vallat
2010-01-16Merge db_stack_trace_print() and stacktrace() logic, and have the formerMiod Vallat
invoke the latter to avoid duplicating code. Fix the logic by looking for `sd' instructions for register saves only, and read the whole 64-bit value then. Makes the backtraces less wrong.
2010-01-16Fix types so that the upper 32 bits of addresses of branches are correct.Miod Vallat
2010-01-14When trying to get a stack trace, consider CKSEG1 addresses as invalid, as theMiod Vallat
kernel will never use them for code or stack.
2010-01-13Do not lose ra on the first loop (regression from 1.20)Miod Vallat
2010-01-10Make sure END() matches the *{LEAF,ENTRY}() function names.Miod Vallat
2010-01-09L2 cache line is at least 64 bytes long on r10k, so use 64 byte increments toMiod Vallat
flush L2 in Mips10k_SyncCache().
2010-01-09Make interrupt depth counters per-cpu.Miod Vallat
2010-01-09Move more R5000 code behind proper #ifdef stanzas.Miod Vallat
2010-01-09Move cache information from global variables to per-cpu_info fields; thisMiod Vallat
allows processors with different cache sizes to be used. Cache management routines now take a struct cpu_info * as first parameter.
2010-01-09Define struct cpu_hwinfo, to hold hardware specific information about eachMiod Vallat
processor (instead of sys_config.cpu[]), and pass it in the attach_args when attaching cpu devices. This allows per-cpu information to be gathered late in the bootstrap process, and not be limited by an arbitrary MAX_CPUS limit; this will suit IP27 and IP35 systems better. While there, use this information to make sure delay() uses the speed information from the cpu it is invoked on.
2010-01-09Correctly check /dev/kmem offsets within directly translated segments (XKPHYSMiod Vallat
or CKSEG) against the actual physical memory segments, instead of assuming contiguous physical memory starting from zero, as this is utterly wrong on Octane (and a bit less wrong on other systems (-: )
2010-01-08Fix compile failure on MP kernel(missing P_CPU macro on mips64/mips64/context.S)Takuya ASADA
2010-01-08MP-safe FPU handling. ok miod@Takuya ASADA
2010-01-07Repair non-MULTIPROCESSOR kernel compilation.Miod Vallat
2010-01-07Make sure to update p_cpu on MULTIPROCESSOR kernels.Miod Vallat
2010-01-07Enable IPI interrrupt in trap. ok miod@Takuya ASADA
2010-01-05Dynamic allocation for ASID and ASID generation number on struct pmap. ok miod@Takuya ASADA
2010-01-03Use a split genassym.cf scheme on mips64 ports. Don't forget to rerun config(8).Miod Vallat
2010-01-01Make sure than ptrace functions never return a non-zero value in the zeroMiod Vallat
register.
2010-01-01Make sure we grab the kernel lock before invoking trapsignal().Miod Vallat
2009-12-30curcpu()->ci_curpmap added. ok miod@Takuya ASADA
2009-12-28Fix compile error caused from previous commitTakuya ASADA
2009-12-28MP-safe pmap implemented, enable IPI in interrupt handler to avoid deadlock.Takuya ASADA
ok miod@
2009-12-25Pass both the virtual address and the physical address of the memory rangeMiod Vallat
when invoking the cache functions. The physical address is needed when operating on physically-indexed caches, such as the L2 cache on Loongson processors. Preprocessor abuse makes sure that the physical address computation gets compiled out when running on a kernel compiled for virtually-indexed caches only, such as the sgi kernel.
2009-12-25Don't bother returning a value in *_InvalidateICache(), as it's supposed to beMiod Vallat
a void function.
2009-12-13bit less aggressive about hiding; ok miodTheo de Raadt
2009-12-12Protect more definitions userland doesn't need to care about with _KERNELMiod Vallat
2009-12-12Switch page size from 4KB to 16KB on R10k kernels without R5k supportMiod Vallat
(i.e. IP27 and IP30 sgi kernels).
2009-12-12Introduce various CPU_### options to enable cpu-specific code or workarounds;Miod Vallat
be sure to rerun config(8) on your kernel configuration files.
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