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2018-04-12Implement MAP_STACK option for mmap(). Synchronous faults (pagefault andTheo de Raadt
syscall) confirm the stack register points at MAP_STACK memory, otherwise SIGSEGV is delivered. sigaltstack() and pthread_attr_setstack() are modified to create a MAP_STACK sub-region which satisfies alignment requirements. Observe that MAP_STACK can only be set/cleared by mmap(), which zeroes the contents of the region -- there is no mprotect() equivalent operation, so there is no MAP_STACK-adding gadget. This opportunistic software-emulation of a stack protection bit makes stack-pivot operations during ROPchain fragile (kind of like removing a tool from the toolbox). original discussion with tedu, uvm work by stefan, testing by mortimer ok kettenis
2018-04-09Add a driver for the OCTEON cryptographic unit. It providesVisa Hankala
a hardware-accelerated implementation of several encryption and authentication algorithms for ipsec(4): AES-CBC AES-CTR AES-GCM AES-GMAC HMAC-MD5 HMAC-SHA1 HMAC-SHA2-256 HMAC-SHA2-384 HMAC-SHA2-512 Please note that the driver is currently disabled. OK deraadt@
2018-03-20Do not panic from ddb(4) when a lock requirement isn't fulfilled.Martin Pieuchot
Extend the logic already present for panic() to any DDB-related operation such that if ddb(4) is entered because of a fault or other trap it is still possible to call 'boot reboot'. While here stop printing splassert() messages as well, to not fill the buffer. ok visa@, deraadt@
2018-03-05#define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archTheo de Raadt
needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
2018-02-24Declare ci_ipl volatile to prevent the compiler from optimizingVisa Hankala
or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
2018-02-18Replace a full memory barrier with a write-write barrier. The fullVisa Hankala
barrier is overkill when forcing parameter visibility before IPIs.
2018-01-29Drop unused field `ci_ipiih'.Visa Hankala
2018-01-25Remove mutex implementations that now live in MI code.Martin Pieuchot
2018-01-25Move common mutex implementations to a MI place.Martin Pieuchot
Archs not yet converted can to the jump by defining __USE_MI_MUTEX. ok visa@
2018-01-12Unify <machine/mutex.h> a bit further.Martin Pieuchot
`mtx_owner' becomes the first field of 'struct mutex' on i386/amd64/arm64. ok visa@
2018-01-08Move SC_* defines into <machine/setjmp.h>, and rename them,Visa Hankala
so that <machine/signal.h> is not needed in setjmp.S. Suggested by kettenis@ long ago, OK deraadt@
2018-01-06Remove redundant zeroing and dead code.Visa Hankala
2018-01-04Unify <machine/mutex.h> a bit further.Martin Pieuchot
Remove `mtx_lock' from i386, add volatile before `mtx_owner' where it was missing. Inputs from kettenis@, ok visa@
2017-12-30Delete unnecessary <sys/file.h> includesPhilip Guenther
ok millert@ krw@
2017-12-20Sync C mutex implementations.Martin Pieuchot
ok kettenis@
2017-12-14fcntl(F_SETFL) invokes the FIONBIO and FIOASYNC ioctls internally, soPhilip Guenther
the memory devices (/dev/null, /dev/zero, etc) need to permit them. problem noted, tweak, and testing by jeremy@ ok deraadt@
2017-11-19Remove lock_machdep.c from amd64, i386, mips64 and sparc64.Visa Hankala
The architectures have been using the MI mplock for a while. OK deraadt@, kettenis@
2017-10-21Use MI mplock on mips64.Visa Hankala
OK mpi@
2017-10-11Try to make CPU cache size values more correct, especially on OCTEON IIVisa Hankala
and III. The logic does not look nice, but the parameters do not follow the standard config register layout anyway. Remove unnecessary default values, and assume that the Config1 and Config2 registers are available on every CPU. Tested on CN5020, CN6120, CN7130 and CN7360.
2017-09-16Make sure that `fsr' is always initialized. Non-DEBUG kernelsVisa Hankala
have not been affected. From miod@
2017-09-11Sync alpha/mips64/powerpc mutex implementations.Martin Pieuchot
No functionnal change. ok visa@
2017-09-05Move mutex, condvar, and thread-specific data routes, pthread_once, andPhilip Guenther
pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
2017-09-02Let the kernel utilize the FPU if one is available, even when theVisa Hankala
FPUEMUL option is enabled. This benefits OCTEON III systems which can run floating-point operations natively. Feedback from and OK miod@; he also helped with testing. Tested on octeon without FPU (CN5020, CN6120) and with FPU (CN7130), as well as on sgi/IP27 (MP R16000), sgi/IP32 (R5000), and loongson (3A1000).
2017-09-01Ansify function definitions.Visa Hankala
2017-09-01Zap stray prototype.Visa Hankala
2017-08-30Prefer copyin32() to copyin() when fetching instructionsVisa Hankala
from user space. This improves performance slightly. Discussed with miod@
2017-08-27Rely on the hardware to clear hazards on octeon.Visa Hankala
2017-08-26Use copyin32() instead of a direct memory load when fetching a branchVisa Hankala
instruction for branch emulation. This ensures the userspace memory access is properly guarded and that TLB faults are handled. In order not to complicate the interface of MipsEmulateBranch(), each caller now has to provide the branch instruction for the function. Feedback from miod@
2017-08-26Use macros for Config1 bits.Visa Hankala
2017-08-25Fix pmap_extract() to return false when there is a page table pageVisa Hankala
but no mapping for the input user virtual address.
2017-08-13Make R_MIPS_* defines available via <machine/reloc.h>.Visa Hankala
OK guenther@
2017-08-12Add a dummy (for now) <machine/reloc.h> for mips64 to fix build.Visa Hankala
OK guenther@
2017-07-30Define MAXCPUS per mips64 port.Visa Hankala
2017-07-22Rename variables for clarity.Visa Hankala
It does not seem necessary to provide initial value for `sicode'. When `signal' gets set, `sicode' is set as well. OK deraadt@, kettenis@
2017-07-22Bring SIGBUS and SIGSEGV handling better in line with the otherVisa Hankala
architectures. OK kettenis@, deraadt@
2017-07-12remove CPU_LIDSUSPEND/machdep.lidsuspendMartin Natano
"fire away!" tedu
2017-07-03Use copyin32() instead of copyin() in RDHWR emulation.Visa Hankala
This reduces emulation time about 5%.
2017-06-29kill RCSID macros; discussed with millertTheo de Raadt
2017-06-22Improve the coalescing of instruction cache flushes on R8000 in orderVisa Hankala
not to perform redundant work. There is no direct way to flush the cache; rather, the kernel evicts unwanted bits from the cache by executing a block of instructions, which is expensive. With this diff, make build time decreases about 0.4%. Diff from miod@
2017-06-17Invalidate remote TLB entries by address range. This reducesVisa Hankala
the number of IPIs required when removing mappings.
2017-06-13Do not invalidate remote TLB entries with new mappings because theVisa Hankala
virtual addresses really should not have TLB hits. This reduces IPIs.
2017-06-13Tweak order of operands to check constant `cache_valias_mask' first.Visa Hankala
2017-06-11Define register_splx_handler() in one place.Visa Hankala
2017-06-11Fix TLB size computation on OCTEON II and III. The CPUs have utilizedVisa Hankala
the whole TLB space even before this. However, TLB initialization on boot and TLB flush on ASID wraparound have been incomplete. These have caused crashes of processes.
2017-06-08Move loongson/octeon/sgi unmap_startup() under arch/mips64.Visa Hankala
2017-05-30Kill db_sym_t.Martin Pieuchot
ok deraadt@, kettenis@, jasper@
2017-05-29Kill SPINLOCK_SPIN_HOOK, use CPU_BUSY_CYCLE() instead.Martin Pieuchot
ok visa@, kettenis@
2017-05-29Reduce code duplication. The local-CPU-only case is now handledVisa Hankala
without a lock in smp_rendezvous_cpus().
2017-05-29Invalidate OCTEON icache after TLB ASID wraparound, otherwise userspaceVisa Hankala
might execute stale instructions. The cache is virtually tagged and does not seem to pick up TLB alterations automatically.
2017-05-28Do not allow NULL callback at rendezvous and clear callbackVisa Hankala
pointer at the end to catch errors faster.
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