summaryrefslogtreecommitdiff
path: root/sys/arch/mips64
AgeCommit message (Collapse)Author
2012-07-14Split the existing mips64 clock code into time-of-day and generic duties inMiod Vallat
machdep.c, and internal clock interrupting on level 5, still in clock.c; this will allow other clock sources to be used in the near future. (delay() will remain tied to the internal clock)
2012-07-09Do not re-initialize ci_randseed on the primary cpuTheo de Raadt
ok kettenis
2012-06-26create new machine/_float.h which is namespace clean. create a newTheo de Raadt
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-24Bring in line with current cache_r{5,10}k.c style, and optimize slightly theMiod Vallat
handling of a partial last line in IOSyncDCache. No functional change.
2012-06-24Since the RM7000 cache behaves as a physically-indexed cache due to the setMiod Vallat
size being not larger than 4KB, use Hit operations on the pa instead of Index operations on the va for each set in the SyncDCachePage routine, when running with such a cache.
2012-06-24Get the L2 line size from the configuration register instead of hardcoding theMiod Vallat
smallest possible size; and on kernels with 16KB pages, where no virtual aliasing happens, use Hit operations on the pa instead of index operations on the va for all sets in the SyncDCachePage routine. Tested by mikeb@ on IP32 and myself on IP27/28/30/35
2012-06-24Do not output unnecessary semicolons when expanding macros. No functional changeMiod Vallat
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousMiod Vallat
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-23Replace R5000 and R10000 family assembly cache routines with C equivalents,Miod Vallat
which will be easier to maintain on the long run. Be sure to rm cache_r*.d in your kernel compile directories after updating.
2012-06-23Fix ITLBNOPFIX macro definition on RM7000-capable kernels, and use itMiod Vallat
in cp0_set_config() for consistency.
2012-06-17No longer restrict alloc_contiguous_pages() to memory in the low 4GB.Miod Vallat
2012-06-17Using the LLAddr register to store our curcpu() pointer on R10k SMP kernelsMiod Vallat
was a nice trick, but this register is only 32-bit wide and will be sign-extended, which requires all cpu_info structs to be allocated within 2GB physical - something which may not be possible on some configurations. This diff changes IP30.MP kernels to no longer use LLAddr to store curcpu, but use unused fields of the MPConf structure in low memory, indexed with the physical processor id, which can be obtained from the Heart PRID register.
2012-05-27Add a `L2 cache line size' member to struct cpu_info. This allows R4k code toMiod Vallat
stop abusing another field, and will be used by more routines RSN. No functional change.
2012-05-27Replace Loongson2F assembly cache routines with equivalent C code. This willMiod Vallat
make future maintainance easier.
2012-05-17Correct virtual aliasing mask computation.Miod Vallat
Note that this would only affect 4KB page size IP22 kernels, which is not the default IP22 configuration, and which noone not out of his or her mind would do. In other words: this is a correctness fix with no impact on Real Life (c)(R)TM
2012-05-10The uvm_map() changes introduced about two months ago yield a differentMiod Vallat
memory allocation pattern, exposing aliasing bugs in the mips64 pmap, on kernels where virtual aliasing may happen (that is, IP32 kernels on R5000, R10000 and R12000 O2). Fix these (or at least, sweep them better under the rug) by: - always flush caches in pmap_copy_page() and pmap_zero_page(), if the destination page is mapped uncached. - when removing a mapping of a managed page which has been forced uncached due to virtual aliasing conflict, map it back cached as soon as the remaining mappings are non conflicting. - writeback, instead of simply invalidating, pool pages and page table pages, upon release, for there might be stale data in the cache. While these, apply more paranoia and only perform cache operations on pages which have been mapped with the cache enabled. Initially reported by mikeb@ on an R12k O2 (that will teach me to use an RM7000-powered O2, without virtual aliasing, to test IP32 kernels). Verified on an R5k O2, as well as a custom IP30 kernel with page size forced to 4KB (to introduce virtual aliasing). This diff tested on O2 (R5k, RM7k, R12k), IP30, IP35, as well as on Loongson (no aliasing) by mikeb@ and I.
2012-04-25Skip cache flushes in pmap_zero_page() and pmap_copy_page() on systemsMiod Vallat
without virtual aliasing, or for pages which are not currently mapped cached. 1+% speed increase on sgi IP27 and loongson kernels. Tested on LS2F, R4400, R5000, R12000 and R16000.
2012-04-24Harvest some low-hanging fruit in thu R5k/RM7k cache routines:Miod Vallat
- replace masking with large `power of two minus one' constants with a pair of shifts, this is shorter code and does not require the at register. - merge R5000 and RM52xx setup, as the configuration register layout is the same on both processors. - In Mips5k_IOSyncDCache(), delay building the call frame until we know we will not perform a leaf call. Replace leaf calls with jumps to the appropriate routines. Tested on R5000, RM5271 and RM7000.
2012-04-24Add support for wired mappings, using the last unused bit in the PTE.Miod Vallat
2012-04-24Introduce a #define for the number of PFN bits in a pte, to be used in theMiod Vallat
.S code when masking the upper bits, instead of hardcoding them. Makes code easier to understand (and also I might have a need to reduce PFN width on some particular CPU models in the future). No change in generated code.
2012-04-21Correct a wrong comment.Miod Vallat
2012-04-21Rework the signature of the cache handling routines again. It makes more senseMiod Vallat
to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.
2012-04-19Print the currently active ASID in `machine tlb' ddb command.Miod Vallat
2012-04-19Be sure to update the currently active ASID in pmap_activate() if invoked onMiod Vallat
behalf of curproc.
2012-04-16Move proc0 and trap handler setup before consinit(), but still wait for theMiod Vallat
initial setup to be complete before switching to our trap handlers. However, change guarded_{read,write}_* to clear BEV in the coprocessor 0 status register, and restore it afterwards, to use our fault handlers within these functions. This makes these functions usable from consinit().
2012-04-16Fix struct arc_param_blk_* layout to not embed pointers, as this messes theMiod Vallat
layout in 64-bit mode. Found the hard way, of course.
2012-04-15Tell Indy and Challenge S apart.Miod Vallat
2012-04-11The first ktrace record for a newly spawned thread is a returnMike Belopuhov
from a fork syscall done by the parent. Use __tfork, not rfork here to match the ktrace records for the parent (CALL __tfork, RET __tfork). ok guenther
2012-04-10Count traps and fpu context switches.Miod Vallat
2012-04-09No need to round VCEI addresses, and VCED addresses only need to be roundedMiod Vallat
to a word boundary.
2012-04-09More errata bandaid for the R4000SC is necessary in the tlb handlers.Miod Vallat
2012-04-06Make the logic for PMAP_PREFER() and the logic, inside pmap, to do theMiod Vallat
necessary cache coherency work wrt similar virtual indexes of different physical pages, depending upon two distinct global variables, instead of a shared one. R4000/R4400 VCE requires a 32KB mask for PMAP_PREFER, which is otherwise not necessary for pmap coherency (especially since, on these processors, only L1 uses virtual indexes, and the L1 size is not greater than the page size, as we are using 16KB pages).
2012-04-06Rework IP22 RTC year base computation, again. It turns out that differentMiod Vallat
Indy PROM versions use different year bases - after all, using 1970 instead of the previously used value of 1940 smelled like a bug, and probably was, so this eventually got fixed in later PROM versions. Instead of hardcoding a year base depending upon the system, we will now ask ARCBios for its current year, and compare it to what can be read from the RTC registers to figure out what year base is in use by the PROM.
2012-03-28Work in progress support for the SGI Indigo, Indigo 2 and Indy systemsMiod Vallat
(IP20, IP22, IP24) in 64-bit mode, adapated from NetBSD. Currently limited to headless operation, input and video drivers will get ported soon. Should work on all R4000, R4440 and R5000 based systems. L2 cache on R5000SC Indy not supported yet (coming soon), R4600 not supported yet either (coming soon as well). Tested to boot multiuser on: Indigo2 R4000SC, Indy R4000PC, Indy R4000SC, Indy R5000SC, Indigo2 R4400SC. There are still glitches in the Ethernet driver which are being looked at. Expansion support is limited to the GIO E++ board; GIO boards with PCI-GIO bridges not ported yet due to the lack of hardware, and this kind of driver does not port blindly. Most of this work comes from NetBSD, polishing and integration work, as well as putting as many ``R4x00 in 64-bit mode'' erratas as necessary, by yours truly. More work is coming, as well as trying to get some easy way to boot install kernels (as older PROM can only boot ECOFF binaries, which won't do for the kernel).
2012-03-25Move cache handling routines related definitions to a dedicated header file,Miod Vallat
rather than abusing <machine/cpu.h>.
2012-03-25Only set the low order bits of CpuCacheAliasMask if it is nonzero, regressionMiod Vallat
of previous computation fix.
2012-03-24Fix fallback of uvm_map_hint() argument changes.Miod Vallat
2012-03-24Oops, forgot this file in the SGI_<model> -> SGI_IP## change.Miod Vallat
2012-03-24The various ConfigCache() functions actually return void, not int.Miod Vallat
2012-03-24Rename the various SGI_xxx constants from machine names to their IP numbers,Miod Vallat
for IP numbers under 30 (Octane), and add a few interesting ones. No functional change, except making my life easier for upcoming work.
2012-03-24Add a few trivial routines to get mips64r2 specific config registers. Not usedMiod Vallat
by anything yet, but has been lying in one of my trees for too long.
2012-03-19On sgi, use CKSEG0 addresses whenever possible for pmap_map_direct and u areaMiod Vallat
pages. This will allow R5000-based systems with physical memory fitting in CKSEG0 to use 16KB pages and direct maps (since only XKPHYS accesses trigger the XKPHYS coherency errata on these processors). Tested on IP32, IP30 and IP27 (and loongson too as well).
2012-03-19Recent uvm code (and maybe not-so-recent, but it did not explode^WKASSERT atMiod Vallat
my face then...) depends upon PMAP_PREFER_ALIGN to be a power of two, minus one. On mips64 with 4KB pages, the runtime variable used to compute PMAP_PREFER_ALIGN had the low PAGE_SHIFT bits zeroed (for no good reason I'd say). Don't bother zeroing them anymore.
2012-03-19Use uncached addresses for all exception vectors, when copying our code (orMiod Vallat
trampolines) to them; this makes sure there is no risk of pending writes being lost when we clear the caches. Of course, this would be a bug in the cache handling routines, but having our vectors correctly set will help debugging the issue. Tested on sgi and loongson.
2012-03-15uncached_base was introduced early in IP27 support, since these designs useMiod Vallat
subspaces in the CCA_NC uncached memory space. However, being coherent, there was never a need for bus_dma to use uncached addresses. This means that, on the only systems where uncached_base was not set to PHYS_TO_XKPHYS(0, CCA_NC), it was never used. Remove the variable, and replace PHYS_TO_UNCACHED() with PHYS_TO_XKPHYS(, CCA_NC). No functional change.
2012-02-16Do an explicit `sync' instruction before returning from cache routines; this isMiod Vallat
a nop on R5k and RM52xx, but actually required on RM7k.
2012-02-16Be sure to reset coprocessor 0 TAG_LO register to zero before attemptingMiod Vallat
InvalidatePage_* cache operations on RM52xx and RM7k, as strongly recommended by the manual.
2012-02-16Use abbreviated mnemonics whenever possible (e.g. beqz instead of beq ...,zero),Miod Vallat
fix various typos in comments, harmonize a few of them, and rename the internal InvalidateSecondaryPage define to InvalidatePage_S for consistency. No change in generated code.
2011-11-16Make userret() MI. On architectures which jammed stuff into it in theTheo de Raadt
past, pull that code out seperately. ok guenther miod
2011-11-15label_t is the kernel setjmp buffer. It should simply be an array ofTheo de Raadt
the right type, noone will ever fiddle with the internals. discussed with jsing
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-26 20:08:26 +0000