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or'ed together, even on platforms where bus_space_barrier() ignores the
barrier argument yet.
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bus_space_alloc() as a bitmask of flags, and not a boolean controlling
cacheability; and make sure the three MI BUS_SPACE_MAP_xxx values documented
in the manual page are defined on all platforms as well.
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other BUS_DMA_xxx flag names, and nothing uses it.
ok many@
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Saves every damned driver calling bzero(), and continues the M_ZERO,
PR_ZERO symmetry.
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with different locking mechanism. 88110 soft ipi are replaced with an
ipi callback which is checked upon return from exception (it can not be kept
as a softintr, as the generic softinterrupt code doesn't have per-cpu
pending softintr queues).
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possible from the exception, without doing the AST and softintr dance.
This should avoid too much stack usage under load.
ok deraadt@
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to disable NMI sources in addition to interrupt sources, and we can not
use a quick sequence with shadowing frozen as done for atomic ops.
This lets GENERIC.MP boot multiuser on MVME197DP boards, and is so far stable
enough to be able to recompile a kernel from scratch (with make -j2).
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- dma_cachectl() split into a ``local cpu only'' and ``all cpus'', and an ipi
to broadcast ``local dma_cachectl'' is added.
- cpu_info fields are rearranged, to have the 88100-specific information
and the 88110-specific information overlap, and has many more 88110
ugly things.
- more ipi handling in the 197-specific area. Since it is not possible to
have the second processor receive any hardware interrupt (selection
is done on a level basis via ISEL, and we definitely do not want the
main cpu to lose interrupts), the best we can do is to inflict ourselves
a soft interrupt for late ipi processing. It gets used for softclock and
hardclock on the secondary processor, but since the soft interrupt
dispatcher doesn't have an exception frame, we have to remember parts
of it to build a fake clockframe from the soft ipi handler (ugly but
works).
This now lets GENERIC.MP run a few userland binaries before bugs trigger.
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from interrupt() and related function pointers.
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different from regular hardware interrupts to be worth handling the
same way.
Disable IPI reception while we are handling pending IPIs. And do not
reenable them by mistake if we need to send an IPI in return.
This lets GENERIC.MP boot single user on a MVME197DP. There are still
many bugs to fix.
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addition to the kernel, and unconditionnaly handle all busswitch revision 1
based boards as horribly broken, even with 50MHz clocks.
Based on an report of an early 50MHz 197LE board being unable to boot,
due to memory corruption.
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Not sure what's more surprising: how long it took for NetBSD to
catch up to the rest of the BSDs (including UCB), or the amount of
code that NetBSD has claimed for itself without attributing to the
actual authors.
OK deraadt@
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non-VME syscon interrupt sources will now use their own intrhand array,
and interrupt sources will be enabled in the arbiter as interrupt handlers
are registered. This allows VME devices to use the whole 256 interrupts range.
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preserved across BUG calls, but on the other hand the last 16 traps need to
be restored to BUG values, not only trap #496.
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invalidate tlb ipis, and turn them into simple ``handle once'' ipis.
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more work in progress to handle these exceptions correctly, and document
a new undocumented and evil chip bug while there.
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an IPI facility, for MVME197DP.
It's still missing a few remote cache IPIs and IPI do not seem to be reliably
triggered on remote processors at the moment (but this could be a problem
on the board I am currently testing on), at least it will boot multiuser
using only cpu0 to schedule processes.
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x86 __mp_lock changes, but keeping the internal __cpu_simplelock_t to
guarantee atomic access to the __mp_lock fields.
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code. At this moment all architectures get the copy of the old code
except i386 which gets a new shiny implementation that doesn't spin
at splhigh (doh!) and doesn't try to grab the biglock when releasing
the biglock (double doh!).
Shaves 10% of system time during kernel compile and might solve a few
bugs as a bonus.
Other architectures coming shortly.
miod@ deraadt@ ok
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combos (MVME197SP/DP), and implement supposedly smarter cache routines.
There is still room for improvement, however, cache flush operation errata
permissing.
Tested on 197LE and 197DP.
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whenever necessary, instead of duplicating the same code 10+ times.
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appropriate types. No functional change.
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one, so that we can have maskable and unmaskable IPIs. Make the clock ipis
maskable, and masked at IPL_CLOCK and above. This allows us to get rid
of the retrig hack in setipl().
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cpu_disklabel can go away, since nothing anymore needs to use it; ok miod
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to support hotplug media on most architectures. disklabel setup and
verification done using new helper functions. Disklabels must *always*
have a correct checksum now. Same code paths are used to learn on-disk
location disklabels, to avoid new errors sneaking in. Tested on almost all
cases, testing help from todd, kettenis, krw, otto, dlg, robert, gwk, drahn
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lowering the spl.
Also, warn and halt in tracks if the interrupt pin of a secondary cpu never
clears (found the hard way in one of the 2P256 modules here), since there is
nothing better we can do.
Last, do not attempt to handle VME interrupts on secondary processors yes
(this confuses the bus, since both processors will perform a VME interrupt
acknowledge sequence, but only one will succeed).
This lets processes correctly run on all the available processors in
single-user mode, but there are still issues to sort out.
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device_register() function -- even if it does nothing. reduces the
cpp-based blather different between architectures
idea ok'd by miod; tested on all architectures (except a few miod will
need to cleanup because he has them)
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send clock ticks to secondary processors.
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as no more than one interrupt is registered for a given level.
Then, if the VME interrupt vector reading cycle fails on the 188 interrupt
arbiter, we can use this table as a hint if it has a valid entry, since
we know on which ipl line the interrupt occured.
This basically silences the
m188_ext_int: timeout getting VME interrupt vector, level 3, mask 0x400<IRQ3>
occasional messages appearing when the MVME376 is overloaded.
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rt and such; tested and ok miod drahn
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right now that are supposed to be atomic with respect to interrupts and
SMP: atomic_setbits_int and atomic_clearbits_int.
All architectures other than i386 and amd64 get dummy implementations
since at first we'll be replacing operations that are done with
"a |= bit" and "a &= ~bit" today. More proper implementations will follow
kettenis@, miod@ ok
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in its exception-related contents and pcb-related contents.
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independent subfunctions, turn PFSR_SAVE into a couple of NOP, and replace
them early at runtime with a branch to the selected routine, which will
return to pfsr_save.
This is really better for 188 systems.
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off kernel_map whenever necessary.
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fewer assembly statements and much less magic, a few display artefacts
removed, and private definitions moved out of the main prom.h.
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With a few prototype declarations shuffling, this finally allows
<machine/locore.h> to die.
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factorize the build of the VBR page betweem luna88k and mvme88k.
Tested by aoyama@ and I.
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